JPH01100644A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPH01100644A
JPH01100644A JP26008687A JP26008687A JPH01100644A JP H01100644 A JPH01100644 A JP H01100644A JP 26008687 A JP26008687 A JP 26008687A JP 26008687 A JP26008687 A JP 26008687A JP H01100644 A JPH01100644 A JP H01100644A
Authority
JP
Japan
Prior art keywords
signal
storage device
circuit
recording
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26008687A
Other languages
Japanese (ja)
Inventor
Hirotoshi Yamamoto
博俊 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP26008687A priority Critical patent/JPH01100644A/en
Publication of JPH01100644A publication Critical patent/JPH01100644A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To widely reduce the capacity of a storage device by erasing storage contents before the writing of a signal in a writing period, erasing the storage contents after the reading of the signal in a reading period and shortening an action process. CONSTITUTION:A change-over switch 16 switches signals A and B by a signal C to show whether the action condition of a recording/reproducing device 15 is a recording or a reproducing and leads them out to an erasing circuit 12. At the time of the recording action of the device 15, the signal A is inputted to the circuit 12, the circuit 12 starts an erasing action in accordance with this signal A. On the other hand, the signal recorded in a recording medium 7 is read out by a magnetic head 6 and given to a demodulating circuit 9 through an amplifying circuit 8. The signal demodulated by this circuit 9 is stored into a device 2 and the correction of an error or the interpolation of the signal is executed in accordance with an correction signal added by an error correcting circuit 10. The signal to which a processing like this is executed is converted into an analog signal by a D/A converter and reproduced.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、たとえば記録媒体に記憶装置を介してデジタ
ル信号が記録/再生される記録/再生装置、すなわちい
わゆるデジタルオーディオテープ(DAT)などのパル
スコードモデュレーション(PCM)信号記録/再生装
置やコンパクトディスク再生装置等に用いられる記憶装
置において好適に実施される記憶装置の制御方式に関す
る。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a recording/reproducing apparatus in which digital signals are recorded/reproduced on a recording medium via a storage device, that is, a pulse code such as a so-called digital audio tape (DAT). The present invention relates to a storage device control method suitably implemented in a storage device used in a modulation (PCM) signal recording/reproducing device, a compact disc reproducing device, and the like.

従来技術 従来から、たとえばPCM信号記録/再生装置などにお
いてデータの時間的な圧縮を行わない場合には、磁気テ
ープなどの記録媒体に記録されたデジタル信号は磁気ヘ
ッドで読出され、後述するように4つのメモリなどの記
憶装置に記憶されて、信号処理が施される。前記4つの
記憶装置から順次出力される信号はアナログ信号に変換
されてスピーカで音響化される。
BACKGROUND ART Conventionally, when data is not temporally compressed in, for example, a PCM signal recording/reproducing device, a digital signal recorded on a recording medium such as a magnetic tape is read out by a magnetic head, as described below. The signals are stored in storage devices such as four memories, and subjected to signal processing. The signals sequentially output from the four storage devices are converted into analog signals and audible by a speaker.

通常、記録媒体への記録においてはインクリーブと称さ
れる方式によって、デジタル信号は時間的に順序が分散
されて、つまり配列位置が変更される。したがって再生
時には配列を元通りに戻さなければならない。このため
にはインタリーブが完結するまでの信号を記憶装置に記
憶する必要がある。
Normally, when recording on a recording medium, the order of digital signals is temporally dispersed, that is, the arrangement position is changed by a method called increment. Therefore, during playback, the array must be restored to its original state. For this purpose, it is necessary to store the signals until interleaving is completed in a storage device.

また記憶装置は入力および出力などを同時に行うことが
できないので、音声出力などの連続的な信号の入出力が
必要なときにはいくつかの記憶装置を交代で切換えて用
いて、どれか1つの記憶装置からは必ず信号が入力また
は出力されるように動作させる。
Furthermore, storage devices cannot perform input and output simultaneously, so when continuous signal input/output such as audio output is required, several storage devices are switched and used in turn, and only one storage device is used. Operate so that a signal is always input or output from.

第4図および第5図は記録/再生装置の記憶装置におい
て従来から行われている典型的な制御方式を説明するた
めの図である。第4図は記録/再生装置の記録動作時に
おける記憶装置の動作を示し、以下同図を参照して説明
する。
FIGS. 4 and 5 are diagrams for explaining a typical control method conventionally used in a storage device of a recording/reproducing apparatus. FIG. 4 shows the operation of the storage device during the recording operation of the recording/reproducing apparatus, and will be described below with reference to the same figure.

記憶装置は、アナログ/デジタル変換器(以下、A/D
変換器と略称する)からのデジタル信号の入力(書込み
動作)、訂正符号の付加などの信号処理(訂正符号付加
動作)、記録媒体に記録を行うための信号出力(続出し
動作)および記憶装置の記憶内容の消去(初期化動作)
という4つの工程に分けられて動作される。
The storage device is an analog/digital converter (hereinafter referred to as A/D
Input of digital signals from converters (abbreviated as converters) (writing operation), signal processing such as adding correction codes (correction code addition operations), signal output for recording on recording media (continuous operation), and storage devices Erasing the memory contents (initialization operation)
The operation is divided into four steps.

したがって、連続的にA/D変換器がらの信号が書込ま
れるには4つの記憶装置MRI〜MR4が必要となる。
Therefore, four memory devices MRI to MR4 are required to continuously write the signals from the A/D converters.

記憶装置MRI−MR4においては第4図(1)〜同図
(4)に示されるような動作がそれぞれ行われる。たと
えば記憶装置MRIでは期間TAには初期化動作が行わ
れ、期間TB。
In the storage device MRI-MR4, the operations shown in FIGS. 4(1) to 4(4) are performed. For example, in a storage device MRI, an initialization operation is performed during a period TA, and an initialization operation is performed during a period TB.

TC,TDには書込み動作、訂正符号付加動作、読出し
動作がそれぞれ行われ、このような動作が繰返される。
A write operation, a correction code adding operation, and a read operation are respectively performed on the TC and TD, and these operations are repeated.

記憶装置MR2は期間TA、TB、TC,TDには書込
み動作、訂正符号付加動作、読出し動作、初期化動作が
それぞれ行われ、このような動作が繰返される。すなわ
ち記憶装置MR2は記憶装置MRIの動作と同様の動作
を予め定める期間だけ先行して行う。
In the storage device MR2, a write operation, a correction code addition operation, a read operation, and an initialization operation are performed during periods TA, TB, TC, and TD, and these operations are repeated. That is, the storage device MR2 performs the same operation as the storage device MRI in advance for a predetermined period.

記憶装置MR3は記憶装置MR2の動作に一定期間先行
して同様の動作を行う。また記憶装置MR4は記憶装置
MR3の動作にさらに一定期間先行して同様の動作を行
う。すなわち同一期間には−3〜 記憶装置MRI〜MR4は、それぞれ異なる動作をする
。したがって各期間においていずれか1つの記憶装置で
は書込み動作が行われ、この記憶装置とは異なる1つの
記憶装置では読出し動作が行われる。こうして書込みお
よび読出し動作は連続的に行われる。
The storage device MR3 performs a similar operation for a certain period of time prior to the operation of the storage device MR2. Furthermore, the storage device MR4 performs a similar operation for a certain period of time prior to the operation of the storage device MR3. That is, during the same period, the storage devices MRI to MR4 operate differently. Therefore, in each period, a write operation is performed in one of the storage devices, and a read operation is performed in one storage device different from this storage device. In this way, write and read operations are performed continuously.

第5図は前述した記録/再生装置の再生動作時における
記憶装置の動作を示し、以下同図を参照して説明する。
FIG. 5 shows the operation of the storage device during the reproducing operation of the recording/reproducing apparatus described above, and will be described below with reference to the same figure.

再生動作において記憶装置MRI〜MR4は4つの工程
、すなわち記憶内容の消去(初期化動作)、記録媒体か
らの入力(書込み動作)、付加された誤り訂正符号に従
った書込まれた信号の誤りの訂正などの信号処理(訂正
動作)およびデジタル/アナログ変換器(以下、D/A
変換器と略称する)等への出力(読出し動作)を行う。
In the reproduction operation, the storage devices MRI to MR4 undergo four steps: erasing the stored contents (initialization operation), inputting from the recording medium (writing operation), and error correction of the written signal according to the added error correction code. signal processing such as correction (correction operation) and digital/analog converter (hereinafter referred to as D/A
(abbreviated as a converter), etc. (read operation).

記憶装置MR1〜MR4の書込みおよび読出しが連続的
に行われるように、各記憶装置は予め定められる期間だ
けずれて同様な動作を行う。
Each memory device performs similar operations at predetermined intervals so that writing and reading from the memory devices MR1 to MR4 are performed continuously.

たとえば記憶装置MRIは期間TAIにおいて初期化動
作が行われ、期間TBI、TCI、TD1においては書
込み動作、訂正動作、読出し動作がそれぞれ行われ、こ
のような動作が繰返される。
For example, in the storage device MRI, an initialization operation is performed during the period TAI, and a write operation, a correction operation, and a read operation are performed during the periods TBI, TCI, and TD1, and these operations are repeated.

記憶装置MR2は記憶装置MHIより一定期間先行して
同様の動作を行うので、期間TAIには書込み動作が行
われる。このようにたとえば期間TAIにおいては記憶
装置MR,2において書込み動作が行われ、記憶装置M
R4において読出し動作が行われる。期間TB1におい
ては記憶装置MR1,MR3において書込み動作、読出
し動作がそれぞれ行われる。このようにして、記憶袋g
MR1〜MR4において交代で書込みおよび読出しが行
われ、連続的な書込み、読出しが可能となる。
Since the storage device MR2 performs a similar operation a certain period of time ahead of the storage device MHI, a write operation is performed during the period TAI. In this way, for example, during the period TAI, a write operation is performed in the memory device MR,2, and the memory device M
A read operation is performed in R4. During the period TB1, a write operation and a read operation are performed in the memory devices MR1 and MR3, respectively. In this way, memory bag g
Writing and reading are performed alternately in MR1 to MR4, allowing continuous writing and reading.

発明が解決しようとする問題点 近年、ランダムアクセスメモリ(RAM)などの記憶装
置は安価になってきている。しかしながらデジタル技術
の進歩とともに、たとえば音響再生装置においては音質
の向上のために2倍あるいは4倍オーバサンプリングな
どと称される方法が用いられるなど記憶装置には大容量
と高速応答・性とが要求されるようになってきている。
Problems to be Solved by the Invention In recent years, storage devices such as random access memory (RAM) have become cheaper. However, with the advancement of digital technology, for example, methods called 2x or 4x oversampling are used in sound reproduction equipment to improve sound quality, and storage devices are required to have large capacity and high-speed response. This is becoming more and more common.

このような要求に答える記憶装置は一般に高価であり、
このことが装置全体のコストアップを招来してしまう。
Storage devices that meet these demands are generally expensive;
This results in an increase in the cost of the entire device.

したがって装置全体の性能を損わずに記憶装置を削減す
ることができる制御方式が強く要望されていた。
Therefore, there has been a strong demand for a control system that can reduce the number of storage devices without impairing the performance of the entire device.

本発明の目的は、上記問題点を解決し、性能を損わず記
憶装置の容量の大幅な削減が可能であり、なおかつその
ための追加回路をほとんど必要としない記憶装置の制御
方式を提供することである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a storage device control method that solves the above-mentioned problems, allows a significant reduction in the capacity of a storage device without degrading performance, and requires almost no additional circuitry for this purpose. It is.

問題点を解決するための手段 本発明は、デジタル信号が書込まれ、また読出される記
憶装置と、 該記憶装置の記憶内容が消去されるアドレスを出力する
アドレス指定手段とを含み、 前記記憶装置への書込み動作時には書込まれるアドレス
をアドレス指定手段によって指定して書込み動作に先立
って記憶内容を順次的に消去し、前記記憶装置からの読
出し動作時には記憶内容が読出されたアドレスをアドレ
ス指定手段によって指定して記憶内容を順次的に消去し
、これら書込み動作時または読出し動作時において、記
憶内容の消去動作の少なくともいずれか一方を選択する
ようにしたことを特徴とする記憶装置の制御方式である
Means for Solving the Problems The present invention includes: a storage device into which digital signals are written and read; and addressing means for outputting an address at which the storage contents of the storage device are to be erased; During a write operation to the device, an address to be written is specified by an addressing means to sequentially erase the memory contents prior to the write operation, and during a read operation from the storage device, an address from which the memory contents were read is specified as an address. A control method for a storage device, characterized in that the storage contents are sequentially erased by designating means, and at least one of the storage contents erasing operations is selected during a write operation or a read operation. It is.

作  用 本発明に従えば、記憶装置l\の書込み動作時にアドレ
ス指定手段によって指定されるアドレスに対して行われ
る書込み動作に先立つ記憶内容の消去動作と、記憶装置
からの読出し動作時にアドレス指定手段によって指定さ
れるアドレスに対して行われる読出し動作に遅れて行わ
れる記憶内容の消去動作との少なくともいずれか一方が
選択されて行われる。したがって大容量の信号の書込み
あるいは読出しを行う記憶装置において書込みあるいは
読出し動作が行われる期間に記憶装置の消去を同時処理
することができ、このため記憶装置の動作工程が短縮さ
れる。
According to the present invention, the erasing operation of the memory contents prior to the write operation performed to the address specified by the address specifying means during the write operation of the memory device l\, and the address specifying means during the read operation from the memory device At least one of the read operation performed on the address designated by and the erase operation of the stored contents performed with a delay is selected and performed. Therefore, erasing of the memory device can be performed simultaneously during a writing or reading operation in a memory device that writes or reads a large capacity signal, thereby shortening the operation process of the memory device.

実施例 第1図は本発明の一実施例である記録/再生装置15の
構成を示すブロック図である。記録/再生装W 15は
アドレス指定手段である消去回路12と記憶装置2と切
換スイッチ16とを含んで構成される。
Embodiment FIG. 1 is a block diagram showing the configuration of a recording/reproducing apparatus 15 which is an embodiment of the present invention. The recording/reproducing device W 15 includes an erasing circuit 12 serving as an address specifying means, a storage device 2, and a changeover switch 16.

この記録/再生装置15はアナログ信号をデジタル信号
に変換して記憶装置2に記憶し、後述する信号処理を施
して磁気テープ等の記録媒体7に記録する。また記録媒
体7に記録された信号を読出して記憶装置2に記憶し、
後述する信号処理を施してアナログ信号に変換、再生す
る。
This recording/reproducing device 15 converts an analog signal into a digital signal, stores it in the storage device 2, performs signal processing to be described later, and records it on a recording medium 7 such as a magnetic tape. Further, the signal recorded on the recording medium 7 is read out and stored in the storage device 2,
The signal is processed to be described later to convert it into an analog signal and reproduce it.

たとえば音響信号などのアナログ信号はA/D変換器1
によってデジタル信号に変換される。このデジタル信号
は3つの記憶装置2a、2b、2Cから構成される装置 されたデジタル信号は訂正符号付加回路3によって、バ
リティなどと称される誤りの訂正あるいは信号の補間な
どを行うための訂正符号が付加される。この後、記憶さ
れた信号は変調回路4に出力されて変調され、駆動回路
5を介して磁気ヘッド6に与えられ、記録媒体7に記録
される。
For example, an analog signal such as an acoustic signal is sent to the A/D converter 1.
is converted into a digital signal by This digital signal is stored in a device consisting of three storage devices 2a, 2b, and 2C.The digital signal is processed by a correction code adding circuit 3, which adds a correction code to perform error correction called parity or signal interpolation. is added. Thereafter, the stored signal is outputted to the modulation circuit 4 and modulated, applied to the magnetic head 6 via the drive circuit 5, and recorded on the recording medium 7.

切換スイッチ16は記録/再生装置15の動作状態が再
生動作であるか記録動作であるかを表わす信号Cに従っ
て信号A,Bを切換えて消去回路12に導出する。たと
えば記録/再生装置15の記録動作時には信号Aが消去
回路12に入力され、消去回路12はこの信号Aに従っ
て消去動作を開始する。
The changeover switch 16 switches the signals A and B in accordance with the signal C indicating whether the operating state of the recording/reproducing device 15 is a reproducing operation or a recording operation, and outputs the signals A and B to the erasing circuit 12. For example, during a recording operation of the recording/reproducing device 15, a signal A is input to the erasing circuit 12, and the erasing circuit 12 starts an erasing operation in accordance with this signal A.

記録媒体7に記録された信号は磁気ヘッド6によって読
出され、増幅回路8を介して復調回路9に与えられる。
The signal recorded on the recording medium 7 is read by the magnetic head 6 and is applied to the demodulation circuit 9 via the amplifier circuit 8.

復調回路9において復調された信号は記憶装置2に記憶
され、誤り訂正回路10によって付加されている訂正符
号に従って誤りの訂正あるいは信号の補間が行われる。
The signal demodulated by the demodulation circuit 9 is stored in the storage device 2, and error correction or signal interpolation is performed according to the correction code added by the error correction circuit 10.

このような処理が施された信号はD/A変換器11によ
って、アナログ信号に変換されて再生される。再生動作
時においては切換スイッチ16によって信号Bが消去回
路12に導出され、消去回路12は信号Bに従って消去
動作を開始する。
The signal subjected to such processing is converted into an analog signal by the D/A converter 11 and reproduced. During the reproducing operation, the changeover switch 16 outputs the signal B to the erasing circuit 12, and the erasing circuit 12 starts the erasing operation in accordance with the signal B.

第2図は記録動作時における記憶装置2の動作を示す図
であり、第2図(1)〜同図(3)は、記憶装置2a、
2b、2cの動作をそれぞれ示している。
FIG. 2 is a diagram showing the operation of the storage device 2 during recording operation, and FIGS. 2(1) to 2(3) show the storage device 2a,
The operations of 2b and 2c are shown respectively.

3つの記憶装置2a、2b、2cでは各期間においてそ
れぞれ異なる動作が行われ、書込み、すなわちA/D変
換器1からの入力動作と、読出し、すなわち記憶された
信号を変調回路4および駆動回路5を介して磁気ヘッド
6に出力し、記録媒体7へ記録を行う動作とが記憶装置
2において連続して行われるように制御される。
The three storage devices 2a, 2b, and 2c perform different operations in each period, such as writing, that is, inputting the signal from the A/D converter 1, and reading, that is, inputting the stored signal to the modulation circuit 4 and the drive circuit 5. The storage device 2 is controlled so that the operations of outputting the signal to the magnetic head 6 through the magnetic head 6 and recording on the recording medium 7 are performed continuously in the storage device 2 .

たとえば記憶袋fit 2 aにおいては、期間T1で
書込み動作が行われ、期間T5で訂正符号付加動作が行
われる。この後マージン期間TMIの経過を持って期間
T4で読出し動作が行われる。
For example, in the memory bag fit 2 a, a write operation is performed during period T1, and a correction code addition operation is performed during period T5. Thereafter, a read operation is performed in a period T4 after a margin period TMI has elapsed.

このとき期間T4にわずかに遅れて始まる期間T3にお
いて初期化動作が行われる。この初期化動作は、切換ス
イッチ16を介して消去回路12に導出され、第2図(
4)に示される信号Aの立上りで開始される。消去回路
12は読出しを終えた信号のアドレスを順次指定、消去
して、いわゆる初期化を行う。
At this time, the initialization operation is performed in a period T3 that starts slightly after the period T4. This initialization operation is led out to the erasing circuit 12 via the changeover switch 16, and is performed as shown in FIG.
It starts at the rising edge of signal A shown in 4). The erase circuit 12 sequentially specifies and erases the addresses of signals that have been read out, thereby performing so-called initialization.

読出し動作の終了後にも記憶内容の消去が必要であるが
、読出し動作期間T4の後にはマージン期間TM2があ
り、次の書込み動作が行われる前、すなわちこのマージ
ン期間TM2内において初期化動作が終了するために、
実質的な時間の遅れは起こらない。
Although it is necessary to erase the memory contents even after the read operation ends, there is a margin period TM2 after the read operation period T4, and the initialization operation ends before the next write operation is performed, that is, within this margin period TM2. In order to
No substantial time delay occurs.

記憶装置2t+、2cについても上述した記憶装置2a
と同様な動作が一定期間ずつずれて行われる。したがっ
てたとえば期間T1においては書込み動作は記憶装置2
aについて行われ、期間T2においては記憶装置2Cに
ついて行われ、期間T3においては記憶装置2bについ
て行われ、このような動作が繰返される。読出し動作に
ついても同様に記憶装置2a〜2Cにおいて交代で行わ
れ、全体として連続的に行われる。
The storage devices 2t+ and 2c are also the same as the storage device 2a described above.
Similar operations are performed at regular intervals. Therefore, for example, during period T1, a write operation is performed in the storage device 2.
The process is performed for the storage device 2C during the period T2, and is performed for the storage device 2b during the period T3, and such operations are repeated. Similarly, read operations are performed alternately in the storage devices 2a to 2C, and are performed continuously as a whole.

第3図は再生動作時における記憶装置2の動作を示す図
であり、第3図(1)〜同図(3)は記憶装置2a、2
b、2cの動作をそれぞれ示している。
FIG. 3 is a diagram showing the operation of the storage device 2 during playback operation, and FIG. 3(1) to FIG.
The operations of b and 2c are shown respectively.

=11− 3つの記憶装置2a、2b、2cは記録動作時と同様に
各期間においてそれぞれ異なる動作が行われ、書込み、
すなわち記録媒体から磁気ヘッド6、増幅回路8および
復調回路7を介して与えられる信号の入力動作と、読出
し、すなわち記憶されている信号のD/A変換器11へ
の出力動作とが記憶装置2において連続して行われるよ
うに制御される。
=11- Similar to the recording operation, the three storage devices 2a, 2b, and 2c perform different operations in each period, such as writing,
That is, the operation of inputting a signal from the recording medium via the magnetic head 6, the amplifier circuit 8, and the demodulation circuit 7 and the operation of reading, that is, outputting the stored signal to the D/A converter 11 are performed by the storage device 2. It is controlled so that it is performed continuously.

たとえば記憶装置2aにおいては、読出し動作終了後第
3図(4)に示される信号Bの立上りで次に信号が書込
まれるアドレスに対して記憶内容の消去、つまり初期化
動作が開始され、期間T11だけ初期化動作が行われる
。このとき期間T11の開始にマージン期間TM3だけ
遅れて始まる期間T14において書込み動作が行われる
For example, in the storage device 2a, after the read operation is completed, at the rising edge of the signal B shown in FIG. The initialization operation is performed for T11. At this time, a write operation is performed in a period T14 that starts after a margin period TM3 after the start of the period T11.

初期化動作は、書込み動作終了以前に完了し、書込み動
作終了後、マージン期間TM4の経過を待って期間T1
5において訂正動作、すなわち記憶されている信号に付
加されている訂正符号に従って信号の誤り訂正あるいは
補間が行われる。この後期間T13においてD/A変換
器11への出力すなわち読出し動作が行われ、このよう
な動作が繰返される。
The initialization operation is completed before the end of the write operation, and after the end of the write operation, waits for the elapse of the margin period TM4 and then starts the period T1.
In step 5, a correction operation is performed, that is, error correction or interpolation of the signal is performed according to the correction code added to the stored signal. After this, in period T13, output to the D/A converter 11, that is, a read operation is performed, and such an operation is repeated.

記憶装置2b、2cについても上述した記憶装置2aと
同様な動作が一定期間ずつずれて行われる。したがって
たとえば期間Tllにおいては読出し動作は記憶袋W2
cについて行われ、期間T12においては記憶装置2b
について行われ、期間T13においては記憶装置2aに
ついて行われ、このような動作が繰返される。書込み動
作についても同様に記憶装置2a〜2Cにおいて交代で
行われ、全体として連続的に行われる。
For the storage devices 2b and 2c, the same operation as that for the storage device 2a described above is performed with a certain period of time being shifted. Therefore, for example, in period Tll, the read operation is performed by memory bag W2.
c, and in period T12, storage device 2b
This is performed for the storage device 2a during period T13, and such operations are repeated. Similarly, write operations are performed alternately in the storage devices 2a to 2C, and are performed continuously as a whole.

このように記録/再生装置15において記憶装置2の入
出力は連続的に行われ、たとえば音響信号の場合にも途
切れることがなく記録/再生される。従来このような機
能を実現するためには1期間のインタリーブが完結する
までの信号を記憶するだけの記憶容量の4倍の記憶容量
をもつ記憶装置が必要であったが、本実施例においては
従来の3/4に記憶容量を削減し、なおかつこれを実現
するための追加回路はわずかである。
In this way, the input/output of the storage device 2 in the recording/reproducing device 15 is performed continuously, and even in the case of, for example, an audio signal, recording/reproducing is performed without interruption. Conventionally, in order to realize such a function, a storage device with a storage capacity four times the storage capacity for storing signals until one period of interleaving is completed was required, but in this embodiment, The storage capacity can be reduced to 3/4 of the conventional size, and only a small amount of additional circuitry is required to achieve this.

本実施例において、デジタルオーディオチーブにおいて
行われるような信号の時間的な圧縮をしていない場合を
示したが、信号の時間的な圧縮を行う場合にも本発明を
実施することができる。また記録/再生装置15の記録
動作時においては、読出し動作時の記憶内容の消去動作
が選択されたが、書込み動作時の記憶内容の消去動作が
選択されてもよい。さらに再生動作時においては、書込
み動作時の記憶内容の消去動作が選択されたが、読出し
動作時の記憶内容の消去動作が選択されてもよい。
Although this embodiment shows a case where the signal is not temporally compressed as is done in digital audio technology, the present invention can also be implemented when the signal is temporally compressed. Further, during the recording operation of the recording/reproducing device 15, the erase operation of the stored contents during the read operation was selected, but the erase operation of the stored contents during the write operation may also be selected. Further, in the reproduction operation, the erase operation of the stored contents during the write operation is selected, but the erase operation of the stored contents during the read operation may be selected.

効  果 以上説明したように本発明によれば、記憶装置への書込
み期間中に信号の書込みに先行して記憶内容が消去され
るかもしくは記憶装置からの読出し期間中に信号の読出
しに追従して記憶内容が消去される。このため記憶装置
の書込みあるいは読出しの動作が記憶内容の消去と同一
期間に行うことができる。したがって動作工程が短縮さ
れ、記録/再生装置などにおいては記憶装置の容量を大
幅に削減することが可能となり、装置の性能を損なうこ
となくコストダウンが実現される。
Effects As explained above, according to the present invention, the memory contents are erased prior to the writing of the signal during the period of writing to the storage device, or are erased following the reading of the signal during the period of reading from the storage device. The memory contents will be erased. Therefore, the writing or reading operation of the storage device can be performed during the same period as the erasing of the storage contents. Therefore, the operating process is shortened, and the capacity of a storage device in a recording/reproducing device or the like can be significantly reduced, and costs can be reduced without impairing the performance of the device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例である記録/再生装置15の
構成を示すブロック図、第2図は記録/再生装置15の
記録動作時の記憶装置2の動作を示す図、第3図は記録
/再生装置15の再生動作時の記憶装置2の動作を示す
図、第4図は従来技術の記録/再生装置の記録動作時の
記憶装置MR1〜MR4の動作を示す図、第5図は従来
技術の記録/再生装置の再生動作時の記憶装置MRI〜
MR4の動作を示す図である。 2・・−記憶装置、3・・・訂正符号付加回路、6・・
・磁気ヘッド、7・・・記録媒体、10・・・誤り訂正
回路、12・・・消去回路、15・・・記録/再生装置
、16・・・切換スイッチ 代理人  弁理士 画数 圭一部 第1図 第20
FIG. 1 is a block diagram showing the configuration of a recording/playback device 15 which is an embodiment of the present invention, FIG. 2 is a diagram showing the operation of the storage device 2 during the recording operation of the recording/playback device 15, and FIG. 4 is a diagram showing the operation of the storage device 2 during the reproducing operation of the recording/reproducing apparatus 15, FIG. is the storage device MRI during the playback operation of the prior art recording/playback device~
It is a figure which shows the operation|movement of MR4. 2...-Storage device, 3... Correction code addition circuit, 6...
・Magnetic head, 7... Recording medium, 10... Error correction circuit, 12... Erasing circuit, 15... Recording/reproducing device, 16... Changeover switch agent Patent attorney Number of strokes Keibu 1st Figure 20

Claims (1)

【特許請求の範囲】 デジタル信号が書込まれ、また読出される記憶装置と、 該記憶装置の記憶内容が消去されるアドレスを出力する
アドレス指定手段とを含み、 前記記憶装置への書込み動作時には書込まれるアドレス
をアドレス指定手段によつて指定して書込み動作に先立
つて記憶内容を順次的に消去し、前記記憶装置からの読
出し動作時には記憶内容が読出されたアドレスをアドレ
ス指定手段によって指定して記憶内容を順次的に消去し
、 これら書込み動作時または読出し動作時において、記憶
内容の消去動作の少なくともいずれか一方を選択するよ
うにしたことを特徴とする記憶装置の制御方式。
[Scope of Claims] A storage device into which digital signals are written and read, and an address specifying means for outputting an address at which the storage contents of the storage device are erased, and when a write operation is performed on the storage device. Prior to a write operation, the memory contents are sequentially erased by specifying the address to be written by the address specifying means, and when reading from the storage device, the address from which the memory contents were read is specified by the address specifying means. 1. A control method for a storage device, characterized in that the storage contents are sequentially erased using the following steps, and at least one of the storage contents erasing operation is selected during a write operation or a read operation.
JP26008687A 1987-10-14 1987-10-14 Memory control system Pending JPH01100644A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26008687A JPH01100644A (en) 1987-10-14 1987-10-14 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26008687A JPH01100644A (en) 1987-10-14 1987-10-14 Memory control system

Publications (1)

Publication Number Publication Date
JPH01100644A true JPH01100644A (en) 1989-04-18

Family

ID=17343106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26008687A Pending JPH01100644A (en) 1987-10-14 1987-10-14 Memory control system

Country Status (1)

Country Link
JP (1) JPH01100644A (en)

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