JPH0785589A - Acoustic signal processor - Google Patents

Abstract

PURPOSE:To provide the acoustic signal processor which does not change reproducing time even at the time of changing over a speed in a reverse reproduction mode. CONSTITUTION:The acoustic signal reverse reproduced by setting the relative speed of a recorded recording medium and a reproducing element at alpha times the relative speed at the time of recording is converted by an AD converter 4 to digital data, which is stored into a memory 6. Reading out address values are changed by repeating reciprocation between the prescribed top address and final address of the memory 6 and are read out at the reading out period of alpha times the sampling period. The reading out addresses are successively written from the turned back address where the reading out address is turned back when the reading out addresses attain about the address value advanced by (alpha-1)/alpha of the entire address after the reading out address in turned back at the prescribed top address or final address of the memory in the acoustic signal processing from the recording medium at alpha times the recording speed. The reading out addresses are successively written from the address where the top address is turned back right after the reading out addresses turn back at the prescribed top address or the final address of the memory in signal processing from the recording medium at alpha times the recording speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides good sound even when an acoustic signal recorded on a recording medium is reproduced in a state different from the recording order on the recording medium at the time of recording or the recording speed at the time of recording. The present invention relates to an acoustic signal processing device capable of obtaining a signal.

[0002]

2. Description of the Related Art In a VTR, when reproducing a video signal,
Playback images in various playback modes by playing back recorded information from the magnetic tape at the same or different running speed as the recording operation in the same or different direction as the running direction of the magnetic tape during recording operation. That is, a normal reproduction image, a still image, a quick motion image, a slow motion reproduction image, a reverse reproduction image, or the like may be obtained. By the way, in the VTR, not only the recording / reproducing operation of the video signal but also the recording / reproducing operation of the audio signal accompanying the above-mentioned video signal recorded on the magnetic tape is performed, but the above-mentioned recording / reproducing operation on the magnetic tape is performed. When the running direction and running speed of the magnetic tape during the reproducing operation are different from the running direction and running speed of the magnetic tape during the recording operation, the audio signal accompanying the video signal has a pitch different from that of the original audio signal. It becomes a reproduction state in a state where they are different or the arrangement of information on the time axis is reversed.

Therefore, for example, when high-speed reproduction of recorded information of running of a magnetic tape is performed for high-speed confirmation of image contents, the frequency of the audio signal accompanying the reproduced video signal is natural. However, since the pitch is converted to the higher side, when listening to the reproduced sound,
Usually, it is not possible to grasp the information content, let alone the frequency of the audio signal accompanying the reproduced video signal is naturally converted to the higher side when the reverse high speed reproduction is performed. In addition to being in a state where the information array on the time axis is reversed,
The information content cannot be grasped.

Now, with respect to the audio signal reproduced when the running of the magnetic tape on which the information signal such as the audio signal accompanying the video signal is recorded is reproduced at high speed, various information contents can be clearly known. Since it is possible to expand various applications, a video / audio reproducing device equipped with a signal processing means for performing pitch conversion for returning an acoustic signal reproduced at high speed to an original acoustic signal, that is, a time obtained at high speed reproduction. The audio signal in the axially compressed state is used as a signal (one block signal) having a predetermined acoustic information amount, the block signal is sampled at a short sampling period, and the digital signal obtained by quantizing the sampled signal is written into the written state. A long signal stored in a controlled memory and capable of restoring the reading of the digital signal corresponding to the block signal stored in said memory to the original acoustic signal. It performed at the timing of the period of the read clock signal, video and audio reproduction apparatus has been proposed which is configured to be able to read a digital signal which is time-base-decompressed to allow restoration to the original audio signal.

FIG. 10 shows that the above-mentioned known video / audio reproducing apparatus has two memories, one of which is performing a write operation and the other of which is performing a read operation. Writing the time-axis compressed reproduction acoustic signal and the state of the reproduction acoustic signal read in the time-axis-extended state in the case where the two memories are sequentially and alternately written and read. FIG. 10 (a) is a diagram for explaining, when the recording / reproducing apparatus is performing a reproducing operation at N times speed,
An acoustic signal reproduced from a recording medium, that is, a time axis in which the time axis is compressed to 1 / N compared with the original acoustic signal to be recorded, and the time axis of the time length of T / N in the compressed acoustic signal. FIG. 10B shows that only the compressed acoustic signal is intermittently written in the memory every time T, and FIG. 10B shows the time having the time length of T / N stored in the memory. It shows a state in which the axially compressed acoustic signal is read from the memory as an acoustic signal having a time length of T, which is N-time expanded in the time axis.

As is apparent from FIGS. 10 (a) and 10 (b), in the above-mentioned known video / audio reproducing apparatus, the time axis reproduced from the recording medium of the recording / reproducing apparatus performing the reproducing operation at N times speed. Regarding the compressed acoustic signal, a time-axis compressed acoustic signal having a time length of T / N in the time-axis compressed acoustic signal divided into time periods T on the time axis is obtained as a reproduced acoustic signal having the same pitch as the original acoustic signal. Therefore, although the reproduced acoustic signal having the same pitch as that of the original acoustic signal is a discontinuous signal portion of the original acoustic signal, the time length T described above is properly selected and written in the memory T /
If there is valid acoustic information during the time period of N,
It is considered to be useful for confirming the information content of the sound signal reproduced at N times speed. Further, as a device useful for confirming the information content of an acoustic signal when the recording / reproducing device is performing a reproducing operation at -N times speed (reverse rotation high speed reproducing), it is described in JP-A-63-317979. At the same time, the time-axis compressed acoustic signal reproduced from the recording medium of the recording / reproducing apparatus is sequentially written from one end address of the memory (refer to the downward-sloping dashed line in FIG. 9), and at the same time the other end of the memory is simultaneously written. An apparatus has been proposed which is configured to read sequentially from the address in the reverse direction (see a diagonal line with a solid line rising to the right in FIG. 9).

[0007]

However, in the device disclosed in the above-mentioned Japanese Patent Laid-Open No. 63-317979, a predetermined acoustic information amount obtained by the time-axis-compressed acoustic signal obtained by the reverse high speed reproduction is obtained. A series of switching points of reproduced audio information (see, for example, point a in FIG. 9) necessarily occur in the signal (one block signal), and are read out on both sides of the switching point of the reproduced audio information. Since the reproduced sound information contents correspond to the signals of different blocks, the reproduced sound information contents are discontinuous at the above-mentioned switching points of the reproduced sound information. As a means for solving the above-mentioned problems without increasing the capacity of the memory used, conventionally, as shown in FIG. 8, writing (reading with a broken line in FIG. 8) and reading (reading with a solid line in FIG. 8) to the memory are performed. ) Is not performed at the same time, the read operation is performed after the write operation of one block signal is completed, the solution means disclosed in Japanese Utility Model Laid-Open No. 59-45607, a memory as shown in FIG. The read address is read by changing the read address in one direction, and the write address is a cycle of N / (N + 1), which is one cycle of the read address.
In the 1 / (N + 1) period, the write operation is performed by changing the address value at the speed of N times in the direction opposite to the change direction of the read address.
The solution means disclosed in Japanese Patent Publication No. 65 has been proposed.

However, in the solution means shown in the above,
While the reproduction audio signal is being written to the memory, there is a problem in that the audio signal output is interrupted from the start of writing to the end because the reading from the memory is not performed. In the means, the cycle of the write address is N / (N + 1), which is one cycle of the read address.
Therefore, the value of the continuous reproduction time (T) of a series of blocks of the output acoustic signal varies depending on the reproduction speed. For example, at the -1 × speed, (1/2) T seconds,
-There is a problem in that it becomes difficult to grasp the contents because it changes to (2/3) T seconds as shown in FIG. 7 at -2x speed, and there is no problem as described above. The emergence of a solution was desired.

[0009]

According to the present invention, recording is performed in the reverse order of the order of recording on a recording medium at the time of recording, and in a state of α (where α ≧ 1) times the recording speed at the time of recording. An acoustic signal reproduced from a medium, an analog-to-digital conversion means for sampling and quantizing at a predetermined sampling period, a memory for storing digital data of the acoustic signal output from the analog-to-digital conversion means, and Means for reading the digital data of the acoustic signal from the memory at a read cycle longer than the sampling cycle described above, and an analog signal form by digital-analog conversion of the digital data of the acoustic signal read from the memory. Means for outputting as an audio signal, and reading the digital data of the audio signal from the memory is performed by using a predetermined start address of the memory. Read-out address control means for performing reciprocation with respect to the final address in accordance with a change mode of the read-out address value, and reproduction from the recording medium in a state where α is α> 1 times the recording speed. In the signal processing for the generated acoustic signal, after the read address is folded back at the predetermined start address or end address of the memory, (α
-1) / α, which is a state of α times the recording speed in which α = 1 so that the above-mentioned read addresses are sequentially written from the folded address when reaching the vicinity of the address value. In the signal processing for the acoustic signal reproduced from the recording medium, immediately after the read address is folded back at the predetermined start address or the final address of the memory, the read address is sequentially written from the folded address. And a state in which the recording speed at the time of recording is α (where α> 1) times, in the same order as the recording order on the recording medium at the time of recording. An analog-to-digital conversion means for sampling and quantizing the acoustic signal reproduced from the recording medium at a predetermined sampling period,
A memory for storing the digital data of the acoustic signal output from the analog-to-digital conversion means, and the digital data of the acoustic signal is read from the memory with a read cycle longer than the sampling cycle. Means for converting the digital data of the acoustic signal read from the memory into a digital-analog signal and outputting it as an acoustic signal in the form of an analog signal; and the reading of the digital data of the acoustic signal from the memory, is performed by the predetermined memory. The read address control means for performing the read address value change such that the round trip is repeated between the start address and the end address, and the read address is a predetermined start address or end address of the memory. When it reaches near the return address value, the above-mentioned reading To provide an acoustic signal processing apparatus comprising a means to allow the sequentially write from the address dress folded performed.

[0010]

With the relative speed between the recorded recording medium and the reproducing element being α times the relative speed between the recording medium and the recording element at the time of recording, the acoustic signal reproduced in reverse is predetermined by the analog-digital converter. Sampling and quantizing at the sampling period is performed and stored as digital data of the acoustic signal in the memory. The read address is controlled so that the read address value is changed by repeating the round trip between the predetermined start address and the end address of the memory, and the digital of the acoustic signal stored in the memory is performed. The data is read at a read cycle that is α times the sampling cycle described above. When the signal processing is performed on the acoustic signal reversely reproduced from the recording medium at α times the recording speed (where α> 1), the read address is folded back at a predetermined start address or end address of the memory, and then all addresses are read. When it reaches the vicinity of the address value advanced by (α-1) / α, the reading address is written sequentially from the folded address, and the recording speed is α times (α = 1). ), In the signal processing for the acoustic signal reversely reproduced from the recording medium, immediately after the read address is turned back at the predetermined start address or the final address of the memory, the address returned by the read address is returned. Writing is sequentially performed from. The digital data of the acoustic signal read from the memory is digital-analog converted and output as an acoustic signal in an analog signal form.

The relative speed between the recorded recording medium and the reproducing element is α times the relative speed between the recording medium and the recording element at the time of recording (where α> 1), and an acoustic signal reproduced at high speed in the forward direction is The analog-to-digital converter samples and quantizes the audio signal in a predetermined sampling period, and stores it in a memory as digital data of the acoustic signal. The read address is controlled so that the read address value is changed by repeating the round trip between the predetermined start address and the end address of the memory, and the digital of the acoustic signal stored in the memory is performed. The data is read at a read cycle that is α times the sampling cycle described above. When the read address reaches the vicinity of the address value at which the read address is returned at a predetermined start address or end address of the memory, writing is sequentially performed from the address returned by the read address. The digital data of the acoustic signal read from the memory is digital-analog converted and output as an acoustic signal in an analog signal form.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The concrete contents of the audio signal processing apparatus of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram of an audio signal processing device of the present invention, and FIG.
Is a diagram showing the relationship between the write address clock and the read address clock, FIGS. 3 to 5 are diagrams for explaining the operation of the acoustic signal processing apparatus of the present invention, and FIGS. 6 to 10 are operation explanations of the conventional acoustic signal processing apparatus. FIG. In FIG. 1, which illustrates the audio signal processing apparatus of the present invention, reference numeral 1 is an input terminal for an audio signal reproduced from a magnetic tape of a recording / reproducing apparatus. When a recording / reproducing device (for example, a VTR) (not shown) is performing a double speed reproduction operation in the forward direction or a reverse speed double speed reproduction operation on the input terminal 1, the audio signal is time-axis compressed. Since it is reproduced in the state, the input terminal 1 is supplied with the time-axis compressed acoustic signal whose pitch is converted to the higher frequency.

An acoustic signal in the state of, for example, a time-axis compressed acoustic signal supplied to the input terminal 1 is given to an analog-digital converter (AD converter) 4 and is not shown in the AD converter 4. Based on the AD conversion pulse supplied from the control unit, the acoustic signal is converted into a digital signal having a predetermined number of bits for each predetermined sampling period. The digital signal of the acoustic signal output from the AD converter 4 is supplied to the memory 6. In the memory 6, the write address signal ADW generated by the write address counter 16 is supplied to the address switch 7. Is supplied to the memory 6 via the write address signal ADW, the digital signal of the acoustic signal output from the AD converter 4 is written in the storage area of the address specified by the write address signal ADW. The digital signal of the acoustic signal stored in the memory 6 is
A digital-to-analog converter (DA converter) is read in a reading manner so that a reproduced sound signal of a predetermined pitch can be obtained.
5, the output acoustic signal DA-converted into an analog signal by the digital-analog converter 5 is sent to the terminal 2.

In FIG. 1, reference numeral 8 is a reference clock oscillator, and a clock signal CLK generated by this reference clock oscillator 8 is supplied to a timing signal generator 9. The timing signal generator 9 uses the clock signal CLK supplied from the reference clock oscillator 8 and the reproduction speed mode signal supplied from the recording / reproducing apparatus (not shown) to determine the reproduction mode in the recording / reproducing apparatus. Various corresponding signals, that is, a write address clock signal WACK and a read address clock signal RAC
K and address mode signal R / W are generated. Write address clock signal WA illustrated in FIG.
CK and the read address clock signal RACK illustrated in FIG. 2B are such that the cycle of the write address clock signal WACK is the read address clock signal RACK.
The case of 1/5 of the cycle is shown. The write address clock signal WACK and the read address clock signal RACK described above are generated so as to be displaced on the time axis.

A reproduction direction mode signal F / R supplied from the recording / reproduction device to the terminal 3, the reproduction speed mode signal described above, and a write address up / down signal UDW generated from a D flip-flop FF3 as described later. The write start address generator 12, which is supplied with, etc., generates a read address value ADWS to start writing. Read address value ADW at which the writing should start
S is supplied to the comparator 13. Read address clock signal RAC generated by the timing signal generator 9 described above.
The read address counter 10, to which K is supplied as the signal to be counted, performs an addition operation or a subtraction operation according to the read up / down signal UDR, outputs the read address signal ADR, and outputs it to the comparator 13 described above. And the address switch 7 as well. Further, the read address counter 10 has a read address signal AD when it is performing a subtraction operation.
When R becomes the start address, the read address minimum signal RN is output, and the read address counter 1
When 0 is performing the addition operation, the read address maximum signal RX is output when the read address signal ADR reaches the final address.

The read address minimum signal RN output from the read address counter 10 is supplied to the set terminal of the set / reset flip-flop FF1, and the read address maximum signal RX output from the read address counter 10 is , The read address signal ADR is supplied from the Q output terminal of the set / reset flip-flop FF1 to the reset terminal of the set / reset flip-flop FF1.
When the read address counter 10 is performing the adding operation, the read address signal ADR changes to the low level state when the read address signal ADR reaches the final address. The up / down signal UDR is output. The read up / down signal UDR output from the Q output terminal of the set / reset flip-flop FF1 is supplied to the read address counter 10 and also to the D terminal of the D-type flip-flop FF3.

The write address counter 16 to which the write address clock signal WACK generated by the timing signal generator 9 is supplied as the counted signal is output from the Q output terminal of the D flip-flop FF3. According to the write-up / down signal UDW, an addition operation or a subtraction operation is performed to write address signal A
DW is generated and supplied to the address switch 7.
Further, the write address counter 16 outputs the write address minimum signal WN when the write address signal ADW reaches the head address when the write address counter 16 is performing the subtraction operation, and the write address counter 16 described above is output.
However, when the addition operation is performed, the write address maximum signal WX is output when the write address signal ADW reaches the final address.

As described above, the write address counter 16
The OR circuit 17 to which the minimum write address signal WN and the maximum write address signal WX output from the OR circuit 17 are supplied.
Outputs a logical sum output signal WNX of the above two signals. The signal WNX is supplied to the reset terminal of the set / reset flip-flop FF2 and also to the clock terminal of the D-type flip-flop FF3. The output signal WS of the comparator 13 is supplied to the set terminal of the set / reset flip-flop FF2. Therefore, the signal WNX output from the OR circuit 17 is input to the reset terminal from the time when the signal WS output from the comparator 13 is input to the set terminal from the Q output terminal of the set reset flip-flop FF2. The write enable signal WE which is in a high level state by the time point is given to the write address counter 16 and
Performs the counting operation only while the write enable signal WE is at the high level.

The set / reset flip-flop F
The write address up / down signal UDW generated from the D-type flip-flop FF3, to which the read up / down signal UDR output from the Q output terminal of F1 is applied to the data terminal, is the output signal WNX from the OR circuit 17 described above. When applied to the clock terminal, it is supplied to the write address counter 16 and the write start address generator 12 from the Q output terminal of the D-type flip-flop FF3. The read address signal ADR output from the read address counter 10, the write address signal ADW output from the write address counter 16, and the address mode signal R / W output from the timing signal generator 9 are supplied. In the address switch (address selection circuit) 7, the address mode signal R /
In accordance with W, the read address signal ADR and the write address signal ADW output from the write address counter 16 are switched to switch the address signal AD to the memory 6.
Supply S.

The above-mentioned write operation and read operation for the memory 6 are performed in the storage area designated by the address signal ADS including the write address signal ADW and the read address signal ADR supplied to the memory 6 through the address switch 7. As shown in FIG. 3 to FIG.
FIG. 4 illustrates the relationship between the writing operation and the reading operation on the time axis with respect to the memory 6 in the audio signal processing device of the present invention. FIG. 3 shows the memory 6 of the acoustic signal processing device of the present invention regarding the acoustic signal reproduced from the recording medium when the recording / reproducing device is performing the reverse reproduction operation at 5 × speed.
4 is a diagram showing the relationship between the writing operation and the reading operation in FIG. 4, and FIG. 4 is a diagram showing the audio signal reproduced from the recording medium when the recording / reproducing apparatus is performing the reverse reproduction operation at 1 × speed. FIG. 6 is a diagram showing a relationship between a writing operation and a reading operation in the memory 6 of the audio signal processing device of the invention, and FIG.
FIG. 6 is a diagram showing a relationship between a writing operation and a reading operation in a memory 6 of the acoustic signal processing device of the present invention regarding an acoustic signal reproduced from a recording medium when a reproducing operation is performed at a double speed. In each of FIGS. 3 to 5,
Writing to the memory 6 is indicated by a dashed diagonal line.
Readouts from are shown by solid diagonal lines.

As can be seen from FIGS. 3 to 5, in the acoustic signal processing apparatus of the present invention, the read from the memory 6 is such that the read address value makes a round trip between the predetermined start address and the end address of the memory. It is performed under the control of the read address so that the state is repeatedly changed. That is, the continuous hatched lines shown in FIGS. 3 to 5 indicate a state in which the read address value is changed by repeating the round trip between the predetermined start address and the end address of the memory. On the other hand, in the writing operation to the memory 6, when the reproduced acoustic signal from the recording / reproducing apparatus, for example, the relative speed between the recorded recording medium and the reproducing element is α times the relative speed between the recording medium and the recording element at the time of recording. (However α
In the case of the audio signal reproduced in reverse as> 1), the read address is folded back at a predetermined start address or end address of the memory, and then (α-1) of all addresses.
When it reaches the vicinity of the address value advanced by / α, writing is sequentially performed from the address where the read address is folded back. An example of this case is shown in FIG.

In addition, the reproduced sound signal from the recording / reproducing apparatus, for example, determines the relative speed between the recorded recording medium and the reproducing element by α times the relative speed between the recording medium and the recording element during recording (where α = In the case of the audio signal reproduced in reverse as 1), immediately after the read address is turned back at the predetermined start address or the final address of the memory, writing is sequentially performed from the address returned by the read address. To be done. An example of this case is shown in FIG. In the forward direction, the reproduction acoustic signal from the recording / reproducing apparatus is, for example, the relative velocity between the recorded recording medium and the reproducing element is α times (where α> 1) the relative velocity between the recording medium and the recording element at the time of recording. In the case of an acoustic signal reproduced at high speed, when the read address reaches the vicinity of the address value at which the read address is folded at a predetermined start address or end address of the memory, writing is sequentially performed from the address returned by the read address. To be done. An example of this case is shown in FIG.

[0023]

As is apparent from the above detailed description, the acoustic signal processing apparatus of the present invention is such that the relative speed between the recording medium already recorded in the recording / reproducing apparatus and the reproducing element is the recording medium at the time of recording. The acoustic signal reproduced in reverse as α times the relative speed between the recording element and the recording element is sampled and quantized by an analog-digital converter at a predetermined sampling period and stored as digital data of the acoustic signal in a memory. Then, the read address is controlled so that the read address value is changed by repeating the round trip between the predetermined start address and the end address of the memory, and the acoustic signal stored in the above memory is controlled. Of the digital data is read at a read cycle that is α times larger than the sampling cycle, and the acoustic signal is recorded at a recording speed α times (where α> 1) the recording speed. In the signal processing of the reproduced acoustic signal, the read address is returned from the predetermined start address or the final address of the memory to the vicinity of the address value advanced by (α-1) / α of all the addresses. When it reaches, the reading address is sequentially written from the folded address, and at the time of signal processing for the acoustic signal reproduced from the recording medium at α times (α = 1) the recording speed. Is a sound read from the memory such that the read address is folded at the predetermined start address or the final address of the memory, and immediately after the read address is folded, writing is sequentially performed. Converts the digital data of the signal to digital-to-analog and outputs it as an acoustic signal in the form of an analog signal. Then, the relative speed between the recorded recording medium and the reproducing element is set to α times (where α> 1) the relative speed between the recording medium and the recording element at the time of recording (where α> 1), and the acoustic signal reproduced at high speed in the forward direction is analog-digital The converter quantizes and quantizes the audio signal in a predetermined sampling period to store it in a memory as digital data of the acoustic signal, and the read address value reciprocates between a predetermined start address and end address of the memory. By controlling the read address so as to be in a changing state, the digital data of the acoustic signal stored in the memory is read at a read cycle that is α times the sampling cycle, When the read address reaches the vicinity of the address value to be folded at a predetermined start address or end address of the memory, the read address is folded. Since the digital data of the acoustic signal read from the memory is converted into a digital-analog signal to output an acoustic signal in the form of an analog signal, the present invention is adapted to perform sequential writing from different addresses. Output sound signal is not interrupted,
Further, even if the reproduction speed is changed and changed, the continuous reproduction time of a series of one-block signals is always T seconds, so that it is easy to hear, and also in the acoustic signal processing at the time of high speed reproduction in the forward direction, at the time of reverse reproduction Since the read address control means similar to the case of the signal processing for the acoustic signal can be used, the circuit configuration can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram of an acoustic signal processing device of the present invention.

FIG. 2 is a diagram showing a relationship between a write address clock and a read address clock.

FIG. 3 is a diagram for explaining the operation of the acoustic signal processing device of the present invention.

FIG. 4 is a diagram for explaining the operation of the acoustic signal processing device of the present invention.

FIG. 5 is a diagram for explaining the operation of the acoustic signal processing device of the present invention.

FIG. 6 is a diagram for explaining the operation of a conventional acoustic signal processing device.

FIG. 7 is a diagram for explaining the operation of the conventional acoustic signal processing device.

FIG. 8 is a diagram for explaining the operation of a conventional acoustic signal processing device.

FIG. 9 is a diagram for explaining the operation of a conventional acoustic signal processing device.

FIG. 10 is a diagram for explaining the operation of the conventional acoustic signal processing device.

[Explanation of symbols]

4 ... AD converter, 5 ... DA converter, 6 ... Memory, 7 ... Address switch (address selection circuit), 8 ... Oscillator, 9
... Timing signal generator, 10 ... Read address counter, 11,14 ... Set reset flip-flop, 1
2 ... Write start address generator, 13 ... Comparator, 1
5 ... D flip-flop, 16 ... Write address counter, 17 ... OR circuit,

Claims (2)

[Claims] 1. An acoustic signal reproduced from a recording medium in the order reverse to the recording order on the recording medium at the time of recording and at a state of α (where α ≧ 1) times the recording speed at the time of recording. An analog-digital conversion means for sampling and quantizing at a predetermined sampling cycle, a memory for storing digital data of an acoustic signal output from the analog-digital conversion means, and the sampling cycle described above from the memory Means for reading the digital data of the acoustic signal described above in a read cycle that is longer than that of, and means for digital-to-analog converting the digital data of the acoustic signal read from the memory and outputting it as an acoustic signal in the form of an analog signal. , The reading of the digital data of the acoustic signal from the memory is reciprocated between the predetermined start address and the end address of the memory. In the signal processing for the audio signal reproduced from the recording medium in the state where α is α times the recording speed in which α has a relation of α> 1, the read address control means is configured to be repeatedly performed according to the changing manner of the read address value. Is the read address when the read address reaches around an address value advanced by (α-1) / α of all addresses after being folded at a predetermined start address or end address of the memory. In the signal processing of the acoustic signal reproduced from the recording medium in the state of α times the recording speed in the relation of α = 1 so that the addresses are sequentially written from the folded address, the read address is Immediately after returning to the specified start address or end address of the memory,
An audio signal processing apparatus comprising: means for sequentially writing data from the address where the read address is folded back. 2. The recording speed α at the time of recording (however, in the same order as the order of recording on a recording medium at the time of recording)
an analog-to-digital conversion means for sampling and quantizing an acoustic signal reproduced from the recording medium in a state of α> 1) times in a predetermined sampling period; and an acoustic signal output from the analog-to-digital conversion means. A memory for storing digital data, a unit for reading the digital data of the acoustic signal with a read cycle longer than the sampling cycle with respect to the memory, and the digital data of the acoustic signal read from the memory. Means for digital-to-analog converting and outputting as an acoustic signal in the form of an analog signal, and reading of digital data of the acoustic signal from the memory described above repeats a round trip between a predetermined start address and end address of the memory. And a read address control means for performing the read address value change mode. When the address reaches the vicinity of the address value at which the address is folded back at the predetermined start address or the final address of the memory, the read address is sequentially written from the folded address. Sound signal processing device.