RU2018180C1 - Verbal information digital recorder-reproducer - Google Patents

Abstract

FIELD: data storage. SUBSTANCE: device having audio converter 1, record amplifier 2, comparator 3, reversing counter 4, digital-to-analog converter 5, oscillator 6, storage control circuit 10, first digital storage unit 11, integrator 12, low-frequency filter 13, reproduction amplifier 14 is provided in addition with mode selector switch 15, second address counter 16, second digital storage unit 17, and relevant ties. EFFECT: simplified design, improved characteristics. 3 dwg

Description

 The invention relates to the accumulation of information.

 A device is known consisting of an external signal generator and a talking doll containing a central processing unit and a speech synthesizer, which includes a digital-to-analog signal converter, to which a portable speaker is connected for reproducing messages in speech form, a memory device for storing speech messages in digital form, a radio receiver associated with the processor unit, and receiving command signals to sample from the memory the desired voice message from the external signal generator [1].

 The disadvantage is the need to control the choice of voice messages, which reduces amusement, and the lack of the ability to quickly write to the memory of voice messages.

 A device for digital recording - playback of voice information, selected for the prototype, containing a memory unit, an element And, two ADCs, a control pulse shaper, an address counter, a decoder, an interval time counter, a clock bus, an address multiplexer, three OR elements, a recording trigger , commutator [2].

 The disadvantage is that the operation of the device requires a large amount of memory, which leads to a limitation of the area of use by the mass of overall dimensions.

 The purpose of the invention is to simplify the device and increase its amusement.

 Figure 1 presents the functional diagram of the proposed device; figure 2 is a threshold circuit; figure 3 is a memory management diagram.

 The device comprises an audio converter 1, recording amplifier 2, a comparator 3, a reverse counter 4, a digital-to-analog converter 5, a generator 6, a threshold circuit 7, a trigger 8, a first address counter 9, a memory management circuit 10, a first discrete memory block 11, an integrator 12, a low-pass filter 13, a playback amplifier 14, a mode switch 15, a second address counter 16 and a second discrete memory unit 17.

 Scheme 7 is made on a multi-input element And 18.

 The circuit 10 contains the elements And 19 and 20 and the inverter 21.

 The device operates as follows.

 In the first mode, the voice information is periodically recorded and reproduced from the memory unit 11, in the second mode, the device only reproduces the voice information from the memory unit 17. In the process of working in the first mode, the device is sequentially in the following states: standby, recording and playback.

 The acoustic speech signal is converted by the transducer 1 to electric, amplified by the recording amplifier 2 and fed to the direct input of the comparator 3, if the voltage of this signal is higher than the voltage at the inverse input of the comparator, then a high level signal and pulses from the generator 6 to the input of the reversible counter 4 is summed in it, the voltage at the output of the digital-to-analog converter 5 increases, otherwise a low signal is set at the output of the comparator level, the counter 4 operates on the subtraction, and the voltage at the output of the Converter 5 decreases. Thus, the device seeks to compensate for the input signal by tracking its changes. As long as the level of the input signal from the sound transducer 1 does not exceed the threshold value, the device is waiting.

 When the level of the input signal increases, the threshold circuit 7 generates a pulse that changes the state of the trigger 8, the output of which gives permission to the first counter 9 of the address, the device switches to the recording state. The playback amplifier 14 during recording is blocked by the signal from the control circuit 10. Under the influence of pulses from the generator, the first address counter sequentially searches the addresses of the memory block 11, the circuit 10 generates a write signal, and the characteristics of the pulses from the output of the comparator are written to the memory. The duration of these pulses, the amount of pauses between them and their repetition rate contains information about the amplitude and frequency of the input speech signal. Recording continues until the address counter 9 completes the search of all the addresses of the address space of the memory unit 11, after which the device enters the playback state.

 The circuit 10 generates read signals, the counter 9 performs a sequential enumeration of addresses, discrete signals from the output of the first memory block with the help of an integrator 12 and a low-pass filter 13 are restored to the original analog signal, which is transmitted through the playback amplifier 14 to the sound transducer 1, which converts it into acoustic speech signal.

 After enumerating all the addresses, the pulse from the high order of the first address counter switches trigger 8, which blocks the first address counter and puts the device into a standby state. The device waits for a speech signal, upon receipt of which the entire cycle of work is repeated.

 The operation of the device is transferred to the second mode by the switch 15, in this case, the signals from the control circuit 10 are supplied to the memory unit 17, and not to the memory unit 11.

 At the beginning, the device is in a standby state. The permission from the inverse output of the trigger 8 goes to the second address counter 15, which enumerates the high addresses of the memory unit 17 under the influence of pulses from the output of the generator 5, the operation of the rest of the device in the standby state is described above. As in the first mode, the device waits for an output signal, the level of which is higher than the threshold value, when such a signal arrives, the counter 16 is blocked, and the counter 9 receives permission. The device goes into a pause state.

 In the paused state, the first address counter enumerates the addresses, but unlike the first mode, information is not recorded, since the memory unit 17 does not have an information input and does not perceive recording signals from the control circuit 10. The pause lasts until the counter 9 addresses does not complete enumeration of all addresses, after which the device enters the playback state.

 In the memory block 17, the speech information is recorded in phrases, the choice of a particular phrase is determined by the upper digits of the address, i.e. counter status 16. Since the input signal is not synchronized with the operation of the second address counter, the phrase is selected randomly. During playback, the circuit 10 generates read signals, the counter 9 sequentially searches the addresses, the discrete signals from the output of the second memory block with the help of the integrator 12 and the low-pass filter 13 are restored to the original analog signal, which is transmitted through the playback amplifier 14 to the sound transducer 1, which converts him into an acoustic speech signal, the device reproduces one of the phrases.

 After enumerating all the addresses, the pulse from the high order of the first address counter switches trigger 8, which blocks the first address counter, resolves the count to the second address counter and puts the device in the standby state. The device waits for a speech signal, upon receipt of which the entire cycle of work is repeated.

 Scheme 7, for example, can be implemented on the element And 18, the inputs of which are connected to the outputs of the reversible counter in such a way that the number K, the appearance of the code of which at the outputs of the reversible counter causes the logical unit to be set at the output of the element And, more than a certain number M is selected, whose code corresponds to the threshold level of the input speech signal.

 The memory management circuit 10 can be implemented on two elements And 19 and 20 and the inverter 21. The first inputs of the elements And are connected to the output of the generator, and the second inputs to the output of the first counter of the address, and the input of the element And 20 is connected through the inverter 21, from the output which also removes the lock signal of the playback amplifier. The output of the first address counter for connecting the memory management circuit corresponds to bit A, which is selected so that the (A-1) bits completely overlap the address grid of the first block of discrete memory.

 The reduction of hardware costs in the device is achieved by the fact that the sound converter performs two functions of both a microphone and a speaker, while during recording, the playback amplifier 14 is blocked to reduce noise, in addition, the signal is converted from analog form to digital when recording and from digital to analog during playback, it is performed using a reverse counter 14 built on the comparator 3, a digital-to-analog converter 5 and an integrator 12, a delta modulator-demodulator, which provides a reduction memory when recording a voice message, since it is not the absolute value of the digital representation of the signal amplitude that is recorded, but the relative (increment), and for each sample only one bit is recorded that has a single logical value if the signal in this sample increases in relation to the previous sample, or having zero value if the signal decreases.

Claims (1)

 DEVICE FOR DIGITAL RECORDING-PLAYBACK OF SPEECH INFORMATION, containing sound transducer, recording amplifier, comparator, reversible counter, digital-to-analog converter, generator, threshold circuit, trigger, first address counter, memory control circuit, first block of discrete memory, integrator, low-pass filter a playback amplifier, the output of which is connected to the sound transducer, the signal input to the low-pass filter output, and the enable input to the second output of the memory control circuit, first the input of which is connected to the generator, and the second input is to the first output of the first address counter, the counting input of which is connected to the generator, and the enable input is to the direct output of the trigger, the zero setting input of which is connected to the output of the threshold circuit, the input of which, as well as the input digital-to-analog converter, connected to the output of the reversible counter, the counter input of which is connected to the generator, and the input of the direction of the count is connected, as well as the information input of the first block of discrete memory, to the output of the comparator, inverse input One of which is connected to the output of the digital-to-analog converter, and a direct input is connected to the output of the recording amplifier, the input of which is connected to the output of the sound converter, the trigger zero input being connected to the third output of the first address counter, and the second output connected to the address input of the first discrete memory block, characterized in that a mode switch, a second address counter and a second discrete memory block are inserted into it, wherein the input of the mode switch is connected to the first output of the memory control circuit, the first output - to the control input of the first block of discrete memory, and the second output to the control input of the second block of discrete memory, the input of the least significant bits of the address of which, like the address input of the first block of memory, is connected with the second output of the first counter of the address, and the input of the upper bits of the address the second discrete memory block is connected to the output of the second address counter, the counting input of which is connected to the generator, and the enable input to the inverse trigger output, the outputs of the first and second discrete memory blocks are connected to the integral input torus, whose output is connected to an input of a lowpass filter.

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