JPS58218677A - Electronic timepiece having voice storing function - Google Patents

Abstract

PURPOSE:To store voice by automatic starting without causing interruption of voice by dividing storage area and writing coded voice in the first and second areas, and after starting automatic starting, writing in the third area. CONSTITUTION:When recording, a controlling section 23 selects the first or second area of recording storage areas such as RAM 21 etc. which is selected alternately at every recording, and voice that passes through a coding circuit 22 is recorded in the area. When the voice level becomes above specified level, and an automatic starting signal AST is applied, the controlling section 23 selects the third storage area of RAM 21. At the same time, final address at the time of recording the first or second storage area is stored in a latch circuit 24. By storing voice before starting automatic starting in separate storage area, voice storing by automatic starting can be performed without causing interruption of voice and without using storage area unnecessarily.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an Ichiko clock with a voice aF memory function which has a function of encoding and recording and reproducing externally input voice, and particularly relates to its recording and memory function.

An object of the present invention is to provide a recording and storage mechanism for effectively using an auto-start mechanism that automatically starts recording at the same time as voice input without performing any operations other than voice input. It is to obtain.

In addition, the word "voice" in this specification is used in the sense of encompassing all sounds such as human voices, music, and simulated sounds.

In recent years, electronic watches have become more multi-functional, and some have, for example, alarm and timer functions. However, the timing and warning means for these functions are simply sounds specified by the manufacturer, and the user must use the same sounds whether they like it or not. There was the inconvenience of having to remember what the acoustics meant.

In order to eliminate this inconvenience, an electronic watch with a voice SC memory function is an electronic watch that has a voice memory function that allows the user to freely input necessary information from the outside by voice and output it as voice at an appropriate time. be.

Therefore, it is necessary to give this electronic clock some sort of activation signal to start recording, and it would be cumbersome if the user had to give this signal each time by operating a switch, etc. Silence is recorded until the speaker starts speaking, which wastes limited memory capacity. Therefore, it is a very effective means for this electronic timepiece to include an auto-start circuit that determines the presence or absence of input audio and automatically controls the start of recording. However, since the auto start circuit performs startup control after detecting that audio has been input, considering the processing time, the first part of the input audio is not recorded because it is small, and the first part of the audio is not recorded. Parts will be cut off.

The present invention sees the above problem and eliminates this disadvantage.

It provides a recording start mechanism, and a detailed explanation will be added below with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of an electronic circuit of an electronic timepiece with an audio 8e memory function according to the present invention.

In FIG. 1, 1 is an oscillation circuit that generates a reference clock signal, 2 is a frequency divider circuit that receives the reference clock signal and generates a necessary signal, and FB-Fn is a clock circuit, a display circuit, etc. These are various functional circuits. 3 is a speaker that also serves as a microphone, and the 10 parts of 5 are connected through the amplifier of 4.
(input/output) connected to the switching circuit. 6 is an encoding circuit, which encodes the audio signal (vI.ice), which cannot be given in analog quantity, into a digital signal; the signal encoded here is sequentially sent to the recording section 7 according to the present invention. Stored. The recording section is mainly composed of a semiconductor memory, such as a RAM (unterahiro access memory) shaft register, and its control circuit, and uses the signal obtained from the frequency dividing circuit 2 as a reference to read (
read), WR engineering LE import) are performed. Reference numeral 8 denotes an audio signal synthesis circuit, which synthesizes analog audio signals from digital signals read from the recording section 7. Reference numeral 9 denotes an auto-start circuit, which outputs a recording start signal AST, for example, when the amplitude of the audio input signal (woic θ) exceeds a preset amplitude level. Reference numeral 10 denotes a switch control circuit, which receives input from the switch control circuit and generates signals necessary to control each function.

FIG. 2 is a block diagram (a) of an example of the recording section 7 according to the present invention in FIG. 1, and a memory thereof. , an example (1)) of dividing the recording storage area when using RAM.

In FIG. 2(a), 21 is a recording storage area using RAM, and 22 is an encoding circuit that stores data obtained by R.
In a format that is easy to AMKWRITE, and from RAM: a
A data conversion circuit that converts zAD data into a format that is easy to transfer to the audio signal synthesis circuit, and TtEAD/WRI.
The TE switching circuit 25 is a control circuit according to the present invention that monitors and controls the entire main bell sound section, includes an area switching circuit, and in particular controls the address of the RAM, and when the recording start signal AST is input, 5- The current address is transferred to 24 address latches. The address latch 24 memorizes the address that was not transferred and sends it back to the control circuit 23 during audio playback. Figure (b) shows an example of division of RAM (recording storage area). Ao-A, ld, represents the address of RAM. The RAM is divided into three areas as shown in the figure, and in this example, the first area (1) has addresses 'a, 'a'' IIH to 5F.
128Warcl of H, the second area (II) is the address,
'C114RH~128wara of 7 PH, third area (II) is the remaining address u8'aH~311'F
It is H. The operation of the present invention will be explained below.

At the time of recording, first, the area switching circuit VCX selects either area I or area H. For example, if region l is selected, data obtained from the encoding circuit is
address like f1unu-+nu 1H-*-...
Once the 13F'H dimension is completed, \3FH-+'a'a\H→\
11H→... Returns to the first address of the area and continues writing. Continuing to write, P
When the writing continues up to the point, the start signal AST from the auto start circuit enters the control circuit 23, and the control circuit sets the address XXXH of the FA (hereinafter referred to as the recording start address) to the address. Write to latch 24, perform subsequent writing to area ■, 11.8'a
H to 3FFH'! After writing, exit the stupor and finish recording. When the recording is once completed and the recording state is resumed, area (2) is selected this time, and the same operation as the above-mentioned recording operation is performed for area (2). In this way, area I
Switching between area n and area n is performed cyclically.

Next, during playback, the area selected during recording is selected by the area switching circuit, and the recording start address XXXH stored in the address latch is set in the control circuit. Now, if region I is selected, the control circuit is
XXXH+R"EIR1→XXXH+"a12→...
...→113FH→"a'aR) (→・・・・・・→
XXXH-e"a8H-*u81H-p--・-"-+
5FFH (D'7) The data is read out in the order of address, subjected to data conversion by the data conversion circuit 22, transferred to the audio signal synthesis circuit 8 in FIG. 1, and output as audio.

When area (3) is selected, the address control performed by the control circuit is as follows, and this address order is followed (c) The reproduction operation of the previous P cannot be performed.

XXXH+'El 10H-+XXXH+'aR2H-+・
・−・−・−+R7F'I(→...4\H→・・・・・・
→XXXH→18\H→・・・・・・→3FFH or more recording/playback operations make it possible to record the audio before the recording starts.

As described above, according to the present invention, by simple memory address control, it is possible to eliminate sound interruptions caused by the auto start function, and it is possible to obtain a recording and storage mechanism in which the function can be effectively used.

Also, area 1 due to memory division. The sizes of II and Ill can be freely set according to the purpose and conditions by simply modifying the control circuit, and are not limited to the present embodiment.

[Brief explanation of the drawing]

Fig. 1: Configuration example of a weight circuit of an electronic watch with voice memo according to the present invention

Claims (1)

[Claims] 1. It has a recording device that encodes and records and stores audio input from the outside, and an output device that reads out the contents stored in the recording device, converts it into an audio signal, and outputs the audio,
Further, in an Ichiko clock with a voice memory function, the clock has an auto-start circuit comprising a startup control circuit that determines the presence or absence of an input voice, controls the startup of the recording device, and starts recording. The memory area is divided into three areas, and before activation by the auto-start circuit, the encoded audio is stored in the first area or the second area, and the auto-start circuit After startup, S stores encoded audio in the third area.
i) An Ichiko clock with a voice memory function, comprising a memory control circuit and an area switching circuit for selecting either a first area or a second area.