JPS63882A - Digital signal processor - Google Patents

Abstract

PURPOSE:To efficiently perform the transfer of a reception data, by reading out the reception data stored in a memory by a signal based on the count value of the number of the reception data, and controlling transmission. CONSTITUTION:A data clock DCLK from a subcode generator is set as a digit address by being counted by a 6-bit counter 25 in a reception control circuit 13, and the count value of a 7-bit counter 7 which counts a carrier signal from the counter 25 is set as the digit address, thereby, a reception bit data is written on a RAM. The count values of those counters 25 and 26 are monitored at a decision circuit 27, and a latch circuit 32 outputs a monitored at a decision circuit 27, and a latch circuit 32 outputs a latch signal based on the counting of the number of the reception data within a prescribed period, an a gate for significant seven bits, etc., corresponding to the 13-bit counter 33 of a masking circuit 34 in a transmission control circuit 17, is controlled, an one time transmission output by the readout of the RAM is controlled within a prescribed number of bits. In such way, it is possible to perform the transfer of the reception data efficiently in which a bit is varied in capacity, even in a transmission line having a fixed transmission speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital signal processing device that transfers variable received data to a digital transmission path having a fixed transmission rate.

[Prior Art and its Problems] When recording and reproducing audio signals, high-quality recording and reproducing can be achieved by converting the audio signals into PCM, so research has been active in recent years. As an example, research is underway on DAT (digital audio tape recorder), which records audio signals in PCM format on insect tape. In addition, this DAT takes advantage of the feature of digital recording to create a separate area in addition to the audio PCM recording area, and is a formant that can record digital signals other than audio signals at the same time as PCM. It has become. The data written in this area will hereinafter be referred to as subcode data. Various types of subcode data can be considered. For example, recording time, song title, lyrics, etc. Since the subcode data is similar to the above data, data is likely to be lost as time tFI passes. On the other hand, the subcode territory is constant and the recording transmission speed is constant. As described above, in DAT, variable received data must be transferred to a digital transmission path having a fixed transmission rate, and its efficiency is a problem. The data transmission process in the case of the rotating head type DAT (R-DAT) will be specifically described below.

In R-DAT using a rotating head system, two magnetic heads are attached to a rotating drum at an interval of 18 degrees, and rotate at a speed of, for example, 2000 revolutions per minute. By recording data on the tape using two magnetic heads as described above, data for two tracks is recorded within one frame. The above one frame is the period of one rotation of the drum, and within this one frame there are 64
For example, subcode data with bits 1 as 1 pack is 1
28 packs can be recorded. Figure 5(a) shows R-
This indicates the 1-rack format in DAT.
41 is 1 when the magnetic head scans on the magnetic tape 42.
This is the area that touches the area 41 when scanned twice, and the central part of this area 41 contains PCM audio, tml! 43, and subcode areas 44a and 44b are provided near both sides. The subcode 1 back recorded in the subcode order areas 44a and 44b consists of a 4-bit item, 52-bit data, and 8-bit parity, as shown in FIG. 5(b). The above item is the identification code of the subcode data, and is a 4-bit “0 to 15
Indicates modes up to J. This mode includes "one song time", "tape absolute time", etc. as shown in Table 1 below.

Table 1 Also, the above 52-bit data is the data content in the above mode. For example, when the item is "1", 52
The bit data indicates the song time. Further, the above parity is an even parity in which 1 back 64 bits are totaled in units of 8 bits. Therefore, the above variation is
If the exclusive OR is calculated for each of the 8 bits within one back, rOJ is obtained, which becomes pack data rOJ during playback, and is used to check the reliability of packed data during playback.

Therefore, as shown in FIG. 5(C), 128 packs of subcodes from back O to pack 127 can be recorded in one frame, and data having the same item can be recorded multiple times. can. In this case, data having the same item in the same frame are assumed to be the same. Therefore, in one frame, 16 types of items can be written 8 times by n people for each item.

By multiplexing data in this way, data reliability can be sufficiently improved.

However, it is rare for subcode data to have all items in one frame, and between poems and
That number may change over time. For example, it is conceivable that the data group of lyrics changes considerably over time. Conventionally, in such a case, the remaining subcode data part is all ゜゛○′゜, that is, item-Q (
No i nfO r m a j ! On)
This was done by manipulating the numbers to be filled in. However, if all O'' were written in the remaining subcode data part as in the above conventional method, the data area could not be used effectively, and there was also a problem in terms of improving reliability. .

[Object of the Invention] The present invention has been made in view of the above points, and provides a method for efficiently transferring variable received data to a digital transmission path having a fixed transmission rate, and improving reliability. Get digital signal processing 1! ! The purpose is to promote the device.

[Summary of the Invention] The present invention is characterized in that the number of received data within a predetermined period is counted and latched, and the read control circuit is controlled by this latch signal.

[Embodiments of the Invention] Hereinafter, examples of the present invention will be described with reference to the drawings. In FIG. 1, a subcode data generator 11 generates reception data and a data clock DCLK in response to a reception timing signal RT given from a kindergarten section (not shown). That is, the subcode data generator 11 does not operate when the reception timing signal MRT is ``0'', but when it becomes ``1'', it generates the reception data and data clock DCLK, and transfers the reception data to the hl of the changeover switch 12. and outputs the data clock DCLK to the reception control circuit 13. The changeover switch 12 is controlled by the reception timing 1 word RT, and the RT signal is
When O L1, it switches to the Qm side, and when it is "1", it switches to the Hi end side.
A signal is given. Then, the changeover switch 12
Signal 1j taken out from the common terminal of switch 14
It is sent to the first RAM+58 through the f2iIlllM child of R. A M15
sent to b. The changeover switch 14 is controlled by the frame signal FR, and when the frame signal FR is "゛○'', it is switched to the Q terminal side, and when it is "1", it is switched to the H terminal side. FR is a signal obtained by dividing the reception timing signal RT by 1/2.
b as a read/write signal R/W. In this case, a signal FR obtained by inverting the frame signal FR is applied to the first RAM 15a so that the read/write modes of the first RAM 15a and the second RAM 15b are reversed. - On the other hand, the above reception system 6 [1 circuit 13
In addition to inputting the basic clock φ, the RTI-t signal synchronized with the rising edge of the reception timing signal RT and the RTL signal synchronized with the falling edge of the reception timing signal RT are inputted. The above reception control memory 13 is written υ11111 according to the above input signal.
It generates a signal WC and a mask signal MB, the details of which will be described later. And received tII! f)
The control signal WC outputted from the circuit 13 is sent to the first RAMI 5a via the second terminal of the changeover switch 16 controlled by the frame signal FR, and also
It is sent to the second RAM 15b via the 11111 terminal,
Further, the mask signal MB is transmitted to the transmission control circuit 1, the details of which will be described later.
Sent to 7. This transmission fill t2'I1 circuit 11
In addition to the mask signal M B, the RTH signal and the transmission clock T C L K are input to. The transmission control circuit 17 reads out the υ1 signal RC in response to the input signal.
The first R A fvl
+5a and the second RAL via the side terminal.
Output to I15b. And the above-mentioned first RA~115a
The data 91 output from 1 is read out from the second R A M 15b via the h-side screw of the changeover switch 19, which is switched by the frame signal FR.
It is extracted as transmission data via the λ side terminal.

Next, according to FIG. 2, the above-mentioned reception control circuit 13 and transmission control circuit 1
The details of the circuit 11 will be explained. First, details of the reception control circuit 13 will be explained. The data clock DCLK sent from the subcode data generator 11 to the reception control i++ circuit 13 is inputted to the set terminal S of the flip-flop 22 via the delay circuit 21. This flip-flop 22 is reset by the RTH signal, and the signal output from the Q output terminal is input to the clock terminal of the 6-bit counter 25 via the AND circuit 23 and the OR circuit 24 together with the data clock DCLK. be done.

This 6-bit counter 25 counts the signals applied via the OR circuit 24, and converts the carry signal CO into 7 bits.
It is output to the clock terminal of the bit counter 26. Above 6
The bit counter 25 and the 7-bit counter 26 are cleared by the R-H signal, and their count outputs are sent to the determination circuit 27. This judgment circuit 27 constantly checks the counts of the 6-bit counter 25 and the 7-bit counter 26, and outputs a judgment signal DE when the counts become as shown in Table 2.

Table 2 The judgment output from the judgment circuit 27 is No. DE
is input to the reset terminal R of the flip-flop 28 and also to the AND circuit 30 via the inverter 29. Further, the RTL signal is input to this AND circuit 30, and its output signal is input to the set terminal S of the frimbflop 28. And this flip flop 2
The output signal of 8 is input to the AND circuit 31 together with the base clock φ, and the output thereof is input to the OR circuit 24. Further, the output of the AND circuit 31 is taken out through the OR circuit 20 together with the data clock DCLK, and
Together with the count outputs of the 5- and 7-bit counters 26, the write i+II FxI signal ~■C is generated and is sent to the RAMs 15a and 15b via the changeover switch 16 as described above. Further, the count output of the 7-bit counter 26 is sent to the latch circuit 32. This latch circuit 32 latches the count value of the 7-bit counter 2G in response to the RTH signal, and outputs it as a mask signal Me to the transmission control circuit 1.
Output to 7.

The transmission control circuit 17 includes a 13-bit counter 33 and a mask circuit 34. After the 13-bit counter 33 is cleared by the RTH signal, it counts up by the transmission clock TCLK, and the 13-bit count output RCA is sent to the mask circuit 3.
Enter 4. This mask circuit 34, as shown in FIG.
AND circuits 35a to 35Q are interposed for the bits, and the 7-dot mask signal from the reception control circuit 13 is controlled by IB. Then, among the 13-bit RCA signals sent from the 13-bit counter 33, 6 bits of LSB full and the AND circuit 35
A total of 13 bits of 7 bits output from a to 35g becomes the output signal PCB of the mask circuit 2834. Furthermore, this PCB {''6@ and the above transmission clock TC
LK is outputted from the transmission $return circuit 17 as the read $IJ'6II signal RC.

Next, the operation of the above embodiment will be explained with reference to the timing offset in FIG. In addition, the reception timing signal RT switches to high level in the first half and low level in the second half of each frame, as shown in FIG. 4(b). When the frame enters a frame in which the signal @FR is at a low level, the reception timing signal R becomes a high level in the first half of the frame, and the reception data and data clock DCLK are sent from the subcode data generator 11. The timing signal R is 1
Each bit is sent in synchronization with the data clock DCLK. As mentioned above, when the frame signal FR is at a low level and the reception timing signal RT is at a high level, the changeover switches 14, 16, 18, and 19 are set to the λ terminal side, and the changeover switch 12 is set to the h terminal side, as shown in FIG. Switch to the side.

Therefore, the received data from the subcode data generator 11 is transferred to IRAs IRA to 115th via the changeover switches 12 and
Sent to a. Also, at this time, the write control signal WC output from the reception control circuit 13 is sent to the first RAM 15a via the changeover switch 16, and the read control signal RC outputted from the transmission il1 1111 circuit 17 is sent through the changeover switch 18. The data is sent to the second RAM 15b. When the frame signal FR is at a low level, the first RAM 15a is in the write mode and the second RAM 15b is in the read mode, and the received data is written to the first RAM 15a and the second
The stored data can be output from the RAM 15b. This second
The data read from the RAM 15b is transferred to the selector switch 1.
9 as transmission data.

Assuming that pack A and back B data are being sent as received data as shown in FIG. 4(e), the data of packs A and B is transferred to
Written to M15a. The above-mentioned back A and B received data each have a 64-bit configuration as shown in FIG. 4 (1-1>), and each bit is synchronized with the data clock DCLK shown in FIG. The data clock DCLK is outputted from the generator 11.The data clock DCLK is sent to the reception control circuit 13 (not shown in detail in FIG. 2).When the reception timing signal RT rises to a high level, the reception control circuit 13 The flip-flop 22 is reset by the RTH signal generated in synchronization with the rising edge of the flip-flop 22, and
The 6-bit counter 25 and 7-bit counter 26 are reset. In this state, the data clock DCLK output from the subcode data generator 11 is
3 and is delayed for a certain period of time by the delay circuit 21, and the flipflop 22 is set. As a result, the output of the flip-flop 22 becomes "1°" and the gate of the AND circuit 23 is closed. After that, the data clock DCLK sent from the subcode/dake generator 11 is passed through the AND circuit 23 and the OR circuit 24. 6 bit counter 2
5 is input. As a result, the 6-bit counter 25 sequentially counts up as shown in FIG. 4(j). Then, the count of the 6-bit counter 25 {direct (O~6
3) is the digit address and the count value (0) of the 7-bit counter 2G is the row address of the data clock DCL.
It is sent to the first RAM 15a together with K via the changeover switch 16. As a result, in the first RAM 15a, each bit of back A is set to the data clock DCLK at the address determined as 1 by the 6-bit counter 25 and the 7-bit counter 26, that is, in digits 0 to 63 of the ○ row. are written sequentially in synchronization with

On the other hand, in the determination circuit 27, the 6-bit count 25
The count value of the 7-bit counter 26 is constantly judged, and as shown in Table 2 above, the value of the 7-bit counter 26 is "O, 1, 3, 7, 15, 31, 63, 127". When the value of the 6-bint counter 25 reaches "63" while the CPU is in the 6-bint counter 25, a judgment signal @DE is output. At this point, 7
Since the value of the bit counter 2G is "0", the determination circuit 27 outputs the determination signal DE as shown in FIG. Reset. After that, when the data clock DCLK is sent from the subcode data generator 11 together with the back B data, the 6-bit counter 2
5 counts the data clock DCLK and calculates the value in Figure 4 (k
), it outputs the galley signal CO and returns its own count value to "0".

The 7-bit counter 26 counts up by the signal CO outputted from the 6-bit counter 25.
The count value becomes "1" as shown in FIG. 4 (2). Thereafter, the 6-bit counter 25 sequentially counts up by 1 in response to the data clock DCLK sent from the subcode data generator 11, and specifies the address of the first RAM 15a together with the count data of the 7-bit counter 26.

Therefore, this first RAM 15a contains 0163 in the first row.
Pack B data is sequentially written into the digits. Then, when the count value of the 6-bit counter 25 reaches "63" when the count value of the 7-bit counter 26 is "1" as described above, the determination circuit 27 determines the state and outputs the determination signal DE. This state in which the determination signal DE is outputted from the determination circuit 27 continues until the next frame is started, as shown in FIG. 4(m).

As described above, the received data of backs A and B is transferred to the first RA.
~115a, and then the reception timing signal @R
When T falls, the selector switch 12 is switched to the 2-terminal side. As a result, the "O I+" signal is input to the first RAM 15a as the female data, but if the received data is two packs like backs A and B as described above, the flip-flop 28 is in the reset state. gate 1 of the AND circuit 31 is closed, and the output of the basic clock φ is prohibited.For this reason, the first RAM 15a
No data will be stored for.

On the other hand, in the second RAM 15bl, the data stored in the previous frame is read out according to the read control signal RC from the transmission control circuit 17, and the changeover switch
9 as transmission data.

Then, when the above frame ends and the frame signal FR rises to a high level in the next frame, the first R
The AM15a switches to the threading mode, the second RAM 45t) switches to the 8-inclusive mode, and the changeover switches 14 and 1
6, 18, and 19 are switched to the h terminal side.

Also, at this time, the reception timing signal RT becomes high level, so the changeover switch 12 is switched to the h terminal side. Therefore, the received data sent from the subcode data generator 11, for example, the back C. D,E
The data is sent to the second RA~115b, and as described above, the write data is output from the reception control circuit 13.
The information is sequentially stored in the second RA to 115b according to the message @WC. And the data up to pack E is 2nd RA~l15bl
．． : When written, the count of the 7-bit counter 26 becomes "2".

When the count value of the 7-bit counter 26 is "2", even if the count value of the 6-bit counter 25 is "63" as shown in Table 2, the determination circuit 27 outputs the determination signal DE.
There is no output. Therefore, the output of the inverter 29 is "1'
', and then when the reception timing signal RT falls to low level and the RTL signal is applied, the AND circuit 30
The ゜゛1'' signal is not outputted, and the flip-flop 28 is set. Therefore, the output of the flip-flop 28 becomes ``1'', and the gate of the AND circuit 31 is opened.
The basic clock Φ is outputted via the AND circuit 31.

As a result, the 6-bit counter 25 starts counting, and the 6-bit counter 25 and the 7-bit counter 26
The outputs from the counter 1 to the AND circuit 31 and the OR circuit 20
It is sent to the second RA to 115b as a write image signal WC together with the basic clock φ outputted via the write image signal WC. At this point, the changeover switch 12 has been switched to the IJW child side, so the "0" signal is occupied in the empty area of the second RA to 115b.

On the other hand, in the reception control circuit 13, the RTH signal generated at the same time as the rise of the reception timing signal RT at the time of frame switching causes the 7-bit counter 26 to count up, in this case latching "1". , is output to the transmission control circuit 17 as a mask signal MB. This transmission control σ0 circuit 17 is a 13-bit counter 337); RTH
After being cleared by a signal, it performs a count-up operation based on the transmission clock TCLK.

Then, the count data RCA of the 13-pit counter 33 is passed through the mask circuit 34 to the transmission clock TCLK.
It is also sent to the first RA-115a as a read-il1 signal RC. The mask circuit 34 outputs the count data R C . of the 13-bit counter 33 . For A, the upper 7 bits are masked by the mask signal MB, and the first RA
The addresses for packs A and B written in the previous frame are specified in M15a. In this case, the 13-bit counter 33 is cleared by the RTH signal and starts counting from rOJ, so even if the upper 7 bits are masked by the latch data "1" of the latch circuit 32, the upper 7 bits are cleared by the RTH signal. The bit is rOJ.

Therefore, of the received data stored in the first RAM 15a, the O-th pack, that is, the data of back A, is read out and output as transmission data via the changeover switch 19. After that, the first bit of the upper 7 bits becomes "1" due to the count-up operation of the 13-bit counter 33.
The first pack of received data stored in the first RAM 15a, that is, the back B, is outputted as it is through the mask circuit 34, and the data from "0" to "63" is specified.
The data is read out sequentially up to the first row. Thereafter, similarly, in the upper 7 bits of the output data of the mask circuit 34, "○" and "1" alternately change each time the count value of the lower 6 bits goes around due to the masking operation, and the first RAM 15a
Back A and Back B are alternately specified for the target.

As described above, the transmission control circuit 17 controls the first RA to 11
Pack A stored in 5a. The data of B is shown in Figure 4 (
f>, the data is read out repeatedly and continuously, and outputted as transmission data via the changeover switch 19. That is,
The transmission control circuit 17 includes a latch circuit 3 as shown in Table 3 below.
The upper 7 bits of the output data RCA of the 13-bit counter 33 are masked by the mask circuit 34 according to the number of received packs latched to 2, and the first R A M 15a, 15
restricting the address of b and sequentially reading out the stored data;
Output as transmission data.

In this case, the head of the tape recorder contacts the tape in the latter half of the high and low levels of the reception timing signal RT, so the period of contact, that is, for each track, as shown in FIG. As shown in a), reading control of the first RAMs 15a and 15b is performed at timings corresponding to the subcodes vAl44a and 44b at both ends.

Thereafter, when the frame signal FR falls and the next frame is started, the first RAM 15a goes into the 1-input mode and the second RAMi 5b goes into the read mode as described above, and the above-described operations are repeated. In this case, the second RAM 15b contains the pack C. D. The received data of E is embedded, and '
tI! Since data “○” is written in the area, the fourth
As shown in Figure (f), data "0" is read out following the data in packs CXD and E, and is repeatedly output as transmission data.

[Effects of the Invention] As described in detail above, according to the present invention, the number of received data within a predetermined interval is counted and latched, the read control circuit is controlled by this latch signal, and a predetermined data order area is utilized. Since the received data is transferred repeatedly, variable received data can be efficiently transferred and high reliability can be obtained even on a digital transmission path having a fixed transmission rate.

[Brief explanation of drawings]

Figures 1 to 4 show an example of the present invention.
FIG. 1 is a block diagram showing the circuit configuration, FIG. 2 is a block diagram showing details of the reception control circuit and transmission control LIO circuit portion in FIG. 1, and FIG. 3 is a diagram showing details of the mask circuit in FIG. 2. , FIG. 4 is a timing chart for explaining the operation, and FIGS. 5(a) to (C) are track formats in a digital audio tape recorder.
FIG. 3 is a diagram showing a pack format and a frame format. 11...Subcode data generator, 12, 14, 16
, 18, 19... Selector switch, 13... Reception I
I'au circuit, +5a...1st RA~1, 15b...
... 2nd RAM 15, 17... Transmission, I, 11 question circuit, 21... Delay circuit, 25... 6-bit count,
2G... 7-bit counter, 27... Judgment circuit, 3
2...Latch circuit, 33...13-bit counter,
34...Mask circuit.

Claims (1)

[Claims] In a digital signal processing device that transfers variable digital reception data to a digital transmission path having a fixed transmission rate, there is provided a memory for storing digital reception data, and a first counter that counts the number of transmitted digital reception data within a predetermined period. and means for writing the digital reception data into the memory according to the count number of the first counter;
a latch circuit that stores the value counted by the first counter; a second counter that counts in accordance with a fixed clock; and means for changing the count value of the second counter based on latch data of the latch circuit. and means for reading and transferring data stored in the memory according to the value changed by the means.