KR940001053Y1 - Frame number detecting circuit for data backup device - Google Patents

Abstract

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Description

Frame Number Detection Circuit of Data Backup Device

1 is a diagram for explaining a group format recorded on a general digital audio tape (DAT).

2A is a diagram for explaining data allocation in a main area of a DAT.

FIG. 2B is a diagram for explaining bit by bit inside the allocated head data area according to FIG. 2A; FIG.

3 is a block diagram of a frame number detection circuit according to the present invention.

4 is a detailed circuit diagram of a frame number detection circuit according to FIG.

5 is an operation waveform diagram of a frame number detection circuit according to FIG.

* Explanation of symbols for main parts of the drawings

10: DAT driver 20: S / P converter

30: counter 40: timing selector

50: buffer memory

The present invention relates to a frame number detection circuit in a data back-up apparatus for recording and reproducing data carried on a digital audio tape, and in particular, a frame number for re-reading a phenomenon in which frame data overlaps during recording and a frame in which an error occurs during playback. It relates to a detection circuit.

In general, a digital data storage (DDS) format proposed by HEWLETT-PACKARD / SONY is widely used as a data format for reproducing a recorder such as a data file mark or a save set mark rather than music data on a digital audio tape. .

In such a digital audio tape (hereinafter referred to as DAT), a frame arrangement form of a group consisting of the records is shown in FIG.

According to FIG. 1, a group consists of 22 frames, and an amble including an ECC (Error Correction Code) frame for error correction and zero (0) data of an adjustment frame between the group and the group. ) Frame.

FIG. 2A is a diagram for explaining data allocation in each frame constituting a group, and FIG. 2B is a diagram for explaining, logically, the logical frame identification area of the head data area allocated in the frame of FIG. 2A.

In FIG. 2A, one frame is composed of two tracks of plus (+) and minus (-) azimuth. In addition, 4 bytes of head data having an area designated by the frame number, a 5756 user data area usable by the user, and 64 bytes of zero data are allocated. That is, word number 0 is format information called a header, and is assigned to one group of frame numbers 1 to 22 in the logical frame identification (LF-ID) area, and the DF-ID. (Data Frame Identification), the TBD part is filled with zeros. Word numbers 1 to 1439 are data areas used, and word numbers 1440 to 1456 are filled with " 0 ". That is, 5760symbol is recorded in one frame and 5824 bytes are allocated in total.

According to FIG. 2B, the LF-ID region indicates an amble frame when the least significant bit is "0" from 6 bits, and the frame numbers "1" through "10110" indicate frame numbers 1 through 22, and the seventh bit is A " 1 " indicates that an ECC frame exists, and a " 0 " indicates only a frame number other than an " ECC frame. &Quot; A most significant bit indicates a last frame of the group. "0" indicates another frame of the group.

Here, one frame is composed of two channels (Achannel and Bchannel), and each of A and B channels has an IF-ID area where the same frame number is stored. At this time, the LF-ID number is given when the data transmitted from the host PC is recorded in the DAT.

At this time, LF-ID detection is necessary in order to make the tape recognize the frame area when a data error occurs or to read back the frame area where a data error occurs during playback.

Accordingly, it is an object of the present invention to provide a circuit for detecting a frame number for reproducing a phenomenon in which frame data overlaps during recording and a frame in which an error occurs during reproduction in a data backup apparatus using a DAT.

In order to achieve the above object, there is provided a data backup device having a DAT recording and reproducing apparatus for recording and reproducing data loaded on a DAT and a buffer memory for interfacing the data reproduced from the DAT recording and reproducing apparatus to a computer. Conversion means for converting the serial data output to the DAT recording and reproducing apparatus into parallel data, position detecting means for detecting the LF-ID position carried in the DAT according to a timing control signal output from the DAT recording and reproducing apparatus; And timing selection means for outputting only the LF-ID according to the detection signal of the position detecting means from the output of the converting means.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the frame number detection circuit of the data backup device according to the present invention.

3 is a block diagram of a frame number detection circuit of the data back-up apparatus according to the present invention.

The DAT driving unit 10 records data transmitted from a PC at the time of recording to the DAT or, at the time of reproduction, picks up the information recorded in the DAT, processes the signal, and outputs the serial data.

The S / P converter 20 converts parallel data transmitted from the PC into serial data at the time of recording and outputs the serial data to the DAT driver 10, and reproduces the serial data output from the DAT driver 10 at the time of reproduction. The data is converted into data and output to the buffer memory 50.

The counter 30 counts a timing clock signal corresponding to the data bit rate from the timing control signal output from the DAT driver 10.

The timing selector 40 performs a logical operation on the data output from the S / P converter 20 and the output of the counter 30, and then outputs an LF-ID number.

The buffer memory 50 outputs the data transmitted from the host PC to the S / P converter 20 or outputs the output data of the S / P converter 20 to the host PC.

4 is a detailed circuit diagram of a frame number detection circuit of the data backup device according to the present invention according to FIG.

4, the serial data output terminal 11 of the DAT driver 10 is connected to the input terminal of the S / P converter 20, and the frame start control signal output terminal 12 is the first NAND gate G1. The terminal 15 for outputting four times the frame sampling signal to the first input terminal and the clear terminal CLR of the counter 30 is connected to the input terminal of the first inverter INV1 and the reference timing signal output terminal BCK. Are connected to the input terminals of the S / P converter 20, respectively.

The output terminal of the first inverter INV1 is connected to the one input terminal of the AND gate G4 and the second input terminal of the S / P converter 20.

The second input terminal of the first NAND gate G1 is connected to the output terminal of the second NAND gate G2, and the output terminal is the second input terminal of the AND gate G4 and the first terminal of the second NAND gate G2. Connect to the input terminal. The second input terminal of the second NAND gate G2 is connected to the output terminal of the third NAND gate G3. The output terminal of the AND gate G3 is connected to the clock input terminal CLK of the counter 31.

The first output terminal Q0 of the counter 31 is a first input terminal of the third NAND gate G3, a first input terminal of the first NOR gate G5, and a third of the second NOR gate G6. At the input terminal, the second output terminal Q2 is at the input terminal of the second inverter INV2, at the input terminal of the third inverter INV3 and at the second input terminal of the second noar gate G6, and at the third output terminal. Q3 is connected to an input terminal of the fourth inverter INV4, a first input terminal of the third NAND gate G3, and a third input terminal of the first NOR gate G5, respectively.

The output terminal of the second inverter INV2 is connected to the second input terminal of the third NAND gate G3, and the output terminal of the third inverter INV3 is connected to the second input terminal of the first NOR gate G5 and the fourth inverter. The output terminal of INV4 is connected to the first input terminal of the second NOR gate G6.

The first input terminal of the oar gate G7 is the output terminal of the first noar gate G5, the second input terminal is the output terminal of the second noar gate G6, and the output terminal is the first to eighth ends. It is coupled to the first input terminal of the gates G11 to G18, respectively.

The 8-bit parallel data output terminal of the S / P converter 20 has a first to eighth data input terminal of the buffer memory shown in FIG. 3 and a second input terminal of the first to eighth gates G11 to G18. Are connected to each. An 8-bit LF-ID is output from the first to eighth gates G11 to G18.

Next, the operation of FIG. 4 will be described in conjunction with the waveform of FIG.

According to FIG. 4, the frame synchronization clock pulse FSYNC CP output from the DAT driver 10 is shown in FIG.

Since the frame synchronization signal has a period of 30ms in which the rotation drum of the DAT forms two tracks (or channels) in one rotation, the frame synchronization signal can process one frame data, that is, head data and user data shown in FIG. do.

The frame sampling signal Fs output from the DAT driver 10 is shown in (b) of FIG. 5, and the double frame sampling signal (2Fs) is shown in (c) of FIG. The frame sampling signal 4Fs of is shown in Fig. 5D.

The frame start control signal FRAME START shown in (e) of FIG. 5 is input as a clear signal of the counter 30 output from the DAT driver 10 at the rising edge of the signal shown in (a) of FIG. To clear the counter 30.

The signal shown in FIG. 5F is a reference timing signal BCK that processes data in the DAT driver 10 and generates 650 ns periodically. The S / P converter 20 performs one-bit data processing for 650 ns based on the clock shown in (e) of FIG. 5, and the signal shown in (g) of FIG. 5 corresponds to the reference timing signal (FIG. 5). According to (f)), the waveform in which 8-bit data is output is enlarged.

The S / P converter 20 converts 8-bit parallel data transmitted from a personal computer and output from the buffer memory 50 shown in FIG. 3 into serial data at the time of recording, and outputs the serial data to the DAT driver 10 for playback. Next, serial data output from the DAT driver 10 is converted into 8-bit parallel data.

Here, the data waveforms output from the DAT driver 10 during playback and input to the S / P converter 20 are shown in FIG. 5 (h), and the data waveforms output from the S / P converter 20 are shown. The waveform is delayed in the 8-bit data transfer period as shown in Fig. 5 (i).

That is, as in the user data area shown in FIG. 2A, first, 8 bits of zero data, 8 bits of LF-ID, 8 bits of zero data, and 8 bits of LF-ID that are 4 bytes of header are included. After being output, it is output as user data D0 to D5755. The waveforms of the signals output from the first to third output terminals Q0 to Q2 of the counter 30 are shown in (j) to (l) of FIG.

The first output signal Q0 of the counter 30, the inverted signal of the second output signal Q1, the first NOR gate G5 input to the third output signal Q2, and the first output signal of the counter. Waveforms of the output signal of the second NOR gate G6 inputted with the inverted signal of Q0, the second output signal Q2, and the third output signal Q3 are shown in (m) and (n) of FIG. It is.

The output signal waveforms of the noah gate G7 in which the outputs of the first and second noah gates G5 and G6 are ORed are shown in FIG. 5 (o).

On the other hand, the waveform of the output signal of the first NAND gate G1 is shown in (p) of FIG. 5, and the waveform of the output signal of the third NAND gate G3 is shown in (q) of FIG.

8 bits during the LF-ID data output timing by logically multiplying the output signal of the S / P conversion section 20 (i in FIG. Outputs LF-ID data.

As described above, the frame number detection circuit of the data backup apparatus according to the present invention prevents overlapping of frame data during recording by detecting the LF-ID when a data error occurs and rereads a frame in which an error occurs during playback. It can be shipped so that error correction can be easily performed.

Claims (3)

A data backup device having a DAT recording and reproducing apparatus for recording and reproducing data loaded on a DAT and a buffer memory for interfacing the data reproduced from the DAT recording and reproducing apparatus to a computer, the data backup apparatus being output to the DAT recording and reproducing apparatus. Conversion means for converting serial data into parallel data, position detection means for detecting the LF-ID position loaded on the DAT in accordance with a timing control signal output from the DAT recording and reproducing apparatus, and the position from the output of the conversion means. And a timing selecting means for outputting only LF-ID data in accordance with a detection signal of the detecting means. 2. The data backup apparatus according to claim 1, wherein said position detecting means includes a counter with a clock corresponding to a data bit when the LF-ID position on said DAT, and a logic circuit for logically calculating said counter output. Frame number detection circuit. The method of claim 1, wherein the timing selecting means comprises a plurality of logic circuits for calculating the LF-ID data carried on the output of the converting means so that the position detecting end outputs the parallel data according to the output. Frame number detection circuit of a data backup device.