JPS5999556U - phase synchronized circuit - Google Patents
phase synchronized circuitInfo
- Publication number
- JPS5999556U JPS5999556U JP19502082U JP19502082U JPS5999556U JP S5999556 U JPS5999556 U JP S5999556U JP 19502082 U JP19502082 U JP 19502082U JP 19502082 U JP19502082 U JP 19502082U JP S5999556 U JPS5999556 U JP S5999556U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- phase
- phase synchronized
- serial
- synchronized circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の位相同期回路のブロック図、第２図は本
考案の位相同期回路の一実施例のブロック図、第３図は
第２図の各部信号タイムチャート図である。
１・・・フレーム同期回路、２・・・直列並列変換回路
、３・・・クロック位相比較回路、４・・・書き込みタ
イミング制御回路、５・・・書き込みアドレスカウンタ
、６・・・メモリ、７・・・読み出しアドレスカウンタ
、８・・・並列直列変換回路、９・・・アドレス制御回
路、１０．１１・・・分周回路。FIG. 1 is a block diagram of a conventional phase-locked circuit, FIG. 2 is a block diagram of an embodiment of the phase-locked circuit of the present invention, and FIG. 3 is a time chart of signals of each part of FIG. 2. DESCRIPTION OF SYMBOLS 1... Frame synchronization circuit, 2... Serial parallel conversion circuit, 3... Clock phase comparison circuit, 4... Write timing control circuit, 5... Write address counter, 6... Memory, 7 . . . Read address counter, 8. Parallel-serial conversion circuit, 9. Address control circuit, 10.11. Frequency division circuit.
Claims (1)
クロックの位相比較回路と、書込みカウンタと読み出し
カウンタと書き込み制御回路とより成る位相同期回路に
おいて、フレームの第１ビツトから順に出力する直列並
列変換回路と、複数のメモリと、並列直列変換回路とを
設けた事を特徴とする位相同期回路。 。 ノ[Claims for Utility Model Registration] In a phase synchronization circuit consisting of a frame synchronization circuit, a memory, a phase comparison circuit for an external manual clock and an internal clock, a write counter, a read counter, and a write control circuit, A phase synchronized circuit characterized by having a serial-to-parallel conversion circuit that sequentially outputs outputs, a plurality of memories, and a parallel-to-serial conversion circuit. . of
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19502082U JPS5999556U (en) | 1982-12-24 | 1982-12-24 | phase synchronized circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19502082U JPS5999556U (en) | 1982-12-24 | 1982-12-24 | phase synchronized circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5999556U true JPS5999556U (en) | 1984-07-05 |
Family
ID=30418992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19502082U Pending JPS5999556U (en) | 1982-12-24 | 1982-12-24 | phase synchronized circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5999556U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01221948A (en) * | 1988-02-29 | 1989-09-05 | Nec Corp | Multiplexing circuit and multiplex separation circuit for digital signal |
| JPH03259637A (en) * | 1990-03-09 | 1991-11-19 | Fujitsu Ltd | Asynchronous data access system for ram |
-
1982
- 1982-12-24 JP JP19502082U patent/JPS5999556U/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01221948A (en) * | 1988-02-29 | 1989-09-05 | Nec Corp | Multiplexing circuit and multiplex separation circuit for digital signal |
| JPH03259637A (en) * | 1990-03-09 | 1991-11-19 | Fujitsu Ltd | Asynchronous data access system for ram |
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