JPH03259637A - Asynchronous data access system for ram - Google Patents

Abstract

PURPOSE:To attain transmission reception of sure data by comparing the phase of a readout control signal with the phase of a load timing signal and shifting the phase of the readout control signal by a prescribed phase from a usual location when the signal phases are overlapped. CONSTITUTION:A write control signal WE and a readout control signal OE to/from a RAM 1 are generated by using a reception clock synchronously with a reception data R DATA when write/readout of an asynchronous data to/from the RAM 1 is implemented via an S/P converter 2 and a P/S converter 3, a comparator 8 compares the phase of the readout control signal OE with the phase of a load timing signal P/S LOAD TIM for the P/S converter and a phase shift control section 9 shifts a prescribed bit number from the usual position for the phase of the readout control signal OE when the phases of the signals are overlapped.

Description

[Detailed description of the invention] [Table of contents Overview Industrial field of application Prior art (Figure 5) Means for solving the problem to be solved by the invention (Figures 1 and 2) Effect (Figure 5) 1
, 2) Embodiment (Figures 3 and 4) Effects of the invention [Summary] Regarding the data access method when asynchronous data is written to or read from RAM via a serial/parallel converter and a parallel/serial converter. , The purpose is to ensure that asynchronous data can be read and written based on the RAM read/write control signal generated from one side of the asynchronous transmitted and received data, and the asynchronous data is transmitted through a serial/parallel converter and a parallel/serial converter. When writing to or reading from RAM, create a write control signal and a read control signal from the receive clock or transmit clock to the RAM, and compare the phase of the read control signal and the load timing signal for the parallel/serial converter. Alternatively, compare the phases of the write control signal and the load timing signal for the serial/parallel converter, and if these signal phases overlap, shift the phase of the read control signal or write control signal by the required bit from the normal position. Configure.

[Industrial Field of Application] The present invention relates to a data access method when asynchronous data is written to or read from a RAM via a serial/parallel converter and a parallel/serial converter.

[Prior Art] A conventional data access method to a RAM will be described. FIG. 5 is a block diagram for explaining a conventional RAM synchronous data access method. In FIG. 5, 101 is a RAM (random access memory);
2 is a serial/parallel converter (S/P converter), 10
3 is a parallel/serial converter (CP/S converter), 10
4 is a pulse generator, which receives serial data (RDA).
TA) is converted into n-bit parallel data by the S/P converter 102 and stored in the RAM 101, and
The data stored in this RAMl0I is transferred to the P/S converter 1.
03, it is converted into transmission serial data (SDATA) and output. And RAMl0I
, S/P converter 102. The operating state of the P/S converter 103 is controlled by a control signal generated from a common master clock by a pulse generator 104.

[Problem M to be Solved by the Invention] Incidentally, there are cases where a transmitting device and a receiving device are separated and it is necessary to read and write transmitted and received data to and from the RAM asynchronously with each other.

However, when handling such asynchronous data that is sent and received, the above-mentioned conventional method has a problem.

The present invention was devised under these circumstances, and is an asynchronous RAM method that enables reliable reading and writing of asynchronous transmitted/received data based on a RAM read/write control signal created from one side of the asynchronous transmitted/received data. Its purpose is to provide a data access method.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention according to claim 1.

In this FIG. 1, 1 is a RAM, and this RAM 1 is
Asynchronous data is stored at a required address, and reading and writing thereof is performed by a read control signal OE and a write control signal WE.

2 is a serial/parallel converter (S/P converter), and this S/P converter 2 converts received serial data RDATA into n-bit parallel data.

3 is a parallel/serial converter (P/S converter), and this P/S converter 3 converts n-bit parallel data from the RAMI into transmission serial data SDATA.

4.5 is a pulse generator, and the pulse generator 4 generates signals (reception clock RCLK,
It receives the reception timing signal R (IM) and generates a required pulse signal, and this pulse signal is sent to the S/P converter 2. It is supplied to a write control signal generator 6 and a read control signal generator 7.

Further, the pulse generator 5 receives a signal (transmission clock SCLK, transmission timing signal STIM) synchronized with the transmission data S DATA and generates a required pulse signal, and this pulse signal is transmitted to the P/S. Converter 3 and comparator 8 are supplied.

6 is a write control signal generator, and this write control signal generator 6 receives the received data RDAT from the pulse generator 4.
A write control signal WE is generated in response to a signal generated by a reception clock synchronized with A, and this write control signal WE is input to the write control terminal of the RAM1.

7 is a read control signal generator, and this read control signal generator 7 receives the received data RDAT from the pulse generator 4.
A read control signal OE is generated in response to a signal generated from a reception clock synchronized with A, and this read control signal OE is input to the read control terminal of the RAM 1 and the comparator 8.

8 is a comparator, and this comparator 8 receives the read control signal ○E from the read control signal generator 7 and the load timing signal P/S LO for the P/S converter from the pulse generator 5.
It compares the phase with AD TIM, and when these signal phases overlap, a signal to that effect is output.

9 is a phase shift control section, and this phase shift control section 9 is
When receiving a signal from the comparator 8 indicating that the above signal phase overlap is detected, it outputs a control signal to the readout control signal generator 7 to shift the phase of the readout control signal OE from the normal position by the required bits. be.

FIG. 2 is a block diagram of the principle of the present invention according to claim 2.

In this FIG. 2, RAMI, S/P converter 2, P/
Since the S converter 3 is the same as that shown in FIG. 1 described above, its explanation will be omitted.

4' and 5' are pulse generators, and the pulse generator 4' receives a signal (reception clock RC) synchronized with reception data RDATA.
It receives the reception timing signal (LK, reception timing signal (IM)) and generates the required pulse signal, and this pulse signal is
Supplied to P converter 2 and comparator 8. The pulse generator 5' also generates signals synchronized with the transmission data S DATA (transmission clock S CLK, transmission timing signal S T
IM) and generates the required pulse signal.
This pulse signal is sent to the P/S converter 3. It is supplied to a write control signal generator 6' and a read control signal generator 7'.

6' is a write control signal generator, and this write control signal generator 6' receives transmission data S from the pulse generator 5'.
A write control signal WE is generated in response to a signal generated by a transmission clock synchronized with DATA, and this write control signal WE is input to the write control terminal of RAMI and the comparator 8'.

7' is a readout control signal generator, and this readout control signal generator 7' receives transmission data S from the pulse generator 5'.
It receives a signal generated from a transmission clock synchronized with DATA and generates a read control section ○E, and this read control signal ○E is input to the read control terminal of RAMI.

8' is a comparator, and this comparator 8' receives the readout control signal OE from the readout control signal generator 7' and the load timing signal S/P converter from the pulse generator 4'.
It compares the phase with P LOAD TIM, and when these signal phases overlap, a signal to that effect is output.

9' is a phase shift control section; this phase shift control section 9'
When receiving a signal from the comparator 8' indicating that the overlapping signal phases have been detected, it sends a control signal to the write control signal generator 6' to shift the phase of the write control signal WE by the required bits from the normal position. This is what is output.

[Function] In the RAM asynchronous data access method of the present invention as set forth in claim 1 above, when writing or reading asynchronous data to or from the RAM 1 via the S/P converter 2 and the P/S converter 3, As shown in Fig. 1, generates a write control signal WE and a read control signal ○E from the reception terminal synchronized with the reception data RDATA to RAMI, and also creates a read control signal ○E and a read control signal ○E for the P/S converter. Load timing signal P/S LOAD TIM
The comparator 8 compares the phases of the readout control signal OE and the readout control signal OE, and when these signal phases overlap, the phase shift control section 9 shifts the phase of the readout control signal OE by a required bit from the normal position.

Further, in the RAM asynchronous data access method of the present invention according to claim 2, when asynchronous data is written to or read from the RAMI via the S/P converter 2 and the P/S converter 3, the method shown in FIG. As shown in the figure, from the transmission clock synchronized with the transmission data S DAT,A
Write control signal WE and read control signal OE to
At the same time, write control signal WE and S/P converter load timing signal S/P LOAD TIM are generated.
When these signal phases overlap, the phase shift control section 9' shifts the phase of the write control signal WE by a required bit from the normal position.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

Now, in this embodiment, the SONE data is processed in the overhead bit processing unit of the data transmission system.
T) Specification 5ECTION/LINE/PAT) l 0
When sending the J1 byte (service byte) of VERBYTE to or receiving it from the microprocessor unit (MPU), this information is temporarily stored in RAM.
This relates to the access method when storing data in I.

That is, as shown in FIG. 3 (a block diagram showing an embodiment of the present invention), a service bit insertion/extraction section 20 is provided, and this service bit insertion/extraction section 20 receives one channel of data RDATA. Then, this is sent to the MPU, and the data from the MPU is taken out as data for five channels S DATAI to S DATA5. Note that for each channel for transmission, clocks S P/S CLKI to S P/S
CLK5 [Figure 4 (17), (20), (23),
(26), (29)], timing clock S T
IMI~S TIM5 [Figure 4 (16) (19), (
22), (25), and (28), and for the receiving channel, the clock RCLK [see FIG. 4 (2)]
, and a timing clock RTIN [see FIG. 4 (1)].

Further, a dual port RAM 1 is provided between the service bit insertion/extraction section 20 and the MPU via a path line.
When transmitting and receiving data [see FIG. 4 (4) to (11)] with U, the data can be temporarily stored in this dual port RAMI. The write/read control of this dual port RAMI is performed by a read control signal ○E [see FIG. 4 (13)] and a write control signal WE [see FIG. 4 (14)].

By the way, the service bit insertion/extraction unit 20 is connected to the S/P converter 2. Pulse generator 4, P/S converters 31-35 for 5 channels, pulse generators 51-55, write control signal generator 6. Read control signal generator7. Comparator 89 Ring counter 9 as a phase shift control section. Gate part 1
0. Data latch 11. It is equipped with an address generator 12.

Here, the S/P converter 2 converts the received serial data RDA
TA [see FIG. 4 (3)] is converted into, for example, 8-bit parallel data [see FIG. 4 (4) to (11)].

Each of the P/S converters 31 to 35 is a dual port R.
8-bit parallel data from AMI [Figure 4 (4) ~
(11)] as serial data S DATAI~S
This is to convert it to DATA5.

The pulse generator 4 receives a signal synchronized with the received data RDATA (reception clock RCLK [see Figure 4 (2)), reception timing signal RTIM E (see Figure 4 (1)), and generates a required pulse signal. The pulse signal is generated by the S/P converter 2. Write control signal generator6.
Read control signal generator7. Day clutch 11. The data is supplied to the address generator 12.

In addition, pulse generators 5 to 55 transmit data S DA
Signal synchronized with DATA5 (transmission clock S P/S CLK1 to S P/S CLK5 [4th
Figures (17), (20), (23), (26), (29)
Reference], transmission timing clock S TIMI~ST
IM5 [Figure 4 (16), (19), (22), (2
5), (28)) and generates the required pulse signal, and among the pulse signals, S P/S CL
KI to SP/S CLK5 are each P/S converter 31
~35, and the load timing signal P
/S LOAD TIMI~P/S LOAD TIM
5 [Figure 4 (18), (21), (24), (27)
, (30) are supplied to the comparator 8 via the gate section 10, respectively.

The write control signal generator 6 uses a reception clock RCLK that is synchronized with the reception data RDATA from the pulse generator 4.
The write control signal WE [see Fig. 4 (14)] is generated in response to the signal generated from [see Fig. 4 (2)], and this write control signal WE is transmitted to the write control terminal of the dual port RAMI. is input to.

The read control signal generator 7 generates a reception clock RCLK that is synchronized with the reception data RDATA from the pulse generator 4.
[Refer to Figure 4 (2)] The read control signal ○E [Refer to Figure 4 (13)] is generated in response to the signal generated from the dual port R.
It is input to the read control terminal of AMI and the comparator 8.

The comparator 8 receives the read control signal OE from the read control signal generator 7 and the pulse generator 5 via the gate section 10.
Load timing signal for P/S converter from 1 to 55 P/S LOAD TIMI to P/S LOAD TI
M5 [Figure 4 (18), (21), (24), (27
), (30) The reference phase is compared, and when these signal phases overlap, a signal to that effect is output.

When the ring counter 9 receives a signal from the comparator 8 indicating that the above signal phase overlap is detected, the ring counter 9 sends a control signal to the read control signal generator 7 to shift the phase of the read control signal OE by a required bit from the normal position. This outputs the following.

The gate section 10 receives P/S from the pulse generators 51 to 55.
Load timing signal P/S LOAD T for converter
IMI~P/S LOAD TIM5 [Figure 4 (18
), (21), (24), (27), and (30) are passed to the comparator 8, for example, an OR gate is used.

The data latch 11 latches data read from the dual port RAMI, and the address generator 1
2 generates a write address and a read address to the dual port RAMI. Note that FIG. 4 (15) is data latch output (8 bits), and FIG. 4 (12) is address control data.

With the above configuration, asynchronous data is sent to the dual port RA via the S/P converter 2 and the P/S converters 31 to 35.
When writing to or reading from M1, the write control signal generator 6 and the read control signal generator 7 each generate a reception clock RCLK [Fig. 4 (2)] synchronized with the reception data RDATA [see Fig. 4 (3)]. )reference]
Write control signal WE from to dual port RAM1
[See Figure 4 (14)] and read control signal ○E
[Refer to FIG. 4 (13), and at the same time create the readout control signal OE and the rotary timing signal P/S LOAD TIMI to P/S LOAD TI for the P/S converter.
M5 [Figure 4 (1B), (21), (24), (27
), (30) The comparator 8 compares the phases of the reference signals, and when these signal phases overlap, the ring counter 9
Then, the phase of the read control signal ○E is shifted by the required bits from the normal position [see part A in FIG. 4 (13)].

As a result, after this phenomenon, P/
Load timing signal P/5LOAD T for S converter
IMI~P/S LOAD TIM5 [Figure 4 (18
).

(21), (24), (27), and (30) references and the read control signal OE [see Figure 4 (13)] no longer overlap, making it possible to reliably read data from the dual port RAM 1. It becomes possible.

Note that after that, if the readout control signal OE and the load timing signal P/S LOADTIM for the P/S converter are
Even if the phase overlaps with the I-P/S LOAD TIM5, the same operation is performed again to avoid signal mismatch.

In this way, when reading and writing asynchronous serial data via the dual port RAM 4, it is possible to reliably avoid inconvenient timing, thereby making it possible to reliably exchange data.

Also, when writing or reading asynchronous data to or from RAM 1 via S/P converter 2 and P/S converter 3, RAM 1 is
Write control signal WE and read control signal OE to
At the same time, compare the phase of the write control signal ○E and the load timing signal of the S/P converter.
When these signal phases overlap, R
Inconvenient timing when reading and writing asynchronous serial data via AM1 can be avoided, and reliable data exchange is also possible in this way.

Note that in the above embodiment, the write control signals WE,
Read control signal ○E, load timing signal P/S
Since LOAD TIMI to P/S LOAD TIM5 are inverted signals, they should be marked with a bar, but they are omitted in the specification.

[Effects of the Invention] As detailed above, according to the RAM asynchronous data access method of the present invention as set forth in claim 1, asynchronous data is written to the RAM via the serial/parallel converter and the parallel/serial converter. When reading or writing, a write control signal and a read control signal to the RAM are created from a reception clock synchronized with the received data, and the phase of the read control signal and the load timing signal for the parallel/serial converter is adjusted. When these signal phases overlap, the phase of the readout control signal is shifted by the required bits from the normal position, which eliminates inconvenient timing when reading and writing asynchronous serial data via RAM. This has the advantage of allowing reliable data exchange.

Further, in the asynchronous data access method of the RAM of the present invention according to claim 2, when writing or reading asynchronous data to or from the RAM via the serial/parallel converter and the parallel/serial converter, synchronization is performed with the transmitted data. A write control signal and a read control signal from the transmission clock to the RAM are created, and the phases of the write control signal and the load timing signal of the serial/parallel converter are compared, and if these signal phases overlap, , the phase of the write control signal is shifted by the required bits from the normal position, thus avoiding inconvenient timing when reading and writing asynchronous serial data via the RAM, similarly to the invention as claimed in claim 1 above. This has the advantage of enabling reliable data exchange.

[Brief explanation of drawings]

Figures 1 and 2 are block diagrams of the principle of the present invention, Figure 3 is a block diagram showing an embodiment of the present invention, Figure 4 is a time chart explaining the operation of an embodiment of the present invention, and Figure 5. 1 is a block diagram showing a conventional example. In the figure, 1 is a RAM, 2 is an S/P converter, 3 is a P/S converter, 4.4' and 5.5' are pulse generators, 6.6' is a write control signal generator, and 7. 7' is a read control signal generator, 8 is a comparator, 9 is a ring counter (phase shift control section), 9' is a phase shift control section, 10 is a gate section, 11 is a data latch, 12 is an address generator, 20 is a Service bit insertion and extraction part. 31 to 35 are P/S converters, and 51 to 55 are pulse generators.

Claims (2)

[Claims] (1) Asynchronous data serial/parallel converter (2)
and RAM via parallel/serial converter (3)
When writing to or reading from RAM (1), a write control signal and a read control signal to the RAM (1) are created from a reception clock synchronized with received data, and the read control signal and the parallel/serial converter are (3
), compare the phase with the load timing signal for
An asynchronous data access method for RAM, characterized in that when these signal phases overlap, the phase of the read control signal is shifted by a required bit from the normal position. (2) Asynchronous data serial/parallel converter (2)
and RAM via parallel/serial converter (3)
When writing to or reading from RAM (1), create a write control signal and a read control signal to the RAM (1) from a transmission clock synchronized with the transmission data, and use the write control signal and the serial/parallel converter. (2
) and a load timing signal, and when these signal phases overlap, the phase of the write control signal is shifted by a required bit from the normal position.