JPH05110588A - Data phase converting system - Google Patents

Abstract

PURPOSE:To obtain the data phase converting system which can execute a conversion of high speed data by a simple circuit configuration and can minimize a data delay time which follows the conversion. CONSTITUTION:A data phase converting circuit to which the data phase converting system is applied is provided with a shift register 10 having the number of stages of the maximum value of a control delay value and for outputting data inputted by a shift clock, a counter means 12 corresponding to the number of bits in a frame of synchronizing data, a control means 14 in which the control delay value in each time slot is stored, and which executes an output of a selection control signal in replacement of the time slot in accordance with this delay value, and a selecting means 18 for inputting the data outputted from the shift register 10 and selecting and outputting this data in accordance with the selection control signal inputted from the control means 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data phase conversion system, and more particularly to a data phase conversion circuit for exchanging data time slots.

[0002]

2. Description of the Related Art Conventionally, a circuit of this type is disclosed in, for example, Japanese Patent Application Laid-Open No. 2-121439. Here, a conventional technique of a time switch circuit is shown, and time slots of serial data are exchanged. 3 and 4 are block diagrams of the time switch circuit in this conventional technique. That is, as shown in the figure, in this circuit, a data buffer that temporarily holds serial input data and an address control that controls writing / reading of serial data to / from this data buffer in accordance with a predetermined time slot replacement.・ Memory
The circuit is a combination of ROMs.

[0003]

However, since such a conventional technique is a time switch circuit, it requires a data buffer circuit and an address control memory circuit capable of writing / reading at an arbitrary address. Therefore, for example, when applied to a device in which time slot replacement of input data can be semi-fixedly set, there is a drawback that the device realized by these circuits becomes relatively large.

The present invention eliminates the above-mentioned drawback of an increase in circuit scale and makes it possible to convert high-speed data by adopting a simpler circuit configuration, and a data phase conversion system capable of minimizing the data delay time accompanying the conversion. The purpose is to provide.

[0005]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention is a data phase conversion system for inputting synchronous data and outputting by exchanging time slots of this synchronous data. The delay amount of each time slot in the time slot replacement pattern is calculated, the maximum advance value with the smallest delay amount is selected from this delay amount, and the absolute value of the maximum advance value is calculated for each time slot delay. The control delay value is calculated by adding it to the amount, and the maximum value among the control delay values is set as the number of stages of the shift register for inputting the synchronous data, and these control delay values are used for switching the phase of the time slot of the synchronous data. The synchronous data is input to the shift register by the clock whose synchronous clock is the shift clock, and the synchronous data is generated according to the selection control signal. By shifting stage output of the shift register are sequentially selected in synchronism with the shift clock, switching of the time slots is performed.

Further, according to the present invention, in the above-described data phase conversion system, the data phase conversion circuit to which this system is applied has a maximum number of control delay values and the data input by the shift clock. A shift register for outputting, a counter means corresponding to the number of bits in the frame of the synchronous data, a control delay value in each time slot are stored, and a selection control signal for time slot replacement is output according to this delay value. It has a control means and a selection means for inputting the data output from the shift register and selectively outputting this data according to a selection control signal input from the control means.

[0007]

Embodiments of the data phase conversion method according to the present invention will now be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, there is shown an embodiment of a data phase conversion circuit to which the data phase conversion method according to the present invention is applied. As shown in the figure, this data phase conversion circuit is a time switch circuit for exchanging the time slots of the input data and outputting the same. The shift registers 10-1 to 10-n and the m-ary counter 1 are connected in series.
2, ROM 14, decoder 16 and selector 18.

The shift register 10 is a data holding circuit for serially inputting synchronous data and temporarily holding it, and the shift registers 10-1 to 10-n constitute an n-stage shift register. Each of the shift registers 10 inputs and outputs data by the shift clock 100. That is, the shift registers 10-1 to 10-n
-1 outputs the input data to the shift register and selector 18 on the right side by the shift clock 100, and the shift register 10-n outputs the input data to the selector 18 by the shift clock 100.

The m-ary counter 12 is a counter for one frame of data input which gives the address of the ROM 14, counts up by the shift clock 100, and clears this count by the frame pulse 110. m
The advance counter 12 outputs the data 120 counted up by the shift lock to the ROM 14 as address data. The ROM 14 reads the data corresponding to the address designated by the address data 120 as the selection data of the selector 18, and outputs this selection data 122 to the decoder 16.

The decoder 16 is a circuit that expands the selection data 122 according to the input terminal of the selector 18, and outputs the selection control signal 124 to the selector 18. Although the decoder 16 is used in this embodiment, if the selection control number of the selector 18 is equal to or smaller than the output bit number of the ROM 14, the decoder 16 is not used and the ROM is not used.
14 may directly control the selector 18.

In the data phase conversion circuit configured as described above, the data input is input to the n-stage shift register 10, and the data input and the output of each shift register 10 are input to the n + 1 input selector 18. The output of the m-ary counter 12 which is cleared by the frame pulse 110 corresponding to the data input and which is counted by the shift clock 100 obtains the selection control signal 124 of the selector 18 by the ROM 14 and the decoder 16.

Next, the selection control method of the selector 18 in this embodiment will be described in detail. As shown in FIG. 2, the selection control method of the selector 18 first calculates the delay amount (A) for each time slot in the time slot replacement pattern for the data input sequence. Then, the maximum advance value, in this case, the negative maximum value "-3" is selected from the numerical values of the delay amount in (A), and the absolute value "3" is obtained in (A) for each delay amount. To obtain the correction value (B) as a control delay value. The ROM 14 is designed to obtain this correction value B for the counter output 120. That is, when the counter output 120 is “0”, the input terminal 3 of the selector 18 is
However, when the counter output 120 is "1", the selector 1
The ROM 14 is designed so that the input terminal 2 of 8 and the input terminal 5 of the selector 18 are selected when the counter output 120 is "3". Further, in this embodiment, the maximum value of the correction value (B) is "9", so that the shift register 1
The number of stages of 0 may be 9 stages. The absolute delay amount of data output with respect to data input is a correction value (3 steps).

Below the dotted line in FIG. 2, the selection of n (0-9) is made in time series by the correction value (B), and the result shows the expected time slot replacement pattern. The process of data shift and the selected data are indicated by circle symbols. That is, when the data input as the time slot 1 is output from the shift register 10-3 by the counter output “0” by the first shift clock 100, the input terminal 3 of the selector 18 is selected by the selection signal 124 and output. To be done. Next, when the data input as the tom slot 3 is output from the shift register 10-2 by the counter output "1" by the second shift clock 100, the input terminal 2 of the selector 18 is selected by the selection signal 124. Is output. Subsequently, when the data input as the time slot 5 is output from the shift register 10-1 by the counter output “2” by the third shift clock 100, the input terminal 1 of the selector 18 is selected by the selection signal 124. Is output. Hereinafter, similarly, the counter value 120 of the m-ary counter 12
Then, the address of the ROM 14 is selected and the input terminal of the selector 18 is selected according to the recorded pattern. In this embodiment, the data delay amount is 3
Since it is a step, the output data is actually 3
It is output with a delay.

Further, in the present embodiment, the case where the pattern having the delay amount of "3" is stored in the ROM 14 has been described as an example, but the present invention is not particularly limited to the delay amount of "3". .. Alternatively, for example, a plurality of patterns may be stored in the ROM 14 and a pattern may be selected from among these depending on the situation. In this case, the shift register 10
The number of steps is the maximum value of the correction value (B) in these patterns.

[0016]

As described above, according to the data phase conversion system of the present invention, a data buffer circuit or an address control memory circuit capable of writing / reading at an arbitrary address which is necessary for a time switch is not used. Since the data phase conversion circuit can be configured, the following effects can be expected.

1. The overall circuit scale can be reduced by combining simple circuits with conventional circuits.

2. The control circuit is simple and the number of wires between circuits is small.

3. Frame pulse (clear counter)
Allows you to easily resync.

4. The number of stages of the shift register can be minimized with respect to the time slot replacement pattern (the maximum value of the correction value B).

5. The absolute delay amount of data output with respect to data input can be minimized.

6. It can be easily integrated into an LSI.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a data phase conversion circuit showing an embodiment of a data phase conversion system according to the present invention,

FIG. 2 is an explanatory diagram showing operation contents in the embodiment of the data phase conversion system according to the present invention;

FIG. 3 is a configuration diagram of a time switch circuit according to the related art;

FIG. 4 is a configuration diagram of a time switch circuit in a conventional technique.

[Explanation of symbols]

 10-1 to 10-n shift register 12 m-ary counter 14 ROM 16 decoder 18 selector

Claims (3)

[Claims] 1. A data phase conversion method for inputting synchronous data, outputting the synchronous data by exchanging time slots of the synchronous data, and calculating a delay amount of each time slot in a time slot interchange pattern for the synchronous data to be input,
The maximum advance value with the smallest delay amount is selected from this delay amount, the absolute value of the maximum advance value is added to the calculated delay amount of each time slot to obtain the control delay value, and the control delay value is The maximum value is the number of stages of the shift register for inputting the synchronous data, and these control delay values are selection control signals for exchanging the phases of the time slots of the synchronous data, and the synchronous data is the synchronous clock as the shift clock. Input to the shift register according to the clock for switching, and the shift stage output of the shift register according to the selection control signal is sequentially selected in synchronization with the shift clock, whereby the time lots are switched. Data phase conversion method. 2. The data phase conversion system according to claim 1, wherein a data phase conversion circuit to which this system is applied has a maximum number of stages of the control delay value, and outputs the input data by the shift clock. A shift register for outputting, counter means corresponding to the number of bits in the frame of the synchronous data, and the control delay value in each time slot are stored,
Control means for outputting a selection control signal in time slot replacement according to the delay value and data output from the shift register are input, and this data is selectively output according to the selection control signal input from the control means. A data phase conversion circuit having a selecting means. 3. The data phase conversion circuit according to claim 2, wherein the control means stores the control delay value.
A data phase conversion circuit comprising: storage means for outputting the control delay value as data; and a decoder for outputting a selection control signal to the selection means according to the output of the storage means.