JPH04145747A - Parallel signal processing circuit - Google Patents

Abstract

PURPOSE:To drive this parallel signal processing circuit without aborting it, to reduce the cost of the circuit and to reduce the number of hard circuits constituting the circuit by using a memory to be independently accessed at the time of writing and reading. CONSTITUTION:A speed converter 105 outputs processed data inputted from a signal processor 104 as an N-bit data sequence processed after returning the bit width of the processed data to the same value of input data A1. Data to be processed next are written in the B area of a 2-port memory 103 in order to execute the succeeding signal processing The processor 104 can execute time slot signal processing by a time slot corresponding to a slot number. Since time slot data have been written in 2-port memories 113, 123, the data are outputted from speed converters 115, 125. A selector successively outputs output data A2 based upon a control signal C102.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a parallel signal processing circuit, and particularly to a data signal processing circuit when the amount of digital signal processing in a digital communication system is large compared to the time of a time slot. The present invention relates to a parallel signal processing circuit that secures signal processing time by installing two in parallel.

[Conventional technology]

Generally, in a data signal processing diagram, after N bits of data in one time slot are stored in a memory circuit, a lock is used to store the data stored in the memory circuit at a higher speed than the input data rate. There is one that performs signal processing while reading and writing, and then outputs after converting to the original data speed. An example of such a data signal processing circuit is an accumulation/broadcast demodulator. This demodulator processes a certain accumulated data series all at once, performs carrier recovery, clock recovery, etc., and demodulates the data. In such a circuit, when the amount of signal processing is larger than the time slot time, it is conceivable to install data signal processing circuits in parallel in order to secure the signal processing time. A conventional parallel signal processing circuit of this type will be explained with reference to the configuration diagram of FIG. 3 and the time chart of FIG. 4. In FIG. 3, input data A1 is divided into N bits of data for one time slot in a distributor 11 by a control signal C1 from a controller 12, and is sequentially divided into N bits of data for each of four signal processing circuits 50 to 53. 1
For example, the data D1 of the time slot with slot number 1 in FIG. 4 is sent to the control signal C
31, the data is written into the first time slot of the memory 103. The signal processor 14A reads Dl written in the memory 13A while outputting the control signal C41 to the memory 13A during the three slots of the 2.3°4 time slot, and performs signal processing. Rewrite the data that is currently being processed inside the device. Further, predetermined signal processing is performed using a high-speed clock supplied from an oscillator built in the signal processor 14A, and the speed converter 15A
Output to. In this case, since the processing within the signal processor 14A is performed using a high-speed clock, the speed converter 15A
The data output to is the bit width of the high speed clock. Therefore, the speed converter 15A restores the bit width to the same data speed as the input data Al, and converts the processed N-bit data sequence D1 at the time of the fifth time slot.
′ is output. On the other hand, since the processing of Dl by the signal processor 14A is completed at the fourth time slot, new input data D5 of the memory 13A is processed after a pause of one time slot.
is read out and signal processing of data D5 is performed in the same manner as described above.Meanwhile, data D of the 2.3.4th time slot
2. D3. D4 are signal processors 14B, 14C, and
14D, the same processing as described above is performed, and the signal-processed data D2', D3', and D4' are sent to the speed converter 15B,
Output from 15C and 15D. Signal processing circuits 50 to 53
D1' to D4' outputted from the selector 5 are selected by the control signal C2 inputted from the controller 12.
It is converted into a series and outputs output data A2. Note that the controller 2 inputs a slot timing and a clock synchronized with the input data A1 from an external circuit, and outputs the input data AI.
is distributed to data signal processing circuits 50 to 53 for each slot. As can be seen from FIG. 4, if the processing time for data in each time slot of the signal processors 14A to 14D requires three time slots, the processed data DI'D2'D3', etc. Continuous output requires four memories, a signal processor, and a speed converter.

Furthermore, for example, when the signal processor 14A processes the next data D5, it pauses for one time slot while the memory 13A writes the data D5.

[Problem to be solved by the invention]

In the conventional parallel signal processing circuit described above, when writing the next data sent from the distributor to the memory, there is one memory corresponding to each signal processor, so the signal processor is The disadvantage is that it must be paused for a period of time. Furthermore, in the case of the processing procedure of such a signal processing circuit, if the data processing time for one time slot is equivalent to three time slots, then
There is a drawback that four systems of signal processing circuits are required, resulting in a redundant circuit configuration.

[Means to solve the problem]

The parallel signal processing circuit of the present invention includes a distributor that sequentially distributes inputted data arranged in consecutive time slots in units of time slots, and N that processes in parallel the data in units of time slots output from the distributor. (N is an integer) signal processing circuits, and a control circuit that controls each of the distributor and the signal processing circuit using a timing signal and a clock of the time slot input from the outside;
and a selection circuit that outputs an output signal of the signal processing circuit in time series according to a control signal of the control circuit, wherein each of the signal processing circuits is arranged in the input time slot. a first memory for storing data in a first time slot of data stored in the first time slot; and a first memory for storing data in a first time slot of the data stored in the first time slot; and a second memory for storing data.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a time chart of this embodiment. Input data A1 is distributed by distributor 1
01, data for one time slot is divided into N bits by the control signal C101 from the controller 102, and the data is sequentially divided into three two-vote memories 103 and 113, respectively.
, 123. For example, in FIG. 2, data D1 of the time slot of slot signal 1 is written to area A of the 2-vote memory 103, data D2. Data D3
is written to area A of the two-vote memories 113 and 123. Here, the two-boat memory 103, 11 in the present invention
3,123 has two or more memory areas, and is a so-called 2-bottom R that can access the memory independently for writing from the distributor side and reading from the signal processor side.
It has an AM configuration. Therefore, new data can be written to the B area even while data is being exchanged between the memory in the A area and the signal processors 104, 114, and 124. This control is based on the slot timing and clock input to the controller 102 using the control signal C131,1.
This is done under the control of 32 and 133. Signal processor 104
In the 2.3.4 time slot, Dl written in area A of the 2-vote memory 103 is read and processed, and the data being processed is written again. Further, the internal high-speed clock performs high-speed signal processing and outputs from the speed converter 105.

That is, the speed converter 105 returns the processed data input from the signal processor 104 to the same time slot bit width as the input data A1, and outputs the processed N-bit data in the time slot at slot number 5. Series D
Output as I'. Since the signal processor 104 processes the data D1 up to the time slots 2 and 3.4 as described above, it is not possible to perform signal processing on the next data from the time slot with slot number 5. For 0th order signal processing, 2-board memory 103
Data D4 to be processed next is written in the B area in the time slot of slot number 4. Signal processor 10
4, signal processing of D4 can be performed in time slots with slot numbers 5 and 6.7. On the other hand, data D2. of the time slot with slot number 2.3. D3 is written in the two-board memories 113 and 123, and the same processing as described above is performed in the signal processors 114 and 124, respectively, and the processing is performed from the speed converters 115 and 125 in the time slots of slot numbers 6 and 7, respectively. The selector 106 outputs the speed-converted data D1', D2', D3' as the control signal Cl.
O2 is used to sequentially output the data as output data A2.

〔Effect of the invention〕

As explained above, the present invention has twice the memory area of the conventional one, and by creating a memory that can be accessed independently for writing and reading, it is possible to eliminate the need to suspend the signal processor. There are effects that can be made to work. Therefore, it is possible to reduce the number of signal processing circuit systems by one, resulting in lower costs and fewer hardware circuits.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a time chart showing the operation of Fig. 1, Fig. 3 is a block diagram of a conventional parallel signal processing circuit, and Fig. 4 is the operation of the conventional example. It is a time chart showing. 11.101...Distributor, 12,102...Controller, 103.113,123...2 port memory, 13
A, B, C, D...Memory, 14A, B, C, D. 104.114,124...Signal processor, 15A. B, C, D, 105, 115, 125...speed converter, 16,106...selector.

Claims (1)

[Claims] 1. A distributor that sequentially distributes input data arranged in consecutive time slots in units of time slots, and N that processes in parallel the data in units of time slots output from the distributor. (N is an integer) signal processing circuits,
a control circuit that controls each of the distributor and the signal processing circuit using a timing signal and a clock of the time slot inputted from the outside; and a control circuit that controls the output signal of the signal processing circuit in time series using the control signal of the control circuit. a selection circuit that outputs a selection circuit, each of the signal processing circuits comprising: a first memory that stores data of a first time slot of data arranged in the input time slots; a second memory that stores data of a second time slot within a time corresponding to N-1 time slots starting from the storage time of the first time slot. processing circuit. 2. The parallel processing according to claim 1, wherein the signal processing circuit writes data to the second memory while reading and processing data stored in the first memory. signal processing circuit.