JPH0542010B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In order to increase the processing speed of a sequential serial memory circuit for data buffering, two 2-port memories that perform writing and reading independently and one register that bypasses data at address 0 are provided. , regardless of whether the data length to be written to the memory is an even number, an odd number, or an odd number, the first data at address 0 is written to the register that bypasses the data at address 0, and the input data after the data at address 1 is written to the two 2 ports. Write to memory alternately.

On the other hand, the data written alternately to the register and the two 2-port memories is read out at a certain stable period after the writing is completed in the order in which they were written. Data is read in the order written independently of the write operation, and whether the data length written to the memory is odd or even, data is written and read at approximately twice the operating speed of the memory inside the circuit. This realizes a sequential memory circuit that performs processing.

[Industrial application field]

The present invention relates to improvements in sequential memory circuits.

The present invention provides a sequential memory circuit that can be used as a data buffer or data recording device for speed conversion in a digital device that uses sequential data.

It is desired that such memory circuits be able to store large amounts of data at high speed.

[Conventional technology]

Traditionally, in order to increase the operating speed of memory,
Two memories are prepared, and writing and reading processes are performed while switching between these two memories alternately.
A circuit to which a so-called memory share method is applied has been proposed, and the memory share method is shown in FIG. 6a.

In the alternating operation memory sharing method shown in FIG. 6a, after the writing of input data to memory address 0 is completed, data is written to memory address 1, and thereafter data is written to memory address 2 in the same manner. , 3 are written to the memory alternately.

In the memory share system that performs such alternating operations, the write cycle is the same as in the case of a single memory, so the operating speed of the memory circuit cannot be improved.

Therefore, in order to improve this operation speed, the sixth
As shown in Figure b, a method has been proposed in which the write timings of the even address memory and the odd address memory are shifted by half a cycle so that they operate alternately, and this method is currently in general use.

With this method, the even-address memory and the odd-address memory operate at timings that are shifted by half a cycle, so that the memory write speed can be doubled.

[Problem that the invention seeks to solve]

However, in the conventional method of shifting the write timing by half a cycle as shown in Fig. 6b, when the number of data to be written is an even number, for example, the data length is 4 pieces from addresses 0 to 3 as shown in Fig. 6b. if there is,
Since the data at addresses 0 and 2 are written to the even address memory, and the data at addresses 1 and 3 are written to the odd address memory, no problem occurs.

However, if the data length is an odd number, 0, 2,
If the data at even address addresses such as 4 is written to the even address memory, and the data at odd address addresses such as 1, 3, 5, etc. are written to the odd address memory, the last Invalid data will occur at the address on the odd-numbered address side next to the 2n address where the data at the address is written.

As a result, it has become necessary to process this invalid data upon reading.

In order to avoid this, measures have been taken, for example, to match data with an even number of data at the stage of inputting the data to the memory circuit, but this has the disadvantage of increasing the circuit scale. Ta.

In addition, as a method to prevent invalid data from being generated, as shown in Figure 6d, the data at address 2n, where the last data is written, and the data at address 0, where the next data is written, are written consecutively for 1/2 of the time. However, since the memory operating speed cannot follow the 2n and 0 addresses, it is physically impossible to write.

SUMMARY OF THE INVENTION The present invention is intended to solve this problem, and aims to provide a sequential memory circuit that can perform writing and reading at high speed regardless of the data length of input data.

[Means for solving problems]

The above problem can be solved by using two memory circuits 4 and 5, as shown in the principle diagram of the present invention in FIG. The circuits 4 and 5 write data alternately, and the read clock supplied by the read address clock generation circuit 9 is used to write data.
Data is read out alternately, and the memory circuits 4,
The data mutually read from the two memory circuits 4 and 5 is transferred by alternately switching the selector 6 which is operated by a selection signal supplied by the read address clock generation circuit 9. In a sequential memory circuit that reads and retrieves data, two two-port memory circuits that can independently execute data writing and data reading are used for the memory circuits 4 and 5.

Further, when data at address 0 of a plurality of input data is written using the write clock from the write address clock generation circuit 8, and when the address generated by the read address clock generation circuit 9 is "0",
A register 3 is provided which performs reading based on a selection signal from the selector 6.

Then, the data at address 0 of the input data is detoured to the register 3, and the data after address 1 of the input data is written alternately in the two memory circuits 4 and 5. This can be solved by independently reading the data written in the register 3 and alternately reading the data written in the memory circuits 4 and 5.

[Effect]

According to the present invention, the register 3 is clocked by a write clock generated in an external write control circuit and a one-pulse register write clock from a write address clock generation circuit 8 which receives a write address signal. , writes the 0 address data which is the first data of the plural data to be input. When data writing to the register 3 is completed, the second data, address 1 data, is written to one of the memory circuits 5 using the write address and write clock from the write address clock generation circuit 8, and is delayed by half a cycle. Then, the third data, address 2 data, is written into the other memory circuit 4. Thereafter, data is sequentially and alternately written into the memory circuits 5 and 4.

When the writing of the first plurality of data is completed and the next plurality of data is input, the register write clock is reset by a write reset signal obtained from the outside to the write address clock generation circuit 8. At the same time as the data is supplied to the register 3, the write clocks to the memory circuits 4 and 5 are stopped, so in the same way as in the case of the first plurality of data, the data is written to the register 3.
Write address 0 data to.

Thereafter, the writing of data after the first address data to the memory circuits 5 and 4 is performed in the same manner as the first data.

Further, in order to read the data written in the register 3 and memory circuits 5 and 4, first, a read address clock generation circuit 9 receives a read address signal, a read clock, and a selector control signal generated in an external read control circuit. The selector 6 is switched by a selection signal from the register 3, and the 0 address data written in the register 3 is read out and taken out via the selector 6.

Next, the read address and read clock are supplied from the read address clock generation circuit 9 to the memory circuit 5, so the data at address 1 written in the memory circuit 5 is read out, and the read address clock generation circuit 9
The memory circuit 5 is selected by a selection signal supplied to the selector 6 from the selector 6, and the read address 1 data is taken out via the selector 6.

Similarly, read address clock generation circuit 9
The second address data written in the memory circuit 4 is read using the read address and the read clock from the memory circuit 4, and the memory circuit 4 is selected using the selection signal from the same generation circuit 9, and the read second address data is taken out via the selector 6. .

Similarly, the data written in the memory circuits 5 and 4 is read out and taken out via the selector 6.

Since two-port memories are used in the memory circuits 4 and 5, data writing and data reading can be performed independently.

By doing so, data can be written and read in the same way regardless of whether the data length of the data input to the memory circuit is an even number or an odd number.

〔Example〕

FIG. 2 is a block diagram of a sequential memory according to an embodiment of the present invention. Regarding the operation of the circuit diagram in Figure 2, Figure 3 shows the write time chart for odd number data, Figure 4 shows the write time chart for even number data, and Figure 5 shows the read time chart for odd number data. shows.

First, a write time chart for odd number data will be explained using FIGS. 2 and 3.

Here, input data 1 is Am~Gm (m=0~
n) is made up of seven odd-numbered pieces of data.

First, the first input data 1 consisting of A0 to G0
, A0 goes to 0 address register 30, B0, D0,
F0 is written to the B memory 53, and C0, E0, G0 are written to the A memory 43. Then, in the same way, A1 of the next input data 1 consisting of A1 to G1 is written to the 0 address register 30, B1, D1, and F1 are written to the B memory 53, and C1, E1, and G1 are written to the A memory 43. The same applies hereafter.

The write address clock generation circuit 8 for writing data to the register 30 and memories 43 and 53 includes (a) write clock WCK obtained from the outside;
(b) Write reset signal WR and (f) Register write clock WCK0 to 0 address register 30.
and (d) A memory write clock to the data register 41 and address register 42 of the A memory 43.
WCKA and data register 51 of B memory 53
and (e)B memory write clock WCKB to address register 52, and both address registers 42, 52.
(c) Write clock WA is generated.

Then, each data Am, Bm,
Cm, ...Gm are address numbers for specifying the location to write to the memory circuit, respectively.
0, 1, 2,...6 are given.

The timing of writing input data 1 is as follows:
To the write address clock generation circuit 8 from the outside,
Last address number Gm of previous input data 1
Corresponding to (b) write reset signal WR given at the same timing as data, (f) 0 address register write clock WCKO of 1 pulse generated in synchronization with (a) write clock, 0 address register 3
0, input data Am of address number 0 of input data 1 is written.

On the other hand, this (f)0 address register write clock
This (f) 0 address register write clock is set so that the (d) (e) write clocks WCKA and WCKB are not supplied to the A memory and B memory at the clock time when WCKO is supplied to the 0 address register 30.
At the clock timing when WCKO is supplied to the 0 address register 30, memory A, memory B
The supply timings of (d) and (e) write clocks WCKA and WCKB to the memory are each shifted later by one clock.

Next, the input data Bm of address number 1 is (e)B
The data is written to the B memory 53 via the data register 51 by the memory write clock WCKB.

Then, input data Cm for the next address number 2
(d) is written to the A memory 43 via the data register 41 by the A memory write clock WCKA.

Similarly, address numbers 3 and 5 are stored in the B memory 53, and address numbers 4 and 6 are stored in the A memory 43 alternately in the data registers 51 and 41, respectively.
written via.

As a result, the timing at which data is written to the 0 address register 30 is as shown in (k). Data is held until a signal is input.

Furthermore, the timing at which data is written to the B memory 53 via the data register B51 is as shown in (j), in the case of the next input data B1, the input data B1
From the time of the next write clock inputted to this memory circuit, the input data B1 temporarily stored in the data register B51 is written into the B memory 53 in two clocks. In this way, it is sufficient to write to the memory circuits 53, 43 in twice the period of the write clock supplied from the outside. That is,
This means that the operating speed of the memory circuits 53 and 43 can be reduced to 1/2.

In this way, input data Am to Gm are written at the timing indicated by address 0 number Am in the (k)0 address register 30, and Bm, Dm, Fm
(j) B memory 5 at the timing of data register B
3, and Cm, Em, and Gm are each written to the A memory 43 at the timing of (i) data register A.

Next, the case where there is an even number of input data will be explained using FIG. 4.

Assume that the input data 1 consists of six even-numbered data Am to Fm (m=0 to n).

First, the input data 1 consisting of the first data A0 to F0 is sent to the address register 30 where A0 is 0.
B0, D0, F0 go to B memory 53, and C0, E0
is written to the A memory 43. Then, in the same way, the following input data 1 consisting of A1 to F1
However, A1 goes to 0 address register 30, B1, D
1 and F1 are written to the B memory 53, and C1 and E1 are written to the A memory 43. The same applies below.

The input data is Am~Fm (m=
0 to n), at the same timing as the input of the last data F0 of the previous input data, (b)
A write reset signal WR is sent to the write address clock generation circuit 8.

Then, since there is no longer any data corresponding to the input data "GO" in the case of FIG. 3, the first address data A1 of the next data is sent immediately after the input data "FO". Also, at the same timing, (f)0 address register write clock
WCKO is provided to the 0 address register 30.
Correspondingly, data A1 of the (k)0 address register is written.

In FIG. 3, (c) address data “6” of write address WA and (d) A write clock WCLA.
(c) Since the write clock at the timing of address data “6” of write address WA is also eliminated,
(g) Address data “4” of A address register
continues until the next address data "2" is input.

Furthermore, data "E0" of the (i) A data register written by address data "4" continues until data "C1" written by the next address data "2" is input.

Further, the address data "5" of the (h)B address register also continues until the next address data "1" is input.

As a result, the (l) write data written into the memory circuits 5 and 4 is written in the same order as the input data.

In this way, even if there is an even number of input data, it is possible to write without data loss.

Next, the read time chart of FIG. 5 corresponding to the case where there are seven pieces of data shown in FIG. 3 will be explained.

0 address register 30, A memory 43, B
In order to read the data written in the memory 53, a read address clock generation circuit 9 and a selector 6 are provided.

The read address clock generation circuit 9 uses (m) read clock RCK and (n) read reset signal RR obtained from the outside to input ((m) to address register 44 of memory A 43 in synchronization with (m) read clock RCK). p)
A memory read clock RCKA and B memory 53
(q)B memory read clock to address register 54 of
RCKB and both address registers 44 and 54.
It generates (o) a read address RA and (y) a selection signal for the selector 6 to take out the data read from the 0 address register 30, the A memory 43, and the B memory 53.

Further, in response to the (y) selection signal supplied from the read address clock generation circuit 9, the selector 6
The 0 address register 30, the B memory 53, and the A memory 43 are sequentially switched and the data read from each is taken out.

The relationship between the read timing of data written in the memory circuit and the write timing in FIG. 3 depends on the storage capacity of the 2-port memory circuit and the device configuration, but for example,
Assuming one frame of data, the read reset signal is input with a delay of several to several tens of data from the write reset signal, so that the data is read out at a timing that allows stable data reading.

Further, in response to the (n) read reset signal RR applied externally to the read address clock generation circuit 9, (o) read address RAP is generated at the timing of the next read clock, but the select 6 is (o). ) According to the read address RA, B memory, A memory 54,
In consideration of the delay in the data output from 44, the (y) selection signal is supplied with a delay of two clocks.

First, by (n) read reset signal RR, at the timing of the next clock, (o) read address RA is set to "0" to read data at address 0.
occurs, but the 0 address register 30 contains 0.
Since only data "A1" corresponding to address data is written, (o) read address RA is not supplied, but after two clocks, 0 address register 3
Since the (y) selection signal for selecting 0 is supplied to the selector 6, data “A1” is read out and the selector 6
is retrieved via.

Next, (o) "1" for reading address 1 data is supplied to the read address RA, and (s) the B address register RCKB is supplied to the address register 54. Then, the data "1" is stored in the address register 54, and the data "Bm" stored at the address "1" in the B memory 53 is read out and sent to the selector 6. And selector 6
When a (y) selection signal is sent to select the B memory 53, data "Bm" is taken out via the selector 6. Similarly, data "C1" written in address "2" of A memory 43 is taken out via selector 6.

Similarly, data Am written in the 0 address register 30, data Bm, Dm, Fm written in the B memory 53, and data Cm, Em, Gm written in the A memory 43 are stored in the B memory. 53.A
After each data is read from the memory 43, the data is sequentially taken out by the selector 6 as (x) selector output data.

Also, reading data for an even number of data is basically the same as for an odd number of data, so
I will omit the explanation.

In this way, (a) write clock in Figure 3
WCK, the external clock cycle shown in (m) read clock RCK in Figure 5, and (d) (e) write clock.
WCKA, WCKB, (p), (q) read clock
The internal clock cycle indicated by RCKA/RCKB is twice the operating time of , but since the two memories, A memory and B memory, are written and read independently, it is difficult to compare it with the register operating time. Even if a memory with a processing speed of 1/2 is used, as a memory circuit, if the operation around the 0 number is excluded, the processing speed is as fast as the register operation time.
Write and read processing can be performed.

In addition, in FIGS. 3 to 5, for convenience of explanation, A
For example, if the used address of memory, B memory is
In the case of memory, the address is 2, 4, 6, but in reality, each memory address is one of the address data generated by counting the external write clock WCK or write reset signal WR. By not using the least significant bit (LSB) of the memory, etc., the addresses given to memory A and memory B are made continuous, so that the memory usage area does not become discontinuous.

〔Effect of the invention〕

As described above, according to the present invention, by using the 0 address register, it is possible to write and read data in the same way whether the data length is odd or even. It can greatly contribute to readout.

By using multiple 2-port memories that can perform writing and reading independently even if the operation is slower than that of registers, writing and reading can be performed independently, and the times used can be staggered. Since they operate in parallel, it is possible to realize a high-speed memory circuit.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of the present invention, and FIG. 2 is a block circuit diagram of a sequential memory according to an embodiment of the present invention.
FIG. 3 is a write time chart (odd data) of a sequential memory circuit according to an embodiment of the present invention;
The figure is a write time chart (even data) of a sequential memory circuit according to an embodiment of the present invention, FIG. 5 is a read time chart (odd data) of a sequential memory circuit according to an embodiment of the present invention, and FIG. 6a is a conventional diagram. Figure 6b shows the conventional memory sharing method of alternating operation with half-cycle shift (even number data), Figure 6c shows the conventional memory sharing method of alternating operation with half-cycle shift (odd number data), and Figure 6d is the conventional memory sharing method of alternating half-cycle shifting (odd data). In the figure, 1 is input data, 2 is output data, 3 is a register, 4 and 5 are memory circuits, 6 is a selector, 7 is an output register, 8 is a write address clock generation circuit, and 9 is a read address clock generation circuit. In the circuit, 30 is a 0 address register, 41, 51 are data registers, 42, 52, 44, 54 are address registers, 43 is an A memory, and 53 is a B memory.

Claims (1)

[Scope of Claims] 1. Using two memory circuits 4 and 5, data is written alternately in the two memory circuits 4 and 5 by a write clock supplied by a write address clock generation circuit 8, Data is read out alternately by the read clock supplied by the read address clock generation circuit 9, and the data mutually read from the memory circuits 4 and 5 is controlled by the selection signal supplied by the read address clock generation circuit 9. In a sequential memory circuit that reads and retrieves the data written in the two memory circuits 4 and 5 by mutually switching the selectors 6 operated by the Using two two-port memory circuits that can read data independently, data at address 0 of a plurality of pieces of input data is written using the write clock from the write address clock generation circuit 8, and the data at address 0 is written using the write clock from the write address clock generation circuit 8. When the generation address of the generation circuit 9 is "0", a register 3 is provided which performs reading according to a selection signal from the selector 6, and the data at address 0 of the input data is stored in the register 3.
The data after address 1 of the input data is detoured to the two memory circuits 4 and 5.
A sequential memory circuit characterized in that writing is performed alternately, and the data written in the register 3 and the memory circuits 4 and 5 are read out independently of the writing.