JPS6122512B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an image encoding device for interframe encoding that highly compresses television signals.
This invention relates to a buffer memory for smoothing data that occurs irregularly and intermittently and transmitting the smoothed data to a transmission line at a constant speed.

Television signals transmit images at 30 seconds (called frames) every second, but if there is little movement on the screen, the difference in signals between successive frames becomes very small. Therefore, by transmitting only the difference signal between frames, that is, information about the moving portion of the screen, the amount of transmitted data can be significantly reduced. Coding based on this concept is called "interframe coding," and the basic configuration of its encoder/decoder is shown in FIG. That is, the input television signal is sent to an analog-to-digital converter (A/D converter) 1.
is converted into a digital signal (PCM signal) by The PCM-encoded television signal and the previous frame signal stored in the frame memory 2 are compared, and only for pixels having a difference of a certain value or more, the amplitude, position on the screen, etc. are encoded by the encoder 3. become The amount of output codes generated by the encoder 3 changes depending on the movement of the screen, so after being temporarily stored in the buffer memory 5, the output code is generated at an approximately constant rate (taking into account stuffing, frame markers, etc., it is not completely constant). Sent to the transmission path. The output of the encoder 3 is decoded by a decoder 4 and stored again in the frame memory 2.

On the other hand, the code sent from the transmission path is temporarily stored in the buffer memory 6, and then decoded by the decoder 7 into the original difference signal according to the TV synchronization signal, and the image signal in the frame memory 8 is rewritten, and the PCM The television signal is reproduced, and a digital-to-analog converter (D/A converter) 9 obtains the original analog television signal.

In the above-mentioned interframe encoding device, a buffer memory is essential for smoothing irregularly/intermittently generated encoded data and sending it to a transmission path. Normally, the buffer memory used for this purpose has a storage capacity of about one screen (0.4 to 1.5 x ¹⁰⁶ bits) and an input of 6 to 13 x ¹⁰⁶ words (a word represents n-bit parallel data). Output speed is required. That is, the input to the transmitter buffer memory is at its maximum equal to the rate of the sampling frequency;
The output code of the encoder 3 (generally an n-bit parallel signal) has a code generation amount equal to the speed of the transmission line on average, and the buffer memory output is:
It is connected to the transmission line as an output signal having a substantially constant period. On the other hand, the buffer memory on the receiving side has input and output interchanged with that on the transmitting side. Further, the above-mentioned generated data and the clock of the transmission line are generally asynchronous.

As described above, buffer memory is a large-capacity memory, and therefore MOS random access memory, which can be highly integrated, is often used as a storage element. This MOS type random memory has a write or read cycle time of up to several hundred nanoseconds, which is a much slower operating speed than the data rate it generates. This speed mismatch between the operating speed of the memory device and the data rate is achieved by serial-to-parallel converting the data and writing or reading parallel data to or from the memory device at the same time, thereby effectively reducing the data rate to 1. I was able to solve this by changing the number of parallel bits to /(number of parallel bits). At this time, as the number of parallel expansions for serial-to-parallel conversion of data increases, the number of logic elements required for this increases, so it is desirable that the number of parallel expansions be as small as possible. To this end, it is necessary to maximize the operating speed of the memory device. In other words, since the amount of generated data that is input to the buffer memory should be equal to the bit rate of the transmission line on average, if the memory element can be operated at at most twice the bit rate of the transmission line, the number of expansions will be as long as possible. Although it requires less memory and is the most effective in terms of memory operation speed, it inevitably becomes extremely complex in terms of circuitry. That is,
The output of the buffer memory 5 on the transmission side of the interframe encoding device shown in FIG. , is input intermittently. Therefore, in order to operate a memory element at a speed that is at most twice the transmission line bit rate, if half of each memory operation cycle is a write cycle and a read cycle, and this is performed periodically, the The rule input data must already be smoothed and converted to constant velocity. For this purpose, a waiting circuit is required to store input data that is input irregularly until the time when it can be written. The number of registers in this waiting circuit must be determined in such a way that there is sufficient margin even in the worst case, where several samples of encoded data at the highest speed are input in succession, so the number of registers becomes large. Ta. Moreover, considering the buffer memory configuration as described above, the buffer memory configurations on the transmitting side and receiving side in Figure 1 require waiting circuits on the input and output sides, respectively. Either they were switched on the side, or a waiting circuit was provided for both the input and output, making the circuit redundant and using the same buffer memory.

For example, if the maximum data rate of input data is 8 megabits/second, one word is 8 bits, and the output signal is 6.3 megabits/second, the input data is converted into 8-bit parallel signals on the transmitting side, and each signal is further processed into 8-bit parallel signals. The phase parallel signals were used, and a 4-bit shift register had to be used as a waiting circuit for each phase. Therefore, the total number of bits in the waiting circuit is 4×8×8=256 bits. After each shift register, an input register, a storage circuit, an output register, and a parallel-to-serial conversion circuit were connected in cascade. Similarly, on the receiving side, a waiting circuit consisting of a 4×8×8=256-bit shift register was required on the output side of the buffer memory.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a buffer memory which has a simple circuit configuration and in which both input and output data can be irregular and intermittent.

Next, details of the present invention will be explained with reference to the drawings. 2A to 2E are diagrams for explaining the basic configuration of the buffer memory according to the present invention, FIG. 2A shows the basic configuration of the buffer memory, and FIGS. e is a time chart for explaining the operation of the memory control circuit d.

As shown in FIG. 2a, the basic configuration of the buffer memory consists of an input terminal 101 _i and an output terminal 102 _i
n connected to (i=1, 2,...n) respectively
Bit-parallel input data DI _i and output data
A storage module 100 _i provided corresponding to DO _i ,
The input terminal 10 is synchronized with each input/output data.
An input control circuit 200 and an output control circuit 30 which take input clock IREQ and output clock OREQ applied to 3 and 104, and perform control to match the data input/output speed to the memory operation speed.
0 and the input terminal 105 according to the write/read request signal output from the control circuits 200 and 300.
The memory module 10 is synchronized with the main clock FC of
0 _i and a memory control circuit 400 that performs write/read control.

FIG. 2b shows the detailed structure of the storage module _100i . That is, the serial-parallel conversion circuit 1
10 inputs the input data DI one bit at a time to the terminal 111
Shifts in synchronization with the input clock IREQ. The input register 120 converts the serial-to-parallel converter 110 according to the input buffer clock PI input from the terminal 121 every time this shift is performed by P bits.
The contents of P bits are stored simultaneously, and the write data WD _j
It is output to the storage circuit 130 as (j=1, 2...P). Therefore, the write data WD _j changes at a rate of 1/P of the input data rate. Note that the input clock IREQ and input buffer clock PI are provided from the input control circuit 200.

As shown in FIG. 2c, the memory circuit 130 has P.times.Q memory elements arranged in P rows and Q columns for parallel writing/reading of P bits. Here, Q is an integer selected so as to satisfy the storage capacity required for each bit of the n-bit parallel input data DI using P.times.Q storage elements.

On the other hand, the address signal ADD representing the write/read address of the memory element and the control signal R/W for writing to the memory element are inputted through terminals 131 and 132, respectively, and are connected to all the memory elements. . j
The write data WD _j of the row is all the memory elements of the j-th row
It is simultaneously input to Mj1, Mj2..., MjQ, and at this time, which column of memory element is operated is determined by the terminal 13.
3 _k (k=1, 2...Q) is determined by the column selection signal CS _k input. That is, only one input is made at a certain time. The column to be operated is determined by the column selection signal CS _k . For example, when the column selection signal CS _k corresponding to the k-th column becomes "1", the memory elements M _1k M _2k . . .
...M _pk performs a write or read operation at the same time. All data read from these storage elements are output to one line and output as read data RD _j .

Returning again to FIG. 2b, the write data WD _j is an address signal given from the memory control circuit 400.
ADD, column selection signal CS, and write control signal R/
W is written to a predetermined location in the storage circuit 130. On the other hand, P-bit parallel read data read from a predetermined position by the same control signal (the period when the write control signal R/W is "0" is a read operation)
RD _j is a load signal input from the memory control circuit 400 to the terminal 141 when data is read.
It is temporarily stored in the output register 140 by DL. The data in the output register 140 is transferred to the parallel-serial conversion circuit 150 by the parallel load signal PO applied from the output control circuit 300 to the terminal 153, and then transferred to the output clock OREQ of the terminal 152 also applied from the output control circuit 300. Output data DO is output to terminal 102 while being shifted one bit at a time in synchronization with . Furthermore, the parallel load signal PO input to the terminal 153 causes the output register 14
At the same time that the 0 data is transferred to the parallel-to-serial conversion circuit 150, the output control circuit 300 and the memory control circuit 400 are controlled to read the next data from the storage circuit 130.

Next, the structure and operation of the memory control signal 400 will be explained with reference to FIGS. 2d and 2e. The memory control circuit 400 controls the input control circuit 20 when write data WD _j to the memory circuit 130 is ready.
When there is a write request signal input from 0 to the terminal 401 or a read request signal input from the output control signal 300 to the terminal 402 when data reading is required, the memory circuit 130 synchronizes with the memory operation cycle. It controls the write/read operations of.

First, based on the main clock FC shown at 1 in FIG. 2e inputted to the terminal 105, the timing circuit 410
Then, various timing signals as shown in 2 to 8 in e of the same figure are generated. This figure shows an example in which the memory operating frequency m is 1/m (m is an integer) of the main clock frequency c, and m=8. That is,
The timing pulse _T1 shown in 2 has a frequency of 1/8 of the main clock frequency c, has equal intervals of "1" and "0", and is a pulse that regulates the write mode interval and read mode interval correspondingly. be. 3 and 4
The timing pulses T ₂ and T ₃ shown in are write mode,
This pulse is synchronized with the start of the read mode and is used to synchronize the asynchronously input write request signal and read request signal with the memory operation cycle. 5 and 6 timing pulses T ₄ and T ₅
are pulses that determine the output timing of the column selection signal CS and write control signal R/W in the write mode, and timing pulses _T6 and _T7 of 7 and 8 are the pulses that determine the output timing of the column selection signal CS and the write control signal R/W in the read mode. This is a pulse that determines the output timing of the load signal DL for writing DL into the output register 140.

First, the operation when a write request signal is input to the terminal 401 will be described. If the write request signal is "0" here, there is no write request.
If it is "1", it indicates that there is a write request. The write command register 421 reads the contents of the terminal 401 every time the timing pulse _T2 is input, and is reset by the timing pulse _T3 . Therefore, the write command register 421 has the second
As shown at 9 in FIG. e, an output such that the write mode section becomes "1" is obtained only when the write request signal is "1". The output of the write command register 421 is connected to a write column counter 122, a write column signal timing gate circuit 424, and a write control gate circuit 442. The write column counter 422 is a counter that can count from 1 to Q, and counts 1 every time an input is added.
Count each time. When the count exceeds Q, the upper write address counter 423 counts by one. This 2
The order in which the two counters 422 and 423 are connected is such that each memory element of the memory circuit 130 operates column by column sequentially from the first column, second column... The counter 422 is at the lower level, and the write address counter 423 is at the upper level. However, if this selection of memory elements is such that the operation moves to the second column after all address operations in the first column are completed, the connection order of the two counters 422 and 423 is reversed. Therefore, the contents of the parallel digital outputs of the two counters 422 and 423 shown in FIG. 2d change. The time point is at the timing shown at 10 in FIG. 2e (although the periods are different from each other). The output signal of write address counter 423 is output to terminal 131 via address switching circuit 440. The address switching circuit 440 switches and outputs address signals corresponding to write mode and read mode depending on whether the input timing pulse _T1 is "1" or "0". Therefore, terminal 13
1, a write address and a read address to be described later are alternately output at the timing shown in B of FIG. 2e, and an address signal ADD is obtained.

The output signal of the write column counter 422 is a write signal only when the write command register 421 is "1" and only while the timing pulse T4 passing through the write column signal timing gate circuit ₄₂₄ is input. The signal passes through the column signal gate circuit 425 and is applied to the column selection signal OR circuit 441. As mentioned above, the column selection signal OR circuit 441 simply ORs the write column selection signal synchronized with the timing pulse T ₄ and the read column selection signal synchronized with the timing pulse T ₆ to be described later, and outputs it to the terminal 133. It is something to do.
Therefore, a column selection signal CS corresponding to the write mode is obtained at the terminal 133, as shown at 14 in FIG. 2e. On the other hand, the write control gate circuit 442 is a circuit for outputting the write control signal R/W to the terminal 132, and the timing is only when the write command register 421 is "1" as shown at 15 in FIG. pulse
It passes through _T5 and is used as the write control signal R/W.

On the other hand, the operation in read mode is similar to that in write mode. That is, terminal 402
The read request signal input to the read command register 431 is read into the read command register 431 by the timing pulse _T3 . Furthermore, the contents of the read command register 431 are reset at timing _T2 , and the contents of the read command register 431 are reset as shown in FIG.
“1” only in the read mode section as shown in 11 of
A signal is obtained. readout column counter 432,
The read address counter 433 operates exactly the same as in the write mode, and when the read command register 431 becomes "1",
One is counted at the timing shown in . The output signal of the read address counter 433 is outputted to the terminal 131 via the address switching circuit 440. Further, the output signal of the read column counter 432 is applied to the read column signal data circuit only when the read command register 431 is "1" and only while the timing pulse _T6 passing through the read column signal timing gate circuit 434 is input. 435 and is output to the terminal 133 via the column selection signal OR circuit 441.
The read control data circuit 443 is a data circuit for generating a load signal DL for temporarily storing data read from the storage circuit 130 in the output register 140 according to the control signal, and the read command register 431 The timing pulse _T7 is passed only when is "1".

On the other hand, since the write request signal and the read request signal are not necessarily synchronized with the memory operation cycle given by the timing pulse _T1 , if they are registered in the write command register 421 and the read command register 431, respectively, It is necessary to release these request signals and prepare for outputting the next request signal. Therefore, the output signals of the write command register 421 and the read command register 431 are sent to the terminal 403 in order to reset their respective request signals.
and is returned to the input control circuit 200 and the output control circuit 30 via 404.

Next, an embodiment of the buffer memory according to the present invention will be specifically described. FIG. 3a shows the configuration of the first embodiment, and FIG. 3b shows its operation time chart. This first embodiment is a storage module 100.
The feature is that the number P of parallel expansion of _j is selected such that 1/P of the maximum input/output data speed is 1/1.5 or less of the memory operation speed, that is, P≧1.5×m. By selecting the number of parallel expansions P as described above, one write mode and one read mode section are always included in the data writing and reading period to the memory circuit 130, as will be described later. It becomes possible to handle input/output data such as

That is, when the maximum input/output data rate is equal to the main clock frequency c and the memory operating speed m is c/8 (m=8), the number of parallel expansions P is 12 or more. Input data DI _i as shown in 3 in b of the same figure
(The breaks in the diagram represent the breaks for each P bit.)
An input clock IREQ synchronized with each bit of is input to the input control circuit 200 via a terminal 103. The input clock IREQ is connected to the storage module _100i for serial-to-parallel conversion of the input data _DIi .
At the same time, the clock signal is output to the terminal 111 of the input clock frequency divider circuit 210, and the frequency is divided by P to obtain the input register clock PI as shown at 4 in FIG. Input buffer lock PI is memory module 10
At 0 _i , in order to transfer the contents of the serial-parallel conversion register 110 to the input register 120, the write request register 220 is set to "1" at the same time as it is output to the terminal 121. The output signal of the write request register 220, that is, the write request signal shown at 5 in FIG.
is input. As described above, the memory control circuit 400 generates a predetermined control signal and inputs the input register 1.
The contents of 20 are written to the storage circuit 130. In addition, the write command signal is passed through the terminal 403 to the input control circuit 2.
00 is fed back to the write request reset circuit 230. The write request reset circuit 230 detects the time when the contents of the input register 120 are written into the storage circuit 130, for example, the fall of the write command signal, and resets the write request register 220. Note that even if the write request register 220 is reset using the write control signal R/W instead of this write command signal, there is essentially no change.

According to the above-mentioned write operation, the write operation of the memory control circuit 400 starts within one memory cycle after the write request signal is issued, and ends within half a cycle, so that the write operation is completed within 1.5 times the memory operation cycle. can completely complete the write operation. Therefore, since the write data changes at a cycle that is 1.5 times or more the memory operation cycle as described above, it is possible to completely write even irregular data input at a frequency less than the main clock frequency c.

On the other hand, the output clock OREQ is input to the output control circuit 300 via the terminal 104. This output clock OREQ is input to the parallel-to-serial converter circuit 150 of the storage module 100 _J through a terminal 151, and output data DO _i as shown in 7 in FIG. (The divisions in the figure represent divisions for each P bit).
Further, the output clock OREQ is input to the output clock frequency divider circuit 310, divided by P, and is sent as a parallel load signal PO shown at 8 in FIG.
The data is input to the parallel-to-serial conversion circuit 150, and new P-bit output data is read from the output register 140 every time the parallel-to-serial conversion circuit 150 completes outputting P bits. Further, the parallel load signal sets the read request register 320 to "1". The output signal of the read request register 320, i.e., b
A read request signal shown in 9 is input to the memory control circuit 400 via a terminal 402. As described above, the memory control circuit 400 generates various control signals necessary for the read operation and reads predetermined data from the memory circuit 130. Also, the memory control circuit 400
outputs the load signal DL shown in parentheses (b) in the figure at the time when the data is completely read. The load signal DL is input to the output register 140 and stores the data read from the storage circuit 130. Therefore, the contents of the output register 140 are 12 in b of the same figure.
Changes at the timing shown in . Further, the load signal DL is input to a read request reset circuit 330. The read request reset circuit 330 detects the time when data is stored in the output register 140, for example, the fall of the load signal DL, and resets the read request register 320. Note that even if the input to the read request reset circuit 330 is a read command signal, there is no operational change.

In the read operation that is completed in this way, the read command signal is output within one memory operation period after the read request signal is output at a certain time (for example, t ₁ shown in 9 in b of the same figure), and Since the read operation is started at t ₂ ) at 10 of b and is completed in half the memory operation period (from t ₂ ), all read operations are completed within a total of 1.5 memory operation periods, so the parallel Load signal PO
The read operation will be completed within 1.5 memory operation cycles after the output of the parallel load signal PO.

FIG. 4a shows a block diagram of the second embodiment, and FIG. 4b shows an operation time chart.

In this second embodiment, the number P of parallel expansion of the storage module _100i in FIG. ,
A feature is that a second input register 160 and an output register 170 are provided after the first output register (referred to as a first output register), respectively. Terminal 101 _i to 4th
n-bit parallel input data as shown in 3 in Figure b
DI _i (the delimiters in the figure represent delimiters of every P bits) is input, and an input clock IREQ bit-synchronized with this input data DI _i is input to the input control circuit 200' via the terminal 103. Input clock IREQ is input from terminal 111 of storage module _100i to serial-to-parallel conversion circuit 110, and shifts input data _DIi one bit at a time. On the other hand, the input clock IREQ is also input to the input clock frequency divider circuit 210 and is frequency-divided by P. This frequency-divided first input register clock PI shown at 4 in Figure 4b
is the first input register 120 via the terminal 121
The P-bit parallel data of the serial-to-parallel conversion circuit 110 is read into the first input register. 1st
The contents of the input register change as shown at 5 in b of the same figure. The first input register clock PI is input to the second write request register 240 and sets it to "1". The output of the second write request register 240, ie, the second write request signal shown at 6 in FIG. 4B, is input to the second input register clock generation circuit 50. The second input register clock generation circuit 250 also receives the output of the first write request register 220 (described later), that is, a first write request signal, and this first write request signal is "0". , and when the second write request signal is "1", the second input register clock PI ₂ is output to the second input register 160. The second input register 160 stores the contents of the first input register 120 when the second input register clock PI ₂ is input.
Furthermore, the second input register clock generation circuit 25
In addition to the above-mentioned second input register clock PI ₂ , 0 outputs a second output signal obtained by delaying this signal for a very short time, and at the same time resets the second write request register 240, the first write request register 240 is reset. request register 22
Set 0 to "1". The output of the first write request register 220 is sent to the terminal 40 of the memory control circuit 400.
Connected to 1. The memory control circuit 400 starts a predetermined write operation (described above) based on the write request signal applied to this terminal 401. On the other hand, the write command signal fed back from the memory control circuit 400 is input to the write request reset circuit 230. The write request reset circuit 230 detects the point in time when the data in the second input register 160 is completely written into the storage circuit 130, for example, the point in time when the write command signal falls, and resets the first write request register 220. . The second input register clock PI ₂ obtained in this way, the first write request signal, the write command signal,
The outputs of the second input register are shown at 7-10 in FIG. 4b.

In the write operation completed by the above operation, when the second write request signal is generated at a certain time (for example, t ₁ shown in 6 in FIG. 4B), the second write request signal immediately before the second write request signal is generated. Since the write operation by this request signal is completed within 1.5Tm from the time when the signal is generated (t ₂ ), the write operation from the first input register 120 to the second input register is completed within 0.5Tm from the time (t ₁ ). Data transfer to input register 160 is reliably performed. Therefore, no matter how late the data is transferred from the first input register 120 to the second input register 160, it is ensured that the data is transferred before the contents of the first input register change and before the start of the write command signal. , memory circuit 1 for any irregular input data.
30 will be executed in order.

Next, the read operation of this embodiment will be explained. When the output clock OREQ is input to the output control circuit 300' through the terminal 104, this output clock OREQ is input to the parallel-to-serial converter circuit 150 of the storage module _100i through the terminal 151, and the register contents are shifted one bit at a time. and obtain the output data DO _i . Figure 4b shows the output data
It shows the timing of DO _i . However, the divisions in the figure represent the divisions at which all P-bit parallel data are output from the parallel-to-serial conversion circuit 150.

Further, the output clock OREQ is simultaneously input to the output clock frequency divider circuit 310 and is frequency-divided by P.
Parallel load signal PO as shown at 12 in Figure 4b
The signal is input to the parallel-to-serial conversion circuit 150 through the terminal 152, and the contents of the second output register 170 are read into the parallel-to-serial conversion circuit 150. This parallel load signal PO also sets the second read request register 340. At this time, the second read request register 340 is transferred to the second output register 1 by the above-described operation, as shown at 13 in FIG.
70 is empty and new data is required. This second read request register 3
40, that is, the second read request signal is the second read request signal.
The signal is input to the load signal generation circuit 350. The first read request signal is simultaneously input to the second load signal generation circuit 350. The second load signal generation circuit 350 outputs a signal when the second read request signal is "1", that is, the second output register 170 is empty, and the first read request signal is "0", that is, the first
When it is detected that there is data in the output register 140 of , it generates a second load signal DL2 shown at 14 in FIG. 4b. This second load signal DL2 is applied to the second output register 170, causing the contents of the first output register 140 to be stored. 2nd above
The load signal generation circuit 350 also outputs the second load signal DL2 delayed for a very short time, resets the second read request register 340, and resets the first read request register 320.
Set to “1”. The output signal of the first read request register 320, ie, the first read request signal shown at 15 in FIG. 4b, is input to the terminal 402 of the memory control circuit 400 and becomes a read request signal.
The memory control circuit 400 starts a read operation based on this read request signal and transfers the data to the memory circuit 1.
When read from 30, the first load signal DL shown at 17 in FIG. On the other hand, this first load signal DL is sent to the read request reset circuit 3.
30 is also entered. The read request reset circuit 330 indicates that the data has been stored in the first output register 140 by using the input first load signal.
DL and resets the first read request register 320. The data changes in the first and second output registers 140 and 170 are as shown in FIG. 4b.
As shown in 8 and 19.

In the read operation completed as described above, the second
From the output register 170 to the parallel-to-serial conversion circuit 150
After a series of data transfers from the first output register 140 to the second output register 170 is completed, a read request signal is generated and a read operation is started.
After the read request signal is issued at a certain time (for example, t ₃ shown at 15 in FIG. 4B), the read operation is started within one memory operation cycle (t ₄ shown at 15 in FIG. 4B),
Since the read operation is completed in half the memory operation cycle (from _t4 ), the read operation is completed within a total of 1.5 memory operation cycles.

On the other hand, the parallel load signal PO may also be generated in one memory operation cycle, and in this case, data is transferred from the second output register 170 to the parallel-to-serial conversion circuit 150. As mentioned above, data read within 1.5 memory operation cycles is immediately transferred from the first output register 140 to the second output register 170. Since the read request signal generated by this data transfer is synchronized with the memory operation cycle, the read operation accompanying this read request signal is 1
Completes in memory operation cycle. Therefore, after the parallel load signal PO is generated and the second read request signal is generated accordingly, data will be stored in the second output register 170 within half a cycle of the memory operation. What output clock OR
-Be able to respond to EQ.

FIG. 5a is a block diagram of the third embodiment, and FIG. 5b is a time chart for explaining its operation.

The buffer memory of this third embodiment has a parallel expansion number P=m/r (r is any integer less than or equal to m)
The feature is that r memory units consisting of n storage modules, input and output control circuits, and memory control circuits are operated in parallel. In order to simplify the explanation, the case where r=2 and m=8 will be explained below.

The n-bit parallel input data DI _i applied to the terminal 100 _i is stored in two memory units 500 respectively.
_{1,500 2} corresponding storage modules 100 _i
are input in parallel. On the other hand, an input clock IREQ inputted from the terminal 103 and synchronized with the input data DI _i is supplied to each memory unit 500 ₁ , 50 .
The clock is simultaneously input to the input control circuit 200'' of 0 _{and 2} , and is also input to the first input clock frequency divider circuit 510. In this example, the frequency is divided by 4.The output of the first input clock frequency divider circuit 510 is connected to the second input clock frequency divider circuit 520.The second input clock frequency divider circuit 520 is Generally, input signals are counted, and when the count value is k'(k' = 1, 2, ... r), r
This is a circuit that sets the k'th output signal to "1" among the output signals, and each of these r output signals is used as a k'th writing unit switching signal and is output to the corresponding memory unit 500k'. . Here r=2
Therefore, the second input clock frequency divider circuit 520 may be a simple frequency divider circuit by two, and the write unit switching signal shown at 4 in FIG. 5b can be obtained. In the figure, the memory unit ₅₀₀₁ is used as a write unit in the "0" interval, and the memory unit ₅₀₀₂ is used as the write unit in the "1" interval. The write unit switching signal is sent to the input control circuit ₂ of each memory unit ₅₀₀₁ , 5002.
00'' to the input clock gate circuit 260.The input clock data circuit 260 is input to the input clock gate circuit 260 located at the memory unit 00''.
Pass the input clock IREQ mentioned above. Therefore, the first memory unit ₅₀₀₁ outputs the input clock IREQ only while the write unit switching signal shown at 4 in FIG.
An input clock IREQ' is obtained, and in the second memory unit ₅₀₀₂ , a second input clock IREQ' shown in FIG. In this example, these second
When the input clock IREQ' is "0", there is no clock, and when it is "1", four clocks are output. Note that the input clock IREQ is synchronized with the input data shown at 3 in FIG. This input clock IREQ' is connected to a terminal 111 of the serial-to-parallel conversion circuit 110 of the storage module _100i .
, and shifts the input data one bit at a time.

The second write request register 2 is input to the serial-to-parallel converter circuit 110 when a number of data equal to the number of parallel expansions P=4 is completed, that is, at the rising edge of the write unit switching signal in the memory unit ₅₀₀₁ .
40 is set to "1". The output of this second write request register 240 is connected to an input register clock generation circuit 250. On the other hand, the input register clock generation circuit 250 has a first
The output of the write request register 220 is also connected, and the first write request register 220 is "0" and the output of the second write request register 240, that is, the second write request signal is "1". When this happens, the input register clock PI is output. This input register clock PI is input to the input register 120 of the storage module _100i , and stores the data of the serial-to-parallel conversion circuit 110. In addition, the input register clock generation circuit 250 also outputs a signal obtained by delaying the input register clock PI for a very short time, and at the same time resets the second write request register 240, the first write request register 220 is set to "1". Set. Therefore, the second write request signal and input register clock PI are as shown at 6, 7 and 12, 13 in FIG. 5b for the first and second memory units 500 ₁ and 500 ₂ , respectively.

Further, the output of the first write request register 220, that is, the first write request signal shown at 8 or 14 in FIG. A write command signal shown at 9 in FIG. 5B fed back from the memory control circuit 400 is input to the write request reset circuit 230. The write request reset circuit 230 detects the completion of the write operation, for example, at the falling edge of the write command signal, and resets the write request register 220.

In the write operation completed as described above, the write operation is smoothly performed by using the serial-to-parallel conversion circuit 110 as one buffer register. That is, the serial-parallel conversion circuit 1
The second input clock IREQ' input to the 5th
As shown at 5 or 11 in Figure b, there is always a 4-bit non-input section after 4-bit input. Therefore, since the data in the series-parallel circuit 110 does not change during this no-input period, the input register 1
Data can be transferred to 20. A write operation based on a write signal that occurs at a certain time (for example, t ₁ shown at 6 in FIG. 5B) is completed within 1.5 memory operation cycles from that time t ₁ (at t ₂ shown at 9 in FIG. 5B). ), whereas there is one memory operation cycle from the generation of the previous write request signal (t ₁ ) to the next generation (t ₃ ),
After this, there is a no-input period of more than half a cycle of the memory operation, so the write operation is completed during this period, and data transfer to the input register 120 is also possible.
Therefore, any input data will be completely written.

Next, the read operation will be explained. terminal 104
The output clock OREQ input from the output clock gate circuit 360 in the output control circuit 300'_' of each memory unit ₅₀₀₁ , 5002
At the same time, it is input to the first output clock frequency divider circuit 610. The output of the first output clock frequency divider circuit 610 is further inputted to a second output clock frequency divider circuit 620, and is used as the two first and second read unit switching signals to output the corresponding memory unit 5.
Output at 00 ₁ , 500 ₂ . 1st and 2nd
The operation of the output clock divider circuits 610, 620 is exactly the same as that for the input clock;
A readout unit switching signal shown at 18 in FIG. b is obtained. It is assumed that the output data DO shown at 17 in FIG. The above reading unit switching signal is input to the output clock gate circuit 360 of the output control circuit 300''.Output clock gate circuit 360
is a second clock which passes the output clock OREQ inputted to one side only for the period in which the memory unit is selected, by the same operation as that at the input.
The output clock OREQ' of the memory module _100i
The parallel-to-serial conversion circuit 150 is output to the parallel-serial conversion circuit 150. The second output clocks OREQ' of the first and second memory units 500 ₁ and 500 ₂ are shown at 19 and 27 in FIG. 5b. The second output clock OREQ' outputs the 4-bit data stored in the parallel-serial conversion circuit 150 to the output data multiplexing circuit 630 bit by bit.
The output data multiplexing circuit 630 switches the data input from the two memory units 500 ₁ and 500 ₂ according to the read unit switching signal and outputs the data as output data DO _i .

When all 4-bit data of each parallel-to-serial conversion circuit 150 has been output, that is, in the first memory unit ₅₀₀₁ , the second read request register 34
0 is set to "1". The output signal of the second read request register 340, i.e. 20 in FIG.
Alternatively, the read request signal shown at 28 is output to the parallel load signal generation circuit 350. The parallel load signal generation circuit 350 converts the parallel load signal PO into a parallel-to-serial conversion circuit when the output of the first read request register 320 (described later) is "0" and the second read request signal becomes "1". Output to 150. The parallel-to-serial conversion circuit 150 receives this parallel load signal PO.
When input, the contents of the output register 140 are stored and prepared for the next data output. On the other hand, the parallel load signal generation circuit 350 also outputs a second output signal obtained by delaying the parallel load signal PO for a very short time, and resets the second read request register 340 and at the same time sets the first read request register 320 to " Set to 1”. The parallel load signal PO is shown in Figure b.
21 or 29. The output of the first read request register 320, the first read request signal, is input to the memory control circuit 400. The memory control circuit 400 starts a read operation in response to the input of this first read request signal, and transfers the data to the storage circuit 130.
At the same time, the read data is stored in the output register 140 by the load signal DL. The load signal DL is also input to the read request reset circuit 330. The read request reset circuit 330 detects from the load signal DL that data has been stored in the output register 140, and
Reset read request register 320. 1st
The read request signal and the read command signal of the memory control circuit 400 are shown at 22, 23 and 30, 31 in FIG.
The load signal DL of the memory unit is set to 24 in b of the same figure.
The data storage timing in the parallel-to-serial conversion circuit 150 and the output register 140 is shown at 25 and 26 in FIG.

In the read operation that completes the above operations, just as in the write operation, when all the data from the parallel-to-serial conversion circuit 150 is output (for example, t ₁ shown at 19 in FIG. 5b), the next Since the new data is stored in the parallel-to-serial converter circuit 150, it is only necessary to output the new data and read the data to the output register 140 before the next data output start time ( _t2 ). This interval (t ₁ to t ₂ ) is
1.5 memory operating cycles or more. On the other hand, since the read operation is completed within 1.5 memory operation cycles (from _t1 ), it is possible to follow any output clock OREQ.

Furthermore, although r=2 and m=8 are used for the third embodiment described above for convenience of explanation, it is clear from the above description that the same operation can be performed for arbitrary r and m. In particular, the difference between r=2 and more is the first input and output clock frequency divider circuits 510 and 610, and the second input and output clock frequency divider circuits 520 and 620.
The frequency division ratio of the output data multiplexing circuit 6 changes and the output data multiplexing circuit 6
30 switches and outputs each memory unit output signal in response to the read unit switching signal. Furthermore, the timing circuit of the memory control circuit 400 can be shared by each memory unit.

According to the present invention, the control circuit is extremely simple, requiring only a few timing circuits for synchronizing asynchronous data in addition to write/read signals, address signals, etc. necessary for operating the memory circuit. Moreover, since it is sufficient to operate n memory modules in parallel in response to n parallel input bits, the above-mentioned waiting circuit is not required.
The buffer memory configuration can be simplified. Furthermore, since the write/read operation cycles are completely periodic, inspection and retention are easier, and vacant read operation cycles can be used to refresh the memory element, and the input/output data rate is 0. ~
This provides many advantages in that it can be arbitrarily selected between c.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the interframe encoding method. 1 is an A/D converter, 2 and 8 are frame memories, 3 is an encoder, 4 is a decoder, 5,
6 is a buffer memory, 7 is a decoder, and 9 is a D/A converter. FIG. 2a is a diagram showing the basic configuration of a buffer memory according to the present invention. 100 ₁ , 100 ₂ ,...
...100 _o is a storage module, 200 is an input control circuit, 300 is an output control circuit, and 400 is a memory control circuit. FIG. 1B is a detailed configuration diagram of the storage module 100. 110 is a serial-to-parallel conversion circuit, 120 is an input register, 130 is a storage circuit, 140 is an output register, and 150 is a parallel-to-serial conversion circuit. FIG. 1c is a diagram for explaining the configuration of the memory circuit 130. Figure d is a detailed configuration diagram of the memory control circuit 400, and Figure e is an operation time chart thereof. 4
10 is a timing circuit, 421 is a write command register, 422 is a write column counter, 423 is a write address counter, 424 is a write column signal timing gate circuit, 425 is a write signal gate circuit, 431 is a read command register, 432 read column counter, 4
33 is a read address counter, 434 is a read column signal timing data circuit, 435 is a read column signal gate circuit, 440 is an address switching circuit, 44
1 is a column selection signal logic circuit, 442 is a write control gate circuit, and 443 is a read control gate circuit. FIG. 3a shows a first embodiment of the buffer memory according to the present invention, and FIG. 3b shows its operation time chart. 200 is an input control circuit, 210 is an input clock frequency divider circuit, 220 is a write request register,
230 is a write request reset circuit, 300 is an output control circuit, 310 is an output clock frequency dividing circuit, 320
Reference numeral 330 indicates a read request register, 330 a read request reset circuit, and 400 a memory control circuit. FIG. 4a shows a second embodiment of the buffer memory according to the present invention, and FIG. 4b shows its operation time chart. 200' is an input control circuit; 240 is a second write request register; 250 is a second input register clock generation circuit; 300' is an output control circuit;
40 is a second read request register, and 350 is a second load signal generation circuit. FIG. 5a shows a third embodiment of the buffer memory according to the present invention, and FIG. 5b shows an operation time chart. 500 ₁ , 500 ₂ are memory units, 2
00'' is an input control circuit, 240 is a second write request register, 250 is an input register clock generation circuit,
260 is an input clock gate circuit, 300' is an output control circuit, 340 is a second read request register,
350 is a parallel load signal generation circuit, 360 is an output clock gate circuit, 510 is a first input clock frequency divider circuit, 520 is a second input clock frequency divider circuit,
610 is a first output clock frequency dividing circuit, 620 is a second output clock frequency dividing circuit, and 630 is an output data multiplexing circuit.

Claims (1)

[Scope of Claims] 1. A memory element P×Q in which the main clock frequency is c and the operation frequency m of periodic memory operation cycles including both write/read operation cycles is c/m (m is a positive integer). (P, Q are positive integers) and the main clock frequency c
A serial-parallel conversion circuit converts serial input data at a lower data rate into parallel data every P bits, and the output of the serial-parallel conversion circuit is temporarily stored and data is received every P bits into the storage circuit. A memory module is provided with an input register for passing, an output register for temporarily storing the output of the memory circuit, and a parallel-to-serial conversion circuit for receiving the output of the output register and converting it into serial output data every P bits. The serial-to-parallel conversion circuit includes n input frequency divider circuits that are provided corresponding to input/output data of bits (n is a positive integer) and divides the input clock input in synchronization with the input data by P. an input control circuit that controls the input register; and an output control circuit that controls the parallel-to-serial conversion circuit and the output register, including an output frequency divider circuit that divides an output clock input in synchronization with output data by P; and a control circuit for writing/reading the memory circuit in a predetermined memory operation cycle when data is input to the input register and when data in the output register becomes empty. Buffer memory for conversion. 2. In the buffer memory of claim 1, the number P of parallel expansion of each storage module is D≧
1.5×m, the output of the input frequency divider circuit transfers the data of the serial-to-parallel conversion circuit to the input register, and the output of the output frequency divider circuit transfers the data of the output register to the parallel-to-serial conversion circuit. A buffer memory for image encoding, characterized in that: 3 In the buffer memory of claim 1, the number of parallel expansions P of each storage module is P=m
Furthermore, the input register and the output register are each set to two stages, the input register of the first stage stores the data of the serial-to-parallel converter circuit by the output of the input frequency divider circuit, and the input register of the next stage stores the data of the serial-to-parallel converter circuit using the output of the input frequency divider circuit. When there is data in the input register, the data is stored by a signal synchronized with the memory operation cycle, the first stage output register stores the data read from the storage circuit, and the next stage output register stores the data. After transferring the data to the parallel-to-serial conversion circuit, when the next data is stored in the output register of the first stage, the data is stored and the output of the output frequency dividing circuit is transferred to the next stage output register. 1. A buffer memory for image encoding, characterized in that the data is transferred to the parallel-to-serial conversion circuit.