JPS63300289A - Image memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an image memory device using a semiconductor memory.
In particular, the present invention relates to a moving image memory device capable of inputting and outputting moving image signals in real time.

These devices are combined with arithmetic circuits such as combinators and used as image processing/generation devices, special effects devices, format conversion devices, and the like.

[Conventional technology]

Conventionally, this type of image memory device has a unique configuration depending on the format of the video signal handled and the sampling frequency of the signal, and is therefore a dedicated memory device that can only handle one type of video signal. As shown in Figure 6, the memory address generation circuit has a horizontal address generation section for accessing pixels in the horizontal direction of the screen, a vertical address generation section for selecting a vertical scanning line, and a frame or field. This is because the frame address generation section counts the number of frames. There are several papers on this kind of memory organization method, for example (Kaneko et al.
1 General-purpose video processing system equipped with large-scale image memory”
, IEICE Theory vol. J 68-D +Yo 4).

[Problem that the invention seeks to solve]

By implementing the address generation circuit so as to match the screen configuration of the video signal to be handled in this way, there is an advantage that when data in the image memory is accessed by, for example, a combinator, its position can be easily determined. However, as stated at the beginning of the specification, the size of the image is given, and a memory device designed accordingly has the drawback of losing versatility.

The present invention aims to provide a more efficient meshing device that can input and output any signal in real time to and from a single memory device, regardless of the format of the data such as the format of the video signal, and as long as it is below a certain sampling frequency. It is something.

[Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a first embodiment of the present invention, in which a plurality of memos 17 I Cl, a serial/parallel conversion circuit 2 that converts serially input video signals into parallel, and a memory IC 1 that reads out video signals from the memory IC 1 are connected. A parallel-to-serial conversion circuit 3 converts parallel video data into a series and outputs the result, a write address generation circuit 4 to generate a write address for the memory ICI, a read address generation circuit 5 to generate a read address, and a serial-to-parallel conversion circuit A write gate circuit 6 gates the write clock 7 that drives the circuit 2 and the write address generation circuit 4 with a write frame pulse, and a read clock 9 that drives the parallel-to-serial conversion circuit 3 and the read address generation circuit 5 is gated with a read frame pulse. It is composed of a readout gate circuit 7 that applies a gate, and a video complement circuit 11.

Here, the sampling period of the video signal is set to t8% memory I
If the access time of CI is 1a, normally ta)tl
It is. Therefore, simply by connecting the video signal to the memory IC1, it is not possible to write the video signals that arrive one after another without stopping. Therefore, a plurality of memories ICI are prepared as shown in the figure, and these are operated in parallel. When the number of parallel phases is n, the memory access time is effectively reduced by ta/nK by parallel operation. Therefore, it is possible to set tl/n(t3) and write and read in real time.

The value of n is the highest sampling frequency tsma of the six video signals considered to be used in this image memory device.
It is determined by substituting x and ta of the applied memory ICI into the above equation.

In order to operate the memories ICI in parallel in this way, the serial/parallel conversion circuit 2. shown in the figure is used. A parallel-to-serial conversion circuit 3 is required.

These circuits operate with clocks (write clock 7 and read clock 9, respectively) that match the sampling frequency of the video signal. Then, it writes to and reads out the memo IJIC1 every n-ts.

Further, the write address generation circuit 4 is a counter that counts up every n-tS, and is driven by the write clock 7. The generated address is memo IJ
Supplied to IC1. Accordingly, the video signals are sequentially written into the memory. The same applies to the read address generation circuit 5.

With the above-described configuration, any video signal having a sampling frequency less than or equal to tsmax can be input and output in real time, and this is because the video signal is treated as one-dimensional information and the synchronization signal portion is also stored. Therefore, input data can be handled not only as video signals but also as continuous data such as audio.

However, for example, there may be cases where a user wants to store moving images in a memory device and output only one still image from among the moving images. In other words, this is a case where only one frame of video needs to be read out from a memory device in which a plurality of frames are stored as one-dimensional information. At this time, memory IC1
Since the stroke information is stored without a delimiter called a frame, if the above-mentioned parallel operations are performed, it becomes impossible to freely extract the start and end points of the frame.

Therefore, using a frame pulse as shown in Fig. 2, the operation of the serial-to-parallel converter circuit 2 and the write address generation circuit 4 is stopped during the period when the pulse is at O level, and the video signal during this period is not written into the memory. do it like this. This operation is performed, for example, by the write gate circuit 6 shown in FIG.
This can be achieved by setting K so that it is not supplied to

On the other hand, on the read side as well, the read system is temporarily stopped by controlling the read frame pulse. The period of suspension should be supplemented with other data. For example, the video signal immediately before stopping is held and output.

Here, the frame pulse pulse [Lr is calculated by dividing the integer If it represents the remainder of , it is given by tf=modulo (p −1, n ). In general, the memory stores frame images whose number of data is n times the number of parallel phases.

Even if such a control circuit using frame pulses is provided, it is sufficient to supply the input video signal to the memory device and a clock or frame pulse synchronized with this, and each circuit operates according to this, so the versatility of the device is lost. It won't happen.

In the first embodiment shown in FIG. 1, frame pulses are used to control writing and reading, but field pulses may also be used. This is shown in Figure 3. As shown in the figure, if the field pulse width of an odd field in an interlaced video signal is tf + one line of vertical period + tf for an even field, the data in the memory will be This eliminates the distinction between even fields, which can be useful. In this case, the complement data for one line in the video complement circuit 11 may be the one line data immediately before the stop.

In the above embodiment, a device that handles one video signal was shown;

It is also possible to handle component signals such as C2 signals. FIG. 4, which shows the third embodiment, shows this configuration.

Furthermore, using this device for component signals, N
When processing a composite signal such as a T8C signal, three image memory devices can be effectively used by configuring as shown in FIG. In other words, a three-phase serial-to-parallel conversion circuit is used to reduce the input rate of the video signal to each memory device by one-third and store the video signal. This is possible because the configuration of the present invention allows input/output in real time regardless of the sampling frequency.

〔Effect of the invention〕

According to the present invention, as explained above, no-visi=1/
A general-purpose image memory device that can be used regardless of the format of the video signal, such as a signal, NT8C signal, or component signal, and regardless of the sampling frequency can be obtained.

Therefore, it can be economically applied to fields where various video signals must be handled, such as program production systems in broadcasting stations in the new media era and image processing devices in research laboratories.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an image memory device according to an embodiment of the present invention, FIG. 2 is a diagram showing a timing chart of frame pulses for writing or marking in the embodiment of FIG. 1, and FIG. A diagram showing the operation of the second embodiment of the present invention,
A diagram showing a timing chart when the frame pulse in the first embodiment is modified to a field pulse VC fc, and FIG. 4 is a diagram showing the third embodiment of the present invention, which is a configuration diagram when handling a component type video signal. , FIG. 5 is a diagram showing a case where an image memory device for composite signals is configured using the configuration of FIG. 4, and FIG. 6 is a diagram explaining the configuration of a conventional image memory device. Agent: Susumu Uchihara, Patent Attorney 1. . -/' Guheef t-x car--1 fnts/) f4tcP, -1 Fig. 2

Claims (1)

[Claims] A memory circuit that operates a plurality of semiconductor memories in parallel to write and read digital video signals in real time that have a sampling period shorter than the access time of the memory; This occurs when the digital video signal is written into the memory circuit, and the synchronization signal part of the video signal is also written, and the period of the frame or field is divided by the number of parallel phases of the parallel operation of the memory. A write control circuit that stops the write operation of the memory circuit during the surplus period and controls not to write data only during that period; A memory device having a read control circuit configured to stop reading from the memory and supplement this period with other data.