JP2616230B2 - Asynchronous counter circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding an initialization method of an asynchronous counter circuit, the object of the invention is to provide a counter circuit capable of performing initialization to an arbitrary initial value, and each of them operates in synchronization with the output of the preceding stage. In a counter circuit composed of a first frequency dividing circuit to an N-th frequency dividing circuit, control information for initializing the count cycle of the counter circuit to a desired timing is stored in the first frequency dividing circuit to the (N-1) th frequency dividing circuit. First state holding means to (N-1) th state holding means for holding to the next count using the output of the circuit, first set value writing means for setting the control information as a set value of the first frequency dividing circuit, Second setting value writing means to N-th setting value writing means for setting the held output of the first state holding means to the (N-1) th state holding means as the set value of the second frequency dividing circuit to the N-th frequency dividing circuit. Is provided.

[Industrial applications]

The present invention relates to an initialization method for an asynchronous counter circuit.

[Conventional technology]

FIG. 4 is a diagram showing an example of writing the set value of the counter circuit, wherein (A) and (B) show examples where the write output of the counter circuit is "H", and (C) and (D) show the write output. Is "L". In the figure, reference numeral 41 denotes a flip-flop (hereinafter referred to as FF) as a counter circuit, reference numeral 42 denotes an OR operation circuit (hereinafter referred to as OR), and reference numerals 43 and 44 denote input signal inversion output circuits (hereinafter referred to as INV). Reference numeral 45 denotes an AND operation circuit (hereinafter, referred to as AND).

In FIG. 7A, the logical sum of “H” of data (hereinafter, referred to as “D”) and “H” of control information of a set value (hereinafter, referred to as “F”) is obtained.
OR42, and the logical sum value is used as a write signal as D in FF41.
In addition to the terminal, the signal is punched out and held by the clock C, and at the timing of the next clock C, a signal is read from the positive terminal Q (hereinafter referred to as the Q terminal) with the “H” portions of D and F set to “H”. Soup In FIG. 3B, the logical product of the output obtained by inverting “H” of D with INV43 and the output obtained by inverting “H” of F is given by AN.
D45, the logical product value is added as a write signal to the FF41, and is punched and held by the clock C. At the next clock C timing, the negative and positive terminals * Q (hereinafter referred to as the * Q terminals) are connected to the D and F terminals. A signal with the “H” portion set to “H” is read. Similarly, in FIG. 4C, the logical product of the inverted signals of D and F is applied to the D terminal as a write signal to FF41, and the terminal Q
From this, a signal in which the "L" portion of D and the "H" portion of F are set to "L" is read out. In FIG. 4D, a signal in which the "L" of D and the "H" of F are "L" is read from the terminal * Q. Hereinafter, an example of a counter circuit using the circuits of FIGS. 4A to 4D is shown in FIGS.

FIG. 5 is a diagram showing a circuit of a conventional example, and is a circuit diagram of an asynchronous counter designed without considering the initial setting. FIG. 6 is a diagram showing a time chart of a conventional circuit of one embodiment.

In FIG. 5, reference numeral 1-1 denotes a synchronous first frequency divider which uses the reference signal of the circuit as a clock, and 1-2 denotes a synchronous second frequency divider which uses the output of the first frequency divider 1-1 as a clock. It is a frequency dividing circuit. Reference numeral 1-3 denotes a synchronous third frequency divider which uses the output signal of the second frequency divider 1-2 as a clock. The output signals of the first frequency divider 1-1 and the second frequency divider 1-2 are
Asynchronous frequency dividers of 6 × 6 × 3 = 108 are formed by using the clocks of the synchronous frequency dividers at the next stage.

Reference numerals 11 to 13 denote FFs using the input reference signal as a clock, 11 denotes a first FF corresponding to the circuit shown in FIG.
12 is a second FF corresponding to the circuit shown in FIG.
13 is a third FF that combines the operations of FF11 and FF12. Further, 14 is the first NOR of the inverted OR operation circuit having the negative polarity output of the second FF12 and the positive polarity output of the third FF13 as inputs, and 15 has the positive polarity output of the first FF11 and the first NOR14 as inputs. This is the first OR of the OR circuit, and these 11 to 15 form the above-mentioned synchronous divide-by-6 circuit 1-1. Similarly, reference numerals 21 to 23 denote circuits having the same operation as the first FF11 to the third FF13, and the fourth to sixth FFs to the sixth FF11 which use the output signal of the first FF11 which is the output of the first frequency divider 1-1 as a clock. FF, 24 is a second NOR having inputs of the outputs of the fifth FF22 and the sixth FF23, and 25 is a second OR having inputs of the outputs of the second NOR24 and the fourth FF21. Is formed. Further, 31 and 32 are circuits having almost the same operation as the FF12, and the seventh FF and the eighth FF clocked by the output of the fourth FF21 which is the output of the second frequency divider 1-2, and the 33 are the seventh FF31. And a third OR having the negative output of each of the third and eighth FF32s as inputs. These 31-33 form a synchronous divide-by-3 circuit.

In FIG. 6, (a) is a reference signal serving as a clock of the present circuit, (b) is a reset signal of the present circuit, and (c),
(D) and (e) are the first FF11, the second FF12, and the third FF13 provided in the first frequency dividing circuit 1-1 using the reference signal (a) as a clock.
Of the reference signal, and corresponds to the divide-by-6 output of the reference signal (a). The signals (h), (i) and (j) are the fourth FF21 and the fourth FF21 provided in the second frequency divider 1-2 using the output signal (c) of the preceding first frequency divider 1-1 as a clock. 5th FF22, 6th FF23
, Which corresponds to the 6 × 6 = 36 frequency-divided output of the reference signal (a). Also, the signal (m) and the signal (n) are the positive electrodes of the seventh FF31 and the eighth FF32 of the synchronous third frequency divider circuit using the output signal (h) of the preceding third frequency divider circuit 1-3 as a clock. 6 × 6 × 3 based on the reference signal (a)
Equivalent to 108 divided output.

The conventional example of FIG. 5 will be described below with reference to FIG. When a clock, which is a reference signal (a) indicating the reference of the present circuit, is sequentially input and a reset signal (b) is input as shown in FIG. 5, each time the reference signal (a) is input, 1 is output. The clock is shifted by one clock, and the positive output (c) and the negative output (c ') at the clock timing, (d) and (d') at the same timing, and (e) and (e ') at the timing. Output from the first FF11 to the third FF13, and the same operation is repeated thereafter. The outputs (d ') and (e) are fed back to the first NOR 14 and the output (e') is fed back to the first FF11. Sends out. Next, when the output (c) of the frequency divider 1-1 is input to the second frequency divider 1-2 as a clock, the second frequency divider 1-2 operates in the same manner as the first frequency divider 1-1. The signals shown in FIGS. 6 (h) to (j) are sequentially output from the fourth FF21 to the sixth FF23. Similarly, the outputs of FIGS. 6 (m) and (n) are sequentially transmitted from the third frequency dividing circuit 1-3 using the signal (h) as a clock.

In the circuit of such a continuous counting operation, for example, the state of the set value = “8”, that is, the signal state of the area (A) in the second clock is (c) = 1, ( d) = 1, (e) = 0, (h) = 1, (i) = 1, (j) = 0 in the region (B), and (m) = 1 in the region (C). , (N) = 0,
These are the count values at a certain moment in the continuous count of each of the FFs 11, 12, 13, 21, 22, 23, 31, 32.

As described above, in the conventional asynchronous counter circuit, the count operation is started by resetting the counter circuit without performing the initial setting.
Therefore, when a certain value is desired to be initially set, it must be taken into consideration at the stage of designing the counter circuit.

[Problems to be solved by the invention]

Therefore, the counter circuit once designed has no versatility with respect to the initial value. That is, when the initial value changes, the counter circuit must be designed again in consideration of the value. There is a problem that it causes an increase.

An object of the present invention is to provide an asynchronous counter circuit capable of initializing an arbitrary initial value.

[Means for solving the problem]

In order to achieve the above object, according to the present invention, in a counter circuit including a first frequency dividing circuit 1-1 to an N-th frequency dividing circuit 1-n, each of which operates in synchronization with a preceding stage output, The control information for initially setting the cycle to a desired timing is stored in the first frequency dividing circuit 1-1 to the (N-1) th frequency dividing circuit.
The first state holding means 3-1 to the (N-1) th state holding means 3- which hold until the next count using the output of the frequency dividing circuit 1-n.
(N-1), a first set value writing unit 2-1 for setting the control information as a set value of the first frequency dividing circuit 1-1, and the first state holding units 3-1 to N-1. The held output of the state holding means 3- (n-1) is output from the second frequency divider 1-2 to the N-th frequency divider 1-
The second set value writing means 2-2 to the N-th set value writing means 2-n for setting the set value of n are provided.

[Action]

In the present invention, as shown in FIG. 1, in an asynchronous counter circuit composed of N stages of first frequency divider circuits 1-1 to N-th frequency divider circuits 1-n, each of which operates in synchronization with each other, The control information is input to the first-stage first setting value writing means 2-1 for initial setting, and the initial setting value is stored in the first-stage first frequency dividing circuit 1--1.
1 is written directly, and the second and Nth frequency dividers 1-2 to 1-n in the second and subsequent stages are used by the frequency dividers 1-2 to 1-n. The output of the first frequency dividing circuit 1-1 to the (N-1) th frequency dividing circuit 1- (n-1) in the preceding stage is used by the first state holding means 3 based on the control information until the next count.
1 to the (N-1) th state holding means 3- (n-1), and write the next count value of the set value in each of the second frequency dividing circuits 1-2 to the N-th frequency dividing circuit 1-n. I have to.

Therefore, the first set value writing means 2-1 writes a desired initial set value, and the second divider circuit 1-2 to the N-th divider circuit 1-n write the next value after the initial set value. Is written in the asynchronous counter circuit.

〔Example〕

FIG. 2 is a diagram showing a circuit of one embodiment of the present invention, and FIG. 3 is a diagram showing a time chart of the circuit of one embodiment of the present invention. FIG. 3 shows a case where the initial setting = “8” is performed by input of control information in the asynchronous counter designed without considering the initial setting shown in FIGS. 5 and 6.

In FIG. 2, reference numeral 1-1 denotes a first frequency divider circuit of a synchronous divide-by-6 system using the clock signal of the present circuit as a clock, and the first FF11 to the third FF13, the first NOR14, the first OR15 of the conventional circuit. And an 11th OR16 corresponding to the first set value writing means 2-1 of the present invention.
To the 13th OR18. Reference numeral 1-2 denotes a synchronous frequency-divided second frequency dividing circuit that uses the output signal of the first frequency dividing circuit 1-1 as a clock, and is a fourth to sixth FF23, a second NOR24, and a fourth FF21 of the conventional circuit.
There are provided the second OR25, the fourteenth OR26 to the sixteenth OR28 corresponding to the second set value writing means 2-2 of the present invention, and the ninth FF29 corresponding to the first state holding means 3-1. Also, 1-3 is a second frequency divider 1-2.
Is a synchronous frequency-divided-by-3 circuit that uses the output signal as a clock, and corresponds to the seventh to eighth FF32s and the third OR33 of the conventional circuit and the third set value writing means 2-3 of the present invention. 17th OR3
4. Tenth FF3 corresponding to the eighteenth OR35 and the second state holding means 3-2
6 is provided. These output signals of the first and second frequency dividers 1-1 and 1-2 are synchronized with the second and second synchronous frequency dividers 1-2, respectively, similarly to FIG. 6 × 6 × 3 = 108 by using for the clock of the divide-by-3 circuit 1-3
Is formed.

FIG. 3 is a time chart showing the operation of FIG.
The signals (a), (b), (c), (d), (d '),
(E), (e '), (f), (g) and (h), (i),
(I '), (j), (j'), (k), (l) and (m), (m ') (n), (n'), (o), and further (p), (q ) And (r) show the output of each circuit at each point of the circuit of FIG.
(D '), (e), (f), (g) and (i'),
(J), (k), (l) and (m ') and (n'),
(O) is omitted from FIG. The signal (p) is control information for initial setting of the circuit, and the signal (q) is a ninth FF reset by the control information (p).
The negative output 29 and (r) are the negative output of the tenth FF36 reset by the control information (p).

In the case where the first frequency dividing circuit 1-1 to the third frequency dividing circuit 1-3 have already been reset to the signal (b) (not shown) and repeat the self-running count in a certain cycle, any (in this example, the At the time of initial setting at the timing of the (eighth clock), FIG. 3 (p) of the control information is input. Now, the initial setting value is "8", which corresponds to the eighth clock, that is, (c) = 1, (d) from the time chart of FIG.
= 1, (e) = 0, (h) = 1, (i) = 1, (j) =
It can be seen that 0, (m) = 1, and (n) = 0 are the counter values “8”. Therefore, the first frequency dividing circuit 1-1 shown in FIG.
The initial setting values of each of the FFs 11, 12, and 13 are (c) = 1, (d) =
1, (e) = 0, so that (c) = 1, (d)
For = 1, the control information (p) is directly
In the 12th OR17, the control information (p) is ORed with the positive output (e) of the third FF13 in the 11th OR16.
In OR17, the logical sum of the control information (p) and the output (g) of the first OR15 is calculated. For (e) = 0, the logical OR of the negative output (d ') of the second FF12 and the control information (p) is calculated by the third OR.
In step 18, "0" is output from the third FF13 with the polarity of the output of the thirteenth OR18 inverted. In addition, since the polarity of the output pattern of the third FF13 is inverted by doing this, the output polarity of the second FF12, which is the data input destination, is inverted and the first FF13 is inverted.
Input to NOR14 and 11th OR16. The result of performing the above is shown in the area (A), and this circuit is the first frequency dividing circuit 1-1 shown in FIG.

Next, (h) = 1, (i) = 1, and (j) = 0,
Since the synchronous second frequency dividing circuit 1-2 is an asynchronous frequency dividing circuit using the output from the previous stage without directly using the clock signal (a) targeted by this circuit, the above-mentioned first FF11 ~
The same operation as the third FF13 cannot be performed. For this reason, the first-stage frequency divider 1- 1 in the preceding stage, which is the clock of the second frequency divider 1-2.
The output (c) at the timing of 1 is set to “H” at one input terminal.
The output (q) is input to the fixed ninth FF29 and the control information (p) generates an output (q) in which the value at the timing of the output (c) is held until the next rising edge, for example.
Initial settings are made to FF21 to sixth FF23. By doing so, the initial set values are set to the values next to the timing, that is, (h) = 1, (i) = 1, and (j) = 1 of the timing.
That is, the output (q) shown in FIG. 3 is output from the ninth FF29 by the input of the control information (p), and this signal (q) is converted into the fourth FF21 and the fifth FF22 in the same manner as the signal (p) described above. , Sixth FF23
, Outputs such as outputs (h), (i), and (j) shown in the area (B) of FIGS. 2 and 3 are obtained.

Similarly, the third frequency divider 1-3 shown in FIG.
The initial set values of (m) = 1, (n) = 0 at the timing shown in the figure are changed to (m) = 1, as shown in the area (C) of FIG.
By performing the initial setting with (n) = 1, the third frequency dividing circuit 1-3 shown in FIG. 2 is obtained.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, it is possible to perform initial setting to an arbitrary initial value, and therefore, it is possible to reduce the design time and the circuit size.

[Brief description of the drawings]

1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a diagram showing a circuit of one embodiment of the present invention, FIG. 3 is a diagram showing a time chart of the circuit of one embodiment of the present invention, FIG. FIG. 5 is a diagram showing an example of writing a set value of a counter circuit, FIG. 5 is a diagram showing a circuit of a conventional example, and FIG. 6 is a diagram showing a time chart of the circuit of a conventional example. In the figure, 1-1 to 1-n denote first to Nth frequency divider circuits, and 2-1.
To 2-n are first set value writing means to Nth set value writing means,
3-1 to 3- (n-1) are the first state holding means to the (N-1) th state holding means.
State holding means.

Claims (1)

(57) [Claims] 1. A counter circuit comprising a first frequency dividing circuit to an N-th frequency dividing circuit, each of which operates in synchronization with a preceding stage output, wherein control information for initializing a counting cycle of the counter circuit to a desired timing is provided. From the first frequency dividing circuit to the Nth
A first state holding means to an (N-1) th state holding means for holding until the next count cycle using an output of the -1 frequency divider; and a first set value for setting the control information as a set value of the first frequency divider Writing means; and second set value writing means to N-th set values held by the first state holding means to the (N-1) th state holding means as set values of the second frequency dividing circuit to the N-th frequency dividing circuit. An asynchronous counter circuit comprising: a set value writing unit;