JPH0485796A - Control circuit for shift path - Google Patents

Abstract

PURPOSE:To increase a speed for shift operation of a flip-flop without changing the speed of clock by using the rise and fall of the clock. CONSTITUTION:This control circuit for shift path is provided with a 1st shift path part 31 which is constituted of plural stages of flip-flop 41-45 and makes data inputted to the 1st stage flip-flop 41 successively shifted by the same clocks 42-45, a 2nd shift path part 32 which is similarly constituted of plural stages of flip-flops 51-55 and makes data inputted to the 1st stage flip-flop 51 successively shifted by the clock, the phase of which is inverted, and a selection part 33 alternately selecting the data outputted from both of the 1st shift path part 31 and 2nd shift path part 32 respectively once for every one cycle of clock. Then, the data are processed by inverting the clocks of two shift path parts 31, 32, and on the other hand, the outputs of these shift path parts 31, 32 are selected by each one time for every one clock in the selection part 33 and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a shift path control circuit suitable for use, for example, when analyzing a fault.

[Conventional technology]

FIG. 2 shows an example of a conventionally used shift path control circuit. This shift path control circuit includes four stages of flip-flops 11-14. Data 21 is input to the input terminal of the first flip-flop 11. The output terminals Q of the first to third flip-flops 11 to 13 are respectively connected to the input terminals of the next stage. A shift clock 22 is supplied to the clock terminal CLK of each flip-flop 11-14. With this circuit, shift output data 23 is taken out from the output terminal Q of the fourth flip-flop 14.

In such a shift path control circuit, shift clock 2
The data 21 is sequentially shifted in synchronization with the rising edge of 2, and the shift output data 2 is output from the fourth flip-flop 14.
Outputs 3.

[Problem to be solved by the invention]

In the conventional shift path control circuit described above, data is shifted in synchronization with a single shift clock, and therefore data cannot be shifted at a higher speed than the frequency of the shift clock.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a shift bus control circuit that can shift data at a frequency higher than the frequency of a prepared shift clock.

[Means to solve the problem]

In the present invention, a first shift bus section is configured of a plurality of stages of flip-flops and sequentially shifts data input to the first stage flip-flops using the same clock;
It is also composed of multiple stages of flip-flops, and the first
A second clock that sequentially shifts the data input to the flip-flops of the stage using a clock whose phase is inverted from that of the clock.
and a selection section that alternately selects the data output from both the first shift bus section and the second shift bus section once per cycle of the clock. be equipped.

Then, while data is processed by inverting the clocks of the two shift bus sections, the outputs of these shift bus sections are selected and outputted once every clock by the selection section, thereby achieving the above-mentioned purpose. achieve.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to Examples.

FIG. 1 shows the configuration of a shift bus control circuit in one embodiment of the present invention. The circuit of this embodiment is composed of first and second shift bus control sections 31 and 32, and a bus selection section 33 that selects the buses output from these.

The first bus control unit 31 includes a five-stage flip 70 knob 41
It consists of ~45. first flip-flop 4
10 input terminals have data input terminals 46 to 21.
is now entered. The output terminals Q of the first to fourth flip-flops 41 to 44 are respectively connected to the input terminals of the next stage. Further, the shift clock 22 is supplied to the clock terminal CLK of each of the flip-flops 41 to 45 through a shift clock input terminal 47.

The second bus control unit 32 also includes a five-stage flip-flop 51.
55, and their connection relationship is basically the same as that of the first bus control section 31. However, a clock 57 obtained by inverting the shift clock 22 is inputted to the clock terminal CLK of the first stage flip-flop 51 via an inverter 56.

A shift mode signal 59 is input from a shift mode input terminal 58 to the shift mode terminals S of each of the flip-flops 41 to 45 and 51 to 55 in the first and second shift bus control sections 32. . These flip-flops 41 to 45 and 51 to 55 are set to a shift mode in which data can be shifted while a shift mode signal 59 is input.

In this shift mode, the fifth shift bus controller 31
The shift data 61 output from the output terminal Q of the flip-flop 45 and the fifth shift data 61 of the second shift bus control section 32
The shift data clock 2 output from the output terminal Ω of the flip-flop 55 is input to the bus selection section 33.

The shift clock 22 is input to this bus selection 833, and the shift output data 63 is output to the output terminal 64.

In the shift bus control circuit having such a configuration, in the shift mode state, the first shift path control section 31 shifts the data 21 at the rising edge of the shift clock 22, and the second shift path control section 32 shifts the data 21 at the falling edge of the shift clock 22. shift. This causes the fifth flip-flop 4
The shift data 61 and 62 outputted from the respective output terminals Q of 5.55 are supplied to the bus selection section 33. The bus selection unit 33 selects shift data 61 when the clock 57 does not rise, and selects another shift data 62 when the clock 57 rises. As a result, two shift data 61 and 62 are alternately output in one cycle of the shift clock 22.

〔Effect of the invention〕

As explained above, according to the present invention, by using the rising and falling edges of the clock, two shift operations can be performed in one clock, so flip-flops can be shifted without changing the clock speed. This has the effect of substantially speeding up the operation.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a shift bus control circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventionally used shift path control circuit. 21...Data, 22...Shift clock, 31...First shift bus control unit, 32
...Second shift bus control section, 33...
・Bus selection section, 41-45. 51-55...Flip-flop, 57...--Inverted clock, 63...
...Shift output data.

Claims (1)

[Scope of Claims] A first shift path section that is composed of a plurality of stages of flip-flops and sequentially shifts data input to the first stage flip-flop using the same clock, and also composed of a plurality of stages of flip-flops. The first
A second clock that sequentially shifts the data input to the flip-flops of the stage using a clock whose phase is inverted from that of the clock.
and a selection section that alternately selects the data output from both the first shift path section and the second shift path section once per cycle of the clock. Shift path control circuit.