JPH04196921A - Initializing method for asynchronous counter circuit - Google Patents

Abstract

PURPOSE:To easily execute an initial setting at all times by providing a first set value writing means and second-Nth set value writing means to write the counted values next to the set values of respective frequency divider circuits to the respective frequency divider circuit. CONSTITUTION:Control information is inputted from the outside to a first set value writing means 2-1 in a first step and initially set, and the initially set value is written to a first frequency divider circuit 1-1 in the first step directly. In respect to second-Nth frequency divider circuits (1-2)-(1-n) subsequent to the second step, according to the control information, the outputs of the first-(N-1)th frequency divider circuits (1-1)-(n-1) in the preceding steps to be used for respective frequency divider circuits (1-2)-(1-n) are held in first (3-1)-(N-1)th state holding means 3-(n-1). Then, the counted values next to the set values of the second-Nth frequency divider circuits (1-2)-(1-n) are respectively written. Therefore, any initial value can be initially set from the synchronous frequency divider circuit designed without considering initialization.

Description

[Detailed Description of the Invention] [Summary] Regarding the initial setting method of an asynchronous counter circuit, to easily perform initial setting of any initial value from an asynchronous counter circuit designed without considering the initial setting. In order to provide a counter circuit that can perform A first set value writing means for directly writing a set value, and a second frequency dividing circuit to the Nth stage from the second stage onwards.
The frequency divider circuit retains the control information until the next count with the output from the previous stage used in each frequency divider circuit, and the count value next to the set value in each frequency divider circuit is sent to each frequency divider circuit. The configuration includes second setting value writing means to Nth setting value writing means.

[Industrial application field]

The present invention relates to a counter initialization method for initializing an asynchronous counter circuit.

[Conventional technology]

FIG. 4 is a diagram showing an example of writing the set value of the counter circuit. (A) and (B) are examples of writing the set value to the counter circuit with "HI+", and (C) and (D) are examples of writing the set value to the counter circuit. This is an example in which the setting value is written in "Lo". In the figure, 41 is a flip-flop (hereinafter referred to as FF) as a counter circuit;
2 is a logical sum operation circuit (hereinafter referred to as OR), 43 and 44 are input signal inversion output circuits (hereinafter referred to as INV), and 45 is a logical product operation circuit (hereinafter referred to as AND). be.

In figure (A), calculate the logical sum of "H" of the data (hereinafter referred to as D) and "H" of the control information of the setting value (hereinafter referred to as F) using 0R42, and write the logical sum value. F as a signal
In addition to the D terminal of F41, punch out with clock C and hold it, and at the timing of the next clock C, the positive polarity terminal Q
(hereinafter referred to as the Q terminal) reads the signal ■ with the "H" portion of D and F set to "H11". Also, in figure (B),
The logical product of the output obtained by inverting the "H" of D by the INV43 and the output obtained by inverting the "H" of F is determined by the AND45, and the logical product value is added to the FF41 as a write signal, and is punched and held by the clock C. At the timing of the next clock C, a signal ■ with the "H" portions of D and F set to "°H" is read from the negative polarity terminal #IQ (hereinafter referred to as *Q terminal).

Similarly, in Figure (C), the AND value of the inverted signals of D and F is applied to the D terminal as a write signal to the FF41, and from the terminal Q, the L' of D and the H of F are set as "Lo". Read out the signal ■.

In addition, in figure (D), the “Lo” part of D and the “H” part of F are
” is read from the terminal *Q. In the following, examples of counter circuits using the circuits shown in FIGS. 4(A) to 4(D) are shown in FIGS. 5 and 6.

FIG. 5 is a diagram showing a circuit of a conventional example, and is a circuit diagram of an asynchronous counter designed without considering initial settings. Further, FIG. 6 is a diagram showing a time chart of a conventional example circuit.

In FIG. 5, 1-1 is a synchronous first frequency divider circuit that uses the reference signal of this circuit as a clock, and 1-2 is a first frequency divider circuit 1.
This is a synchronous second frequency dividing circuit that uses the -1 output as a clock. Further, l-3 is a synchronous third frequency dividing circuit whose clock is the output signal of the second frequency dividing circuit 1-2. By using the output signals of the first frequency divider circuit Ll and the second frequency divider circuit 1-2 as clocks for the next-stage synchronous frequency divider circuit, a 6X6X3=108 asynchronous frequency divider circuit is formed. ing.

11 to 13 are FFs that use the input reference signal as a clock, and 11 is a third FF that corresponds to the circuit shown in FIG. 4(A). A third FF 13 corresponds to the circuit shown in FIG. 4(D). F
F, 13 is a third FF that combines the operations of FFII and FF12. Furthermore, the first N0R115 is an inverted OR operation circuit which receives the negative output of the second FF 12 and the positive output of the third FF 13 as input, and the first N0R 115 is an OR operation that inputs the positive output of the first FFII and the first NOR 14. This is the first OR of the arithmetic circuit, and these 11-15 form the above-mentioned synchronous divide-by-6 circuit 1-1. Similarly, 21-23
are circuits that operate in the same way as the first FFII to third FF13, and 24 is the fourth FF to sixth FF whose clock is the output signal of the first FFII, which is the output of the first frequency dividing circuit 1-1. The second N inputs the outputs of FF22 and sixth FF23.
0R125 is a second OR which inputs the outputs of the second N0R24 and the fourth FF21, and these 21 to 25 form a synchronous divide-by-six circuit. Furthermore, 31 and 32 are FF12
The seventh FF has almost the same operation as the seventh FF whose clock is the output of the fourth FF 21, which is the output of the second frequency dividing circuit 1-2.
and the eighth FF, 33 are third ORs which receive the respective negative polarity outputs of the seventh FF 31 and the eighth FF 32, and these 31 to 33 form a synchronous three-frequency divider circuit.

In Figure 6, (a) is the reference signal that becomes the clock of this circuit, Φ) is the reset signal of this circuit, (C), (dL
(e) shows a first FFII, a second FF12, . Third F
This is the positive polarity output of F13, and corresponds to the six-frequency divided output of the reference signal (a). Note that the signals (c), (i), and (j) are the signals of the fourth FF2L and the fifth F that are provided in the second frequency dividing circuit 1-2 using the output signal (C) of the first frequency dividing circuit Ll in the previous stage as a clock.
F22゜This is the positive polarity output of the sixth FF23, and the reference signal (
This corresponds to the 6×6=36 frequency-divided output in a). Also at the signal)
and signal (n) are the 7th F of the synchronous third frequency dividing circuit whose clock is the output signal (c) of the previous third frequency dividing circuit 1-3.
It shows the positive polarity output of F31 and the eighth FF32, and the reference signal (
This corresponds to an asynchronous frequency dividing circuit that divides the frequency by 6×6×3=108 based on a).

The conventional example shown in FIG. 5 will be explained below with reference to FIG. 6.

When the clock, which is the reference signal (a) indicating the standard of this circuit, is input sequentially and the reset signal (b) is input as shown in FIG. 5, each time the reference signal (a) is input,
By shifting clock by clock, positive polarity output (C) and negative polarity output (Co) are generated at clock timing ■, (d) and (d゛) at timing ■, and (e) and (at timing ■).
e') is output from the first FFII to the third FF13, and the same operation is repeated thereafter. And this output (d″).

By feeding back (e) to the first NOR 14 and feeding back the output (e゛) to the first FF 1l, the output (C) of frequency division by 6 is obtained.
, (d).

(e) sends out. Next, the output of this frequency divider circuit 1=1 (C
) is input to the second frequency divider circuit 1-2 as a clock, then
The second frequency dividing circuit 1-2 operates in the same manner as the first frequency dividing circuit 1-1, and includes the fourth FF21 to the sixth FF23 to FIG.
The signals shown in (j) are sequentially output. Similarly, the signal (
6) and (n) are sequentially sent out from the third frequency dividing circuit 1-3 using h) as a clock.

In such a continuous counting circuit, for example, in the state where the set value is "8", that is, (A) at the second clock ■? From the time chart in Fig. 6, the signal state in the iN region is (C)' = 1, (d) = 1,
(e) = 0, and in region (B), (c) = 1.
(i) = 1°'U) = O, and in the region (C) = 1. (n)=0, and these are each F Fll
, 12, 13.21, 22, 23.31.32.

As mentioned above, in conventional asynchronous counter circuits, the counter circuit is simply reset without performing initial settings, so if you want to initialize the value, you must consider this at the counter circuit design stage. No.

[Problem to be solved by the invention]

- Therefore, the counter circuit designed once is not versatile with respect to the initial value. In other words, if the initial value changes, the counter circuit must be designed again taking that value into consideration, which leads to loss of time in the design and There is a problem in that the circuit size increases.

An object of the present invention is to provide an asynchronous counter circuit that can be easily initialized to any initial value from an asynchronous counter circuit designed without consideration of initial settings.

[Means for solving problems]

In order to achieve the above object, the present invention provides an asynchronous counter circuit consisting of an N-stage first frequency divider circuit 1-1 to an N-th frequency divider circuit 1-n, each of which is synchronized. a first set value writing means 2-1 that directly writes a set value to the first frequency divider circuit 1-1 in the first stage, and second frequency divider circuits 1-2 to Nth frequency divider circuit 1- in the second and subsequent stages. n holds the control information until the next count in the output from the previous stage used in each frequency dividing circuit 1-2 to 1-n, and each frequency dividing circuit 1-2
~Second set value writing means 2-2~ for writing the next count value of the set value at I-n into each frequency dividing circuit 1-2~1-n.
It is constituted by the Nth setting value writing means 2-n.

In addition, in the second frequency dividing circuit l-2 to the Nth frequency dividing circuit 1-n in the second and subsequent stages, each of the frequency dividing circuits 1-1 to 1-(n-1
) as the clock input, and the data input as “H”
``Input the control information to the reset terminals of the first state holding means 3-1 to the N-1st state holding means 3-(n-1) to be fixed, and make the negative polarity output the control information input. Configure.

[For production]

In the present invention, as shown in FIG. 1, in an asynchronous counter circuit composed of an N-stage first frequency divider circuit Ll to an N-th frequency divider circuit 1-n, each of which operates synchronously, control information from the outside is used. is input into the first stage's first set value writing means 2-1 for initial setting, and the initial set value is written directly to the first stage's first frequency dividing circuit 1-1. For the second frequency divider circuit 1-2 to Nth frequency divider circuit 1-n, the first frequency divider circuit 1-n of the previous stage used in each frequency divider circuit 1-2 to 1-n is
The outputs of the 1st to N-1th frequency dividing circuits 1-(n-1) are controlled by the first state holding means 3-1 to 3-1 according to the control information until the next count.
The N-1 state holding means 3-(n-1) is configured to hold the count value next to the set value in each of the second frequency dividing circuit 1-2 to N-th frequency dividing circuit 1-n. There is.

Therefore, a desired initial setting value is written in the first setting value writing means 2-1, and a value next to the initial setting value is written in the second frequency dividing circuit 1-2 to the Nth frequency dividing circuit 1-n. It is possible to construct an asynchronous counter circuit in which .

〔Example〕

FIG. 2 is a diagram showing a circuit according to an embodiment of the present invention;
The figure is a diagram showing a time chart of a circuit according to an embodiment of the present invention. Note that FIG. 3 shows a case where the initial setting -"8" is applied by inputting control information in the asynchronous counter designed without considering the initial settings shown in FIGS. 5 and 6.

In FIG. 2, Ll is a first frequency divider circuit of synchronous frequency division by six using the clock signal of this circuit as a clock, and includes the first FFII to third FF13, first NOR14, first 0R15, and main frequency divider circuit of the conventional circuit. The first set value writing means 2 to 1 of the invention are provided with an 11th OR 16 to a 13th OR 1B. Also 1-
Reference numeral 2 denotes a second frequency dividing circuit of synchronous frequency division by six using the output signal of the first frequency dividing circuit 1-1 as a clock, and the fourth F of the conventional circuit.
F21~6th FF23, 2nd N0R24, 2nd 0R25
and a first set value writing means 2-2 of the present invention.
40R26 to 160R28 and first state holding means 3-1
Equipped with a corresponding ninth FF29.

In addition, 1-3 is a synchronous 3-3 frequency divider circuit that uses the output signal of the second frequency divider circuit 1-2 as a clock, and is a synchronous 3-3 frequency divider circuit that uses the output signal of the second frequency divider circuit 1-2 as a clock. 170R34 and 180R35 corresponding to the third setting value writing means 2-3 of the invention and the tenth F corresponding to the second state holding means 3-2.
Equipped with F36. These are similar to FIG. 5, in which the output signals of the synchronous first frequency dividing circuit Ll and second frequency dividing circuit 1-2 are divided into the next synchronous type second frequency dividing circuit 1-2 and third frequency dividing circuit, respectively. By using it for the clock of circuit 1-3, 6X6X3=1
08 asynchronous type 108 frequency divider circuit is formed.

FIG. 3 is a time chart showing the operation of FIG. 2, with signals (a), (bL (C), (d), (d'), (
e), (e'), (f), (g) and wholesale, (i), (+
'), C+L(j'), Ck)'+ (f) and )
, (m')(n), (n'), (0), and (r), (q), (r) indicate the output of each circuit at each point in the circuit of Fig. 2, and the signal ( b),
(d'), (e), ge), (scent (i'), (j)
, (b), (1), (m"), (n"), and (0) are not shown in FIG. The signal -) is the control information for initializing this circuit, the signal (b) is the negative polarity output of the ninth FF 29 reset by the control information Φ), and (r) is the control information reset by the control information (p). This is the negative polarity output of the tenth FF 36.

Assume that the control information is inputted as shown in FIG. 3(p) and reset at a timing determined by a signal Φ (not shown). Since the initial setting value is "8", it corresponds to the eighth clock, that is, ■, and from the time chart in Figure 6, (C) = 1, (d) - 1, (e) - 〇, (h )=
1, (i)=1, (j)=0, (m)-1, (n)=
It can be seen that 0 is the counter value "8". Therefore, each F FIL12.1 of the first frequency dividing circuit 1-1 shown in FIG.
The initial setting values for 3 are (C) = 1, (d) = 1, (e) =
Since it only needs to be 0, for (C)-1 and (d) = 1, the control information (P) is used as it is for the 110R16 and 12th
0R17, and in the 110R16, the logical sum of the control information Φ) and the positive output (e) of the third FF13 is taken, and in the 120R17, the control information φ) and the first 0
The output of R15 is logically summed with the output (d). For (e) = 0, the negative polarity output (d゛) of the second FF12 and the control information Φ
), and the third FF13 outputs "0", which is the inverted polarity of the output from the 130th R18. Also, by doing this, the third FF13
Since the polarity of the output pattern of the FF12 is reversed, the output polarity of the second FF12, which is the data input light, is reversed and the output pattern of the first NOR is reversed.
14 and 110R16. The result of performing the above is shown in area (A), and this circuit is the first frequency dividing circuit 1-1 shown in FIG.

Next, (5) = 1, (i) - 1, (j) = 0, but this synchronous type second frequency divider circuit 1-2 directly receives the clock signal (a) targeted by this circuit. Since it is an asynchronous frequency divider circuit that uses the output from the previous stage without using
-Cannot perform the same operation as the third FF13. Therefore, the output (C) at timing ■ of the first frequency dividing circuit 1-1 in the previous stage, which is the clock of the second frequency dividing circuit 1-2, is sent to the ninth FF 29 whose one input terminal is fixed at "H". The control information Φ) is used to generate an output (q) in which the value at timing (3) of the output (c) is held until the next rising edge, and initialization is performed. Also, by doing so, the initial setting value is changed to the next value of timing ■, that is, (h
)-1, (i)=1, (j)=1. That is, in response to the input of the control information Φ), the ninth FF 29 outputs the output (q) shown in FIG. 3, and this signal (q) is sent to the fourth FF 21, fifth FF 22 . 6th F
When applied to F23, it becomes the second frequency divider circuit 1-2 shown in FIG. 2, and the output (5) shown in area (B) of FIGS. 2 and 3,
Outputs such as (i) and (j') are obtained.

Similarly, for the third frequency divider circuit 1-3 in FIG. 5, the initial setting values of (m)-1, (n)=O of timing )=L(n)
When the initial setting is set to 1, the third frequency dividing circuit 1-3 shown in FIG. 2 is obtained.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is possible to initialize any initial value from an asynchronous frequency divider circuit designed without considering initial settings, thereby reducing design time and circuit scale. This has the effect of making it possible to reduce the size of the device.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle configuration of the present invention, Fig. 2 is a diagram showing a circuit of an embodiment of the invention, Fig. 3 is a diagram showing a time chart of an embodiment of the circuit of the invention, Part 4 FIG. 5 is a diagram showing an example of writing a setting value of a counter circuit; FIG. 5 is a diagram showing a circuit of a conventional embodiment; FIG. 6 is a diagram showing a time chart of a conventional circuit. In the figure, 1-1 = 1-n is the first frequency dividing circuit to the Nth frequency dividing circuit, 2-
1 to 2-n are first set value writing means to Nth set value writing means, 3-1 to 3-(n-1) are first state holding means to N-1th set value writing means.
A state holding means is shown. Agent Patent Attorney Sada Igata − Gin・Eishichito
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Claims (1)

[Claims] [1] N stages of first frequency dividing circuits (1-1), each of which is synchronized
In an asynchronous counter circuit consisting of an N-th frequency divider circuit (1-n), the first frequency divider circuit (1-1
) for directly writing the set value into the first set value writing means (2-1
), and the second frequency divider circuit (1-2) to the Nth frequency divider circuit (
1-n) holds the control information until the next count with the output from the previous stage used in each frequency dividing circuit (1-2 to 1-n), and ~1-n) to each frequency dividing circuit (1-2 to 1-n).
An initial setting method for an asynchronous counter circuit, characterized in that a second set value writing means (2-2) to an Nth set value writing means (2-n) are provided. [2] In the second frequency divider circuit (1-2) to the Nth frequency divider circuit (1-n) in the second and subsequent stages, each frequency divider circuit (1-1 to 1
-(n-1)) as a clock input and data input fixed at "H" (first state holding means (3-1)~
The asynchronous according to claim 1, characterized in that the control information is inputted to a reset terminal of the N-1st state holding means (3-(n-1)), and a negative polarity output is used as the control information input. Initial setting method for equation counter circuit. [3] The asynchronous device according to claim (1), wherein “H” is written by inputting the logical sum of the control information to each data input of the frequency dividing circuit (1-1 to 1-n). Initial setting method for equation counter circuit. [4] The asynchronous device according to claim (1), wherein “L” is written by logically inputting the control information to each data input of the frequency dividing circuit (1-1 to 1-n). Initial setting method for equation counter circuit. [5] Write "H" by inputting the logical product of the control information to the polarity of each data input of each of the frequency dividing circuits (1-1 to 1-n) and inverting the output. The initial setting method for an asynchronous counter circuit according to claim 1, characterized in that: [6] Write "L" by inputting the logical sum of the control information to the polarity of each data input of the frequency dividing circuit (1-1 to 1-n) and inverting the output. An initial setting method for an asynchronous counter circuit according to claim (1).