JPH05143752A - Automatic initial setting data reading circuit - Google Patents

Abstract

PURPOSE:To obtain the automatic initial setting data reading circuit for using an LSI adopting a bus system for the write of an internal register even in a system without a CPU. CONSTITUTION:With the outputs of even-number steps and the outputs of odd- number steps from a shift register 16 to fetch system clocks, a flip-flop 21 is set or reset through OR circuits 23 and 24. A binary counter 22 inputs a signal having a phase inverse to the output of the flip-flop 21. Corresponding to the state of an automatic read setting signal, either a WR signal inputted from the outside or the output of the flip-flop 21 is selectively read into a register 25 in the LSI.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit in which initial setting data is automatically read from the outside in an LSI of a system in which initial data is externally set to a register inside the LSI in order to improve versatility. Regarding

[0002]

2. Description of the Related Art In an LSI, when importance is attached to versatility, a recorder for writing data from outside (hereinafter referred to as a register) is provided inside the LSI, and data can be written at the time of initial setting to operate the LSI. is there. For example,
When a timer circuit is provided inside the LSI, normally, the set value of the timer is fixed inside the LSI and cannot be changed from the outside, but it is possible to set it from the outside by providing a register. With this structure, even if the set value is changed due to the system change, the L
It can be handled without recreating SI. In this case, there are often a plurality of registers to increase versatility, and in extreme cases, all variable elements of the LSI (set values of counter / timer, shift values of shift register, etc.) are set by the registers. It is possible to have a system with complete versatility. In the case of having a plurality of registers, there is a method of setting external pins as many as the number of registers as a method of setting data from the outside, but the number of pins is so large that it is not practical and is not often done. Generally, a method is adopted in which a bus (address bus, data bus) is provided in the LSI and data is written. In this system, L
It is assumed that SI is used in a system including a CPU. FIG. 4 shows a configuration for writing data to the register. In the figure, a CPU 1 is a ROM 3 via a bus 2.
Read one setting data from the LSI to the LSI 4 and write the data to the register of the LSI 4 via the bus 2. Further, the next data is read from the ROM 3 and written in the LSI 4. This operation is repeated to write to the register.

[0003]

However, in this way, L
If the bus method is used for writing SI registers, C
It has the drawback that it cannot be used in systems without a PU. The LSI that should be used for system miniaturization is C
There is a contradiction that it cannot be used in a small system without a PU.

It is an object of the present invention to make it possible to use the above-mentioned bus-based LSI for writing registers in a system having no CPU.

[0005]

In order to achieve the above object, an initialization data automatic reading circuit of the present invention takes in a system clock, has a shift register having a plurality of output stages, and an even number stage including the first stage of the shift register. A first OR circuit for inputting an output, a second OR circuit for inputting an odd-numbered output of the shift register, and a flip-flop for inputting the outputs of the first and second circuits to set and reset terminals, respectively. , A counter for inputting a signal having a phase opposite to that of the output of the flip-flop, a register in the LSI having input ports for writing, address, and data, and externally input according to the state of the automatic read setting signal First signal selecting means for selectively supplying the write signal and the flip-flop output to the write input port of the register Depending on the state of the automatic reading setting signal, the address signal externally input to the address terminal and the counter output are selectively supplied to the counter input port of the register, and the output of the counter is selected. And a second signal selecting means for supplying the output to the address terminal.

[0006]

The register in the LSI can automatically read the initial setting data from the outside at the time of resetting without using the CPU.

[0007]

Embodiments of the present invention shown in the drawings will be described below.
FIG. 1 shows an embodiment of a circuit for automatically reading initial setting data to a register inside an LSI according to the present invention. In the figure, 10 is a system clock input terminal, 11 is a reset input terminal, 12 is an automatic read setting terminal, 13 is a write (WR) signal input terminal, 14 is an address bus input / output terminal, and 15 is a data bus input / output terminal. 1
6, 19 and 20 are three-state buffers, 17 is a bidirectional bus buffer, 18 is an inverter, 21 is a set / reset flip-flop, 22 is a counter, 2
3, 24 are OR circuits, 25 are registers inside the LSI, 2
6 is a shift register.

Note that this embodiment is an example in which there are four registers of 8-bit data, and it is necessary to change the number of stages of the shift register 26 and the number of input terminals of the OR circuits 23 and 24 depending on the number of registers. In FIG. 1, the terminal 10
1 to 15 are input / output pins of the LSI. The automatic read setting terminal 12 is fixed to the "H" level when the LSI is used in a system having no CPU, and the system output having the CPU is fixed to the "L" level.

First, the case of fixing to "H level", that is, the case of a system having no CPU will be described. In this case, the three-state buffer 16 is closed and the three-state buffer 19 is opened. As a result, the input to the WR port of the register 25 is given from this circuit inside the LSI. Also, bidirectional bus buffer 1
7 is controlled in the output direction when viewed from the LSI, and the three-state buffer 20 is opened, so that the address created by this circuit is input to the address of the register 25 and is output to the outside from the address bus 14. As shown in FIG. 3, this address bus is connected to the address of the external ROM, and the data bus 15 is connected to the data of the external ROM. As for the signal flow, the reset terminal 1 is first
A reset signal is input to 1. In this case, the reset signal needs to be in synchronization with the system clock input to the terminal 10 and at the “H” level for a period of two cycles of the system clock. The outputs Q0 to Q7 of the shift register 26 upon inputting the reset signal are shown in FIG. In FIG. 1, Q0, Q2 of 26 shift register outputs
Q4 and Q6 are input to the respective input terminals of the 4-input OR circuit 23, and set / reset flip-flop 21 is set at the rising edge of each output pulse. The outputs Q1, Q3, Q5, Q7 of the shift register 26 are input to the respective input terminals of the 4-input OR circuit 24, and the set / reset flip-flop 21 is output at the rising edge of each output pulse.
Set. The output of the set / reset flip-flop 21 becomes the data write signal WR of the register 25, and its waveform is shown in FIG. The signal obtained by inverting the write signal WR is the binary counter 22.
Is input to the CLK terminal of the
2 is counted up. The output of the counter 22 is output to the address of the register 25 and the address bus 14 (external pin) of the LSI. As shown in FIG.
Since the SI address bus 14 is connected to the address bus of the external ROM, the external ROM outputs the data of the address to the data bus 15. This data is LSI
1 is input as data to the register 25 of FIG. Then, the data is read at the rising edge of the WR signal of the register 25. In terms of timing, as shown in FIG. 2, the write signal (WR) is output when the counter value is completely stable. At this point in time, the data from the external ROM has also been determined, so writing of data to the register 25 is reliably performed.

The output of Q7 of the shift register 26 is also used as the clear signal of the binary counter 22 of FIG. 1, and when the writing to the register 25 is completed, the counter 22 is cleared. The output of Q7 is also used as a reset signal for the internal circuit of the LSI. As described above, the data is written to the register 25 between the input of the reset signal from the outside of the LSI and the actual output of the reset signal to the inside of the LSI. Next, the case where the automatic reading terminal 12 of FIG. 1 is fixed to the "L" level will be described. In this case, the three-state buffer 16 is opened and the three-state buffers 19 and 20 are closed. Further, the bidirectional buffer 17 is controlled in the input direction when viewed from the LSI. As a result, the address and WR signals are C as in the case of FIG.
Since it is given from PU, the address and WR signal generated by this circuit are ignored. The reset signal given to the internal circuit of the LSI is the automatic read setting terminal 12
Are output at the same timing as when they are fixed to the "H" level.

[0011]

As described above, according to the present invention, an LSI that uses the bus system for writing the internal register is
It can be used in a system that does not have a PU, which helps reduce the system size.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the above embodiment.

FIG. 3 is a block diagram for explaining the operation of the above embodiment.

FIG. 4 is an explanatory diagram of a method of reading initial setting data into a register in a conventional LSI by a bus method.

[Explanation of symbols]

 10 system clock input terminal 11 reset input terminal 12 automatic read setting terminal 13 WR signal input terminal 14 address bus input / output terminal 15 data bus input / output terminal 16, 19, 20 three-state buffer 17 bidirectional bus buffer 21 set reset flip-flop 22 binary counter 23, 24 4 input OR circuit 25 register 26 shift register

Claims (1)

[Claims] 1. A shift register having a plurality of stages of outputs which takes in a system clock, a first OR circuit which inputs an even number stage output including a first stage of the shift register, and a first OR circuit which inputs an odd number stage output of the shift register. 2 OR circuit, a flip-flop for inputting the outputs of the first and second circuits to the set and reset terminals, a counter for inputting a signal of an opposite phase to the output of the flip-flop, a writing and address , A register in the LSI having each data input port, and a write signal externally input according to the state of the automatic read setting signal and the flip-flop output are selectively supplied to the write input port of the register. According to the state of the first signal selection means and the automatic read setting signal, an address input from the outside to the address terminal is input. Second signal selecting means for selectively supplying the response signal and the counter output to the counter input port of the register and also supplying the output to the address terminal when the output of the counter is selected. An initial setting data automatic reading circuit characterized by including