JPH08287674A - Continuous access memory - Google Patents

Abstract

PURPOSE: To provide a continuous access memory capable of constituting a system eliminating an address generation circuit in the periphery of the memory required in a conventional memory and easily and continuously accessing address. CONSTITUTION: This memory is provided with a memory cell array 101, a sense amplifier and a write control circuit 102. The memory is provided with shift registers 107-110 of a synchronous type of the number of bits corresponding to the number of word lines 103-106 to the memory cell array 101. Then, parallel output lines of the shift registers are connected to the word lines of the memory cell array 101, and when a start signal EN is inputted to the series input of the shift register, the word lines 103-106 are activated successively synchronizing with a clock CLK controlling the shift registers, and the data stored in the memory cell array are read out, or the data are written in the memory cell continuously synchronizing with the clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, particularly to a memory built in a semiconductor chip and a system using the memory.

[0002]

2. Description of the Related Art As shown in FIG. 10, the structure of a conventional memory is mainly composed of a memory cell array 1001, a sense amplifier and write control circuit 1002, and an address decoder 1007. This memory is a 4 bit × 4 word memory and has an address input terminal (A0, A1), a write control signal input terminal (WE) for controlling writing or reading, and a data port input / output terminal. Address input terminal (A
0, A1) is input to the address decoder 1007,
The address decoder activates one of the four word lines 1003 to 1006 connected to the memory cell array 1001 corresponding to the input address input. The memory cell array stores the state of the data added to the data port or activates the data port through the sense amplifier and the write control circuit 1002 depending on the state of the four word lines and the state of the write control signal. It outputs the data of the memory cell stored in the word.

The timing of the memory access operation will be described with reference to FIG. Figure 11 shows the case of reading,
Address (Adrs) is changed from "00" to "0" in synchronization with the clock (CLK).
The data is continuously supplied in the order of 1 "→" 10 "→" 11. "The word line is activated sequentially and the data is output continuously in response to the change of the address. Addresses are continuously supplied to access the data.

In the system for performing the signal processing operation shown in FIG. 12, the data to be operated is stored in the memory 1201, the data processing device 1203 performs the processing, and the processing result is stored in the memory 1202. At this time, the data processing device 1
The data is supplied to 203 by the data continuously read from the memory 1201 by the address generated by the address generator 1204 in synchronization with the clock (CK).
The data resulting from the continuous processing by the data processing device 1203 is continuously written into the memory 1202 by the address generated by the address generator 1205 in synchronization with the clock (CK).

[0005]

In the system for performing the signal processing operation as described above, the data to be operated is stored in the memory,
When storing the calculation result in the memory, the address is often accessed continuously, and when the conventional memory is used, the circuit of the address generator including the counter that continuously generates the address around the memory is used. You will need it.

It is an object of the present invention to provide a memory which can easily configure the system as described above by eliminating circuits around the memory.

[0007]

According to a first aspect of the present invention, in a memory including a memory cell array, a sense amplifier and a write control circuit, a synchronous shift of the number of bits corresponding to the number of word lines to the memory cell array is provided. A register is provided, a parallel output line of the shift register is connected to a word line of the memory cell array, and when a start signal is input to a serial input of the shift register, the word line is sequentially synchronized with a clock for controlling the shift register. The continuous access memory is characterized in that it is activated and reads data stored in the memory cell array or writes data to the memory cell array continuously in synchronization with the clock.

A second invention is a memory including a memory cell array, a sense amplifier and a write control circuit,
A plurality of synchronous shift registers are provided, the parallel output lines of the shift registers are connected to the word lines of the memory cell array, and when the start pulse signal is input to the serial input of one shift register, the shift registers are connected. The word lines are sequentially activated in synchronization with the clock for controlling the shift register, and reading of data stored in the memory cell array or writing of data in the memory cell array is continuously performed in synchronization with the clock. It is a continuous access memory characterized in that

A third aspect of the present invention is a memory provided with a memory cell array, a sense amplifier, and a write control circuit.
A pair of synchronous shift registers, a parallel output line of each shift register of the first set is connected to a word line of the memory cell array, and a parallel output line of each shift register of the second set is a bit line of the memory cell array. Connected to a control line of a bit line selection circuit for selecting, shift clocks are input to the shift registers, and a start pulse signal is input to the serial input of the shift registers, the shift registers are connected. Existing word lines are sequentially activated in synchronization with a clock, and the bit line selection circuit sequentially reads data stored in the memory cell array or writes data in the memory cell array in synchronization with a clock. It is a continuous access memory which is characterized in that

A fourth invention is a memory including a memory cell array, a sense amplifier, and a write control circuit, and a synchronous shift register having a bit number corresponding to the number of word lines to the memory cell array, and the shift register. Has parallel output lines corresponding to all the bits connected to the word lines of the memory cell array, and the inputs of all the flip-flops forming the shift register correspond to the outputs of the previous flip-flops and the number of word lines. A logical OR with an activation signal from the outside is input, a common initialization signal from the outside is input to the initial value input of the flip-flop, and a clock to access any one activation signal input of the shift register When a start signal that is asserted for the number of words in the cycle is input, the word line is used as the clock. When the activation signal inputs are negated, the flip-flops are initialized by using the initialization signal so as not to activate the word line, A continuous access memory characterized in that reading of data stored in the memory cell array or writing of data to the memory cell array can be continuously accessed from an arbitrary number of data in synchronization with the clock. is there.

[0011]

According to the first aspect of the present invention, when the activation signal is input, the parallel outputs of the shift register composed of flip-flops are sequentially activated every cycle, and the word lines of the memory cell array are sequentially activated every cycle. By doing so, continuous access is realized.

The second invention realizes continuous access like the first invention, but since a plurality of shift registers are provided, the range of continuous access can be divided.

The third aspect of the present invention realizes continuous access like the first aspect of the present invention, but it can realize continuous access by including a bit line selection circuit.

The fourth aspect of the invention realizes continuous access as in the first aspect of the invention, but enables access of an arbitrary number of data from an arbitrary address.

[0015]

The following is a block diagram of an embodiment of the present invention,
This will be described with reference to the timing chart.

(Embodiment 1) FIG. 1 is a block diagram of a memory of a 4 bit.times.4 word structure according to the first embodiment of the present invention. This memory has a write control signal input for controlling writing or reading. It has a terminal (WE) and a data port input / output terminal. The main components of this memory are a memory cell array 101 of 4 bits × 4 words, a sense amplifier and write control circuit 102, and flip-flops 107 to 110 that form a synchronous shift register.

The outputs of the flip-flops 107 to 110 are passed through the buffers 111 to 114 to the memory cell array 1
At the same time as being connected to the four word lines 103 to 106 of 01, the output of the flip-flop 107 is connected to the input of the next flip-flop such as to the input of the flip-flop 108. The input of the flip-flop 107 in the first stage becomes the input terminal of the activation signal (EN). A clock signal (CLK) is commonly input to each of the flip-flops 107 to 110, which constitutes a synchronous shift register. Memory cell array 1
01 indicates the state of the data added to the data port (D0, D1, D2, D3) through the sense amplifier and the write control circuit 102 depending on the state of the four word lines 103 to 106 and the state of the write control signal. Store or output the data of the memory cell stored in the active word to the data port.

A case where the timing of the memory access operation of the present embodiment is read out (when the write control signal is in the negate state) will be described with reference to FIG. Clock (CLK)
When a start signal (EN) for one cycle is input to the memory of the present embodiment, the parallel output of the shift register constituted by the flip-flops 107 to 110 (that is, the flip-flops 107 to 110) in synchronization with the clock (CLK). The output of 110) sequentially becomes active every cycle, and the word lines (w.lone0-3) of the memory cell array 101 are sequentially activated every cycle. The data stored in the memory cells connected to the activated word line is sequentially transferred to the data port through the sense amplifier and the write control circuit 102 by sequentially changing the data of the memory cells stored in the active word to 1 by one.
Output in cycle.

Also, in the case of writing to the memory of this embodiment (when the write control signal is in the asserted state), similarly, the word line is sequentially activated by the activation signal (EN), and every one cycle of the clock (CLK). The state of the data port is written in the memory cell array.

FIG. 9 shows a system configuration diagram using the memory of the first embodiment. Data to be calculated is stored in the memory 901, processed by the data processing device 903, and the processing result is stored in the memory 902. At this time, the data is supplied to the data processing device 903 by the data continuously read from the memory 901 by the activation signal generated in synchronization with the clock (CK). The data resulting from the continuous processing by the data processing device 903 is continuously written into the memory 902 by the activation signal generated in synchronization with the clock (CK).

In the present embodiment, the case of a 4-word area has been described, but the number of words can be set arbitrarily and can be configured by changing the number of bits of the shift register.

(Embodiment 2) FIG. 3 is a block diagram of a memory of a 4 bit × 8 word structure according to a second embodiment of the present invention, which is a memory cell array 301 of 4 bit × 8 words, a sense amplifier and a write control circuit. 302, flip-flops 311 to 311, which constitute two synchronous shift registers
4, 315 to 318 are the main constituent elements.

The outputs of the flip-flops 311 to 314 constituting the first synchronous shift register are the buffer 31.
9 to 322 to the four word lines 303 to 306 of the memory cell array 301, and at the same time, the output of the flip-flop 311 is connected to the input of the next flip-flop such as to the input of the flip-flop 312. Has been done. The input of the flip-flop 311 in the first stage becomes the input terminal of the activation signal (EN0). Similarly, a flip-flop 31 that constitutes a second synchronous shift register
The outputs of 5 to 318 are transmitted through the buffers 323 to 326 to the four word lines 307 to 31 of the memory cell array 301.
Flip-flop 315 connected to 0
Is connected to the input of the next stage flip-flop, such as to the input of flip-flop 316. The input of the flip-flop 315 in the first stage is a start signal (EN
It becomes the input terminal of 1). Therefore, each of the flip-flops 311 to 314 and 315 to 318 receives the clock signal (CL
K) is commonly input, and two synchronous shift registers are configured. Memory cell array 301
Depends on the state of the word line and the state of the write control signal,
The state of the data added to the data port (D0, D1, D2, D3) is stored through the sense amplifier and the write control circuit 302, or the data of the memory cell stored in the active word is stored in the data port. Output.

The operation of the memory of this embodiment divides the access of the memory cell array 301 by asserting only one of the two activation signals (EN0, EN1),
The access (writing or reading) is continuously performed as in the first embodiment.

In the present embodiment, the case where the 8-word area is divided into 4 words × 2 has been described. However, the division method can be set arbitrarily by the configuration of the shift register.

The memory of this embodiment can also have a system configuration similar to that shown in FIG. (Third Embodiment) FIG. 4 is a block diagram of a memory according to a third embodiment of the present invention, which is a memory cell array 401 of 16 bits × 4 words, a sense amplifier and a write control circuit 40.
Two or two flip-flops 407 to 410 and 415 to 418 forming a synchronous shift register, and a selection circuit 419 for selecting one bit line pair from the four bit line pairs (b, b) of the memory cell array 401. Is the main component.

The outputs of the flip-flops 407 to 410 constituting the first synchronous shift register are the buffer 4
The output of the flip-flop 407 is simultaneously connected to the four word lines 403 to 406 of the memory cell array 401 via 20 to 423.
It is connected to the input of the next stage flip-flop and so on. The input of the flip-flop 407 in the first stage serves as the input terminal of the activation signal (EN-R).

Similarly, the outputs of the flip-flops 415 to 418 forming the second synchronous shift register are connected to the four control lines 411 to 414 of the bit line selection circuit 419 via the buffers 424 to 427. At the same time, the output of flip-flop 415 is connected to the input of the next-stage flip-flop, such as to the input of flip-flop 416. First stage flip-flop 4
The input of 15 becomes an input terminal of a start signal (EN-C). First
Flip-flops 407 to form a shift register
410 and the flip-flops 415 to 418 of the second shift register are inputted with the clock signals (CLK, CLK4) of different frequencies which are synchronized with each other, which means that two sets of synchronous shift registers are constituted. . CLK4 operates as shown in the timing chart of FIG. 5 when the CLK divided by 4 is input.

The case of reading the operation of the memory of this embodiment (when the write control signal is in the negate state) will be described with reference to FIG. When the activation signal (EN-C) for one cycle of the clock (CLK) is input to the memory of this embodiment, the flip-flops 415 to 418 are synchronized with the clock (CLK).
The parallel output of the second shift register (that is, the outputs of the flip-flops 415 to 418) sequentially becomes active for each cycle, and the control line (control lines 0 to 3) of the bit line selection circuit 419 sequentially operates for one cycle. Each is activated. The bit line selected by the activated control line is the memory cell array 401, the sense amplifier, and the write control circuit 4.
02 are electrically sequentially connected to one cycle child.

When a start signal (EN-R) for one cycle of the clock (CLK4) is input to the memory of this embodiment, the flip-flops 407 to 410 are synchronized with the clock (CLK4).
The parallel output of the first shift register (that is, the outputs of the flip-flops 407 to 410) is sequentially activated every cycle, and the word lines (w.lone0-3) of the memory cell array 401 are sequentially activated every cycle. Be converted.
In the case of FIG. 5, CLK4 is the CLK divided by 4, and the start signal (EN-R) and the start signal (EN-C) are asserted at the same time.
I am In this case, four bit line selection control lines are sequentially activated while one word line is activated. That is, all the data stored in the memory cell array 401 can be sequentially read in units of 4 bits. In the case of writing to the memory of this embodiment (when the write control signal is in the asserted state)
Also, similarly, it is possible to successively and sequentially perform in units of 4 bits.

Further, the memory of this embodiment can have a system configuration similar to that shown in FIG. In the case of the present embodiment, since the bit line selection was 4 to 1, CLK4 is obtained by dividing CLK by 4. However, if the bit line selection is n to 1, CLK4 is
CLK divided by n may be used.

(Embodiment 4) FIG. 6 is a block diagram of a memory of a 4 bit.times.8 word structure in a fourth embodiment of the present invention, which is a memory cell array 601 of 4 bit.times.8 words, a sense amplifier and a write control circuit. 602 and the synchronous shift register 612 are the main constituent elements.

FIG. 7 shows an internal structure of the shift register 612 and an example of peripheral circuits for using the memory of this embodiment. The internal structure of the shift register 612 includes the flip-flops 613 to 620 and the flip-flops 6
OR gates 621-connected to the inputs of 13-620
And 628. Each flip-flop 613-6
The outputs of 20 are connected to the eight word lines 603 to 610 of the memory cell array 601 via the buffers 633 to 640. The output of flip-flop 613 is connected to the input of the OR gate connected to the input of the next stage flip-flop, such as to the input of OR gate 622 connected to the input of flip-flop 614. The other inputs of the OR gates 621 to 628 are connected to external terminals (EN0 to EN7), and the clock inputs of the flip-flops 613 to 620 are all connected to a common external terminal (CLKin). Logic gates 630 to 632 shown in FIG. 7 are peripheral circuits necessary for using the memory of this embodiment.

When the memory of this embodiment is used, a clock pulse is input to the external terminal (CLKin) only when accessing. Also, input a start signal that is asserted for a time corresponding to the number of words in the clock cycle to access any one start signal input from the external terminals (EN0 to EN7). In FIG. 7, only three of the terminals (EN0, EN2, EN4) are externally connected. In other words, the external terminals (EN0 to EN7) for input of the flip-flop corresponding to the first word line that starts continuous access are continuously asserted for the number of words in the clock cycle to continuously output word lines. Is activated. A signal asserted when not accessing is input to the external terminal (EN), and initialization is performed so that no word line is activated when not accessing.

An example of access using the memory of this embodiment (when the write control signal is in the negate state) will be described with reference to FIG. First, EN-a (connected to EN0) is asserted for 4 cycles, so that the word lines (w.line0 to w.lin)
e3) is sequentially activated and four data are output.
Next, EN-b (connected to EN2) is asserted for 5 cycles, so that the word lines (w.line2 to w.line6) are sequentially activated and 5 data are output. There is. Furthermore EN-a
By asserting (connected to EN0) for three cycles, the word lines (w.line0 to w.line2) are sequentially activated and three data are output. Finally, EN-c (connected to EN4) is asserted for 2 cycles.
Lines (w.line4 to w.line5) are activated sequentially and two data
Is being output.

Further, the memory of this embodiment can also have a system configuration similar to that shown in FIG. Although the 8-word configuration has been described in the present embodiment, the n-word configuration can also be achieved by configuring the shift register with an n-bit configuration.

[0037]

According to the first to fourth aspects of the invention, circuits such as an address generator composed of a counter for continuously generating addresses around the memory are eliminated and the circuit is easily and compactly provided. A memory that can configure the system can be provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a memory according to a first embodiment of the present invention.

FIG. 2 is a timing chart of the memory in the embodiment.

FIG. 3 is a configuration diagram of a memory according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a memory according to a third embodiment of the present invention.

FIG. 5 is a timing chart of the memory according to the embodiment.

FIG. 6 is a configuration diagram of a memory according to a fourth embodiment of the present invention.

FIG. 7 is a configuration diagram of a shift register of a memory according to the same embodiment.

FIG. 8 is a timing chart of the memory in the embodiment.

FIG. 9 is a system configuration diagram using a memory according to the first embodiment of the present invention.

FIG. 10 is a block diagram of a conventional memory

FIG. 11 is a timing diagram of a conventional memory.

FIG. 12 is a system configuration diagram using a conventional memory.

[Explanation of symbols]

 101 memory cell array 102 sense amplifier and write control circuit 103-106 word line 107-110 flip-flop

Claims (4)

[Claims] 1. A memory including a memory cell array, a sense amplifier, and a write control circuit, comprising a synchronous shift register having a bit number corresponding to the number of word lines to the memory cell array, and the parallel output of the shift registers. Line is connected to a word line of the memory cell array, and a start signal is input to the serial input of the shift register, the word line is sequentially activated in synchronization with a clock controlling the shift register and stored in the memory cell array. The continuous access memory is characterized in that the reading of the stored data or the writing of the data into the memory cell array is continuously performed in synchronization with the clock. 2. A memory including a memory cell array, a sense amplifier, and a write control circuit, comprising a plurality of synchronous shift registers, wherein parallel output lines of each shift register are connected to word lines of the memory cell array. When an activation pulse signal is input to the serial input of one shift register, the word line connected to the shift register is sequentially activated in synchronization with the clock controlling the shift register, and the data stored in the memory cell array is stored. The continuous access memory is characterized in that the reading or writing of data to the memory cell array is continuously performed in synchronization with the clock. 3. A memory comprising a memory cell array, a sense amplifier and a write control circuit, comprising two sets of synchronous shift registers, wherein the parallel output lines of each shift register of the first set are word lines of the memory cell array. Connect with
A parallel output line of each shift register of the second set is connected to a control line of a bit line selection circuit that selects a bit line of the memory cell array, and a synchronous clock having a different frequency is input to each shift register to shift the shift. When a start pulse signal is input to the serial input of the register, the word line connected to the shift register is sequentially activated in synchronization with the clock, and the bit line selection circuit sequentially stores the data stored in the memory cell array. A continuous access memory, wherein reading or writing of data to the memory cell array is continuously performed in synchronization with a clock. 4. A memory including a memory cell array, a sense amplifier, and a write control circuit, comprising a synchronous shift register having a bit number corresponding to the number of word lines to the memory cell array, and all the shift registers. The parallel output lines corresponding to the bits are connected to the word lines of the memory cell array, and the inputs of all the flip-flops forming the shift register are output from the preceding flip-flops and the number of word lines from the outside. A logical sum of the start signal and the initial value input of the flip-flop is input with a common external initialization signal, and a word of a clock cycle to access any one start signal input of the shift register is input. Time for a few minutes
Input of a start signal to be activated, the word lines are sequentially activated in synchronization with the clock, and when all the start signal inputs are negated, the flip-flops are used by using the initialization signal. Are initialized so that the word line is not activated, the reading of the data stored in the memory cell array or the writing of the data into the memory cell array is synchronized with the clock and any number of addresses are selected. A continuous access memory characterized in that the data of can be continuously accessed.