JPH02156177A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten useless testing time, to make the cost of testing low and to decrease the amount of test patterns by selectively separating a part of a plurality of registers constituting a scan path. CONSTITUTION:An input to a register 11 is a shift input IN. The output of the register is connected to a selecting circuit 21. Another input to the circuit 21 is the shift input IN. The output of the circuit 21 is connected to register 12-1n in series and outputted as a shift output OUT. A shift control 1 (SFT1) is a control line for determining whether the register 11 is connected to the scan path or not. The shift of the register 11 is controlled by an AND circuit 41 with the SFT. The SFT1 is selecting information for the circuit 21. When the data setting register is 12, the register 11 is not used. Then, the circuit 21 is set so that the shift input IN is inputted into the register 12 by the SFT1. Therefore, the number of the shift clocks can be only the number of the bits of the register 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a scan canvas composed of a plurality of registers.

[Conventional technology]

A conventional semiconductor integrated circuit device of this type has a scan canvas shown in FIG. FIG. 4 shows registers 11,
12. ...Connect the shift inputs and outputs of all registers in series so that 1n enters the scan canvas, and connect the shift data input to HJ.

The shift data output is set to OUT, and the shift control is set to SFT. Normally, data is not set or read in all registers; for example, there are 12 registers to set data.
In this case, the total number of bits in register 11 and register 12 is required as the number of shift clocks, and when reading data from register 12, the number of shift clocks is the sum of the number of bits in register 11 and register 12. ..., the total number of bits of In.

Generally speaking, the maximum number of shift clocks equal to the total number of bits of the registers 11 to 1n is always required when reading or writing data once.

[Problem to be solved by the invention]

In the semiconductor integrated circuit device having the above-mentioned conventional scan canvas, all the registers are connected in series, so even if there is a register in which data is not set or read, the necessary register information cannot be transferred unless the data is transferred using the shift clock. Since it is not possible to read or write data, the number of shift clocks is increased. - Scanvases are often installed on boats to test semiconductor integrated circuit devices, and an unnecessary increase in the number of shift clocks has the disadvantage of lengthening the test time and increasing the amount of test slams. Was.

[Means to solve the problem]

The semiconductor integrated circuit device of the present invention has a scan canvas composed of a plurality of registers, and includes means for selectively separating some of the registers from the scan canvas.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. register 1
1 is a shift input IN, and its output is connected to the selection circuit 21. The other input of the selection circuit 21 is a shift input IN, and the output of the selection circuit 21 is connected to the registers 12 to In in a 1llJ manner, and a shift output OUT.
Output to. Shift control 1 (SFTI) is a control line for determining whether to incorporate the register 11 into the scan canvas, and performs shift control of the register 11 by the AND circuit 41 with the shift control (S F T). In addition, shift control 1 (
SFTI) also serves as selection information for the selection circuit 21.

If the register to set data is 12, register 11
is not used, so if the selection circuit 21 is set so that the shift input IN is input to the register 12 by shift control 1 (SFTl), the number of shift clocks is set to register 1.
This means that only 2 bits are required.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

The register 11 in Fig. 1 is configured to bypass the scan canvas by shift control 1 (SFTl), but in Fig. 2, the register 12 is configured to bypass the scan canvas by shift control 2 (SFT2). The same is true.

In this example, if register 12 is not used when reading the contents of register 11 or setting data to registers 13 to In, shift control 2 (SF'T2) bypasses register 12 and changes the number of shift clocks. can be reduced by the number of bits in register 12.

As can be understood from this example, registers 11, 12, and
. . , 1n, whichever register is provided with a scan canvas bypass.

FIG. 3 is a circuit diagram of still another embodiment of the present invention.

FIG. 3 shows an example of a circuit in which a plurality of registers can be bypassed, and the number of shift clocks can be reduced by the total number of bits of the bypassed registers.

〔Effect of the invention〕

As explained above, the present invention selectively separates (bypasses) some of the registers constituting the scan canvas from the scan canvas so that data can be written or read at one time. Since the number of shift clocks can be reduced, wasted test time is reduced, which reduces test cost and reduces the amount of test clicks.

[Brief explanation of the drawing]

1, 2, and 3 are circuit diagrams of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 4 is a circuit diagram of a conventional semiconductor integrated circuit device. IN...Shift input data, OUT...
・Shift output data, SFT...Shift control,
5FTI...Shift control 1.5FT2...
・Shift control 2.11~In...Register, 4
1-42...AND circuit, 21.22...
...Selection circuit. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] A semiconductor integrated circuit device having a scan canvas composed of a plurality of registers, characterized in that the semiconductor integrated circuit device is provided with means for selectively separating at least some of the plurality of registers from the scan canvas. Device.