JPS63188782A - Test assisting circuit - Google Patents

Abstract

PURPOSE:To shorten a test time by supplying the two-phase clock output of a scan path to a scan path connected to a trailing stage it as it is or in an active state. CONSTITUTION:When an operation mode is set, logic 1 is set in a scan register SRb and a pit for operation mode setting which is shifted in is set in a scan register SRa. When logic 0 is set in the register SRa, neither of OR circuits 12b and 12c operates and the two-phase clock inputted to clock input terminals 6 and 7 is sent to clock output terminals 15 and 16. Therefore, a normal clock is supplied to the scan path connected to the trailing stage to perform normal shifting operation. When the logic '1' is set in the register SRa, on the other hand, the terminals 15 and 16 are made active at the same time by the circuits 12b and 12c to enter a data transmission state wherein the input data is outputted to the scan path connected to the trailing stage as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a test auxiliary circuit for simplifying testing of semiconductor devices.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional scan path type test auxiliary circuit. In the figure, 1 is a scan register, and a plurality of scan registers are connected in series to form a shift register. 2 is a parallel input terminal, 3 is a parallel output terminal, 4 is a mode switching terminal, 5 is a serial input terminal, 6, 7
8 is a clock input terminal, and 8 is a serial output terminal.

Next, the operation will be explained.

By setting the mode switching terminal 4 to the serial shift mode, a serial shift is performed every time a two-phase clock is applied to the clock input terminals 6 and 7, and a shift out bit is output to the serial output terminal 8. Shift in data from 5.

On the other hand, by setting the mode switching terminal 4 to the parallel input mode, the data applied to the parallel input terminal 2 is taken into the scan register every time a clock is applied.

In either mode, the value held by the scan register is output to the parallel output terminal 3.

The scan path can operate as described above, so test data is shifted in in serial shift mode, added to the circuit under test through parallel output terminal 3, and the response of the circuit under test is taken into the scan register in parallel input mode. , can be shifted out to the serial output terminal in serial shift mode.

In this way, the number of terminals required for testing is small (in Fig. 3, only five terminals are required: mode switching terminal 4, serial input terminal 5, clock input terminal 6, 7, and serial output terminal 8). The device can be configured at low cost and is used as a test auxiliary circuit.

[Problem that the invention seeks to solve]

Conventional test auxiliary circuits are configured as described above, so when the circuit under test is divided into multiple functional block circuits, unnecessary shift operations are required, resulting in an increase in test time. was there. This problem will be explained using FIG. 4.

In FIG. 4, numerals 1 to 8 indicate the same or corresponding parts as in FIG. 3. 9 and 10 indicate separate functional block circuits, respectively. In FIG. 4, the scan path is separated into two, an n-stage scan path and an m-stage scan path are connected in series, and the n-stage scan path is connected to the functional block circuit 9.
The m-stage scan path is connected to a functional block circuit 10.

When testing a semiconductor device having a plurality of functional block circuits using a scan path as described above, there are the following drawbacks. That is, reading data (m bits) from the functional block circuit 10 requires m shift operations, but reading data (n bits) from the functional block circuit 9 requires n0m shift operations. It is. As described above, there are cases where the number of shifts is greater than the number of bits that are effective as information, resulting in an increase in test time and a problem in that the test cost of the semiconductor device increases.

This invention was made to solve the above-mentioned problems, and it is possible to read data from each functional block circuit without performing unnecessary shift operations when testing a semiconductor device having multiple functional block circuits. The purpose of the present invention is to obtain a test auxiliary circuit that can perform the following steps and shorten the test time.

[Means for solving problems]

The test auxiliary circuit according to the present invention supplies the two-phase clock output of the scan path to the scan path connected to the subsequent stage either as is or in an active state, depending on the data shifted in first, An operation mode setting means is provided for setting the subsequent scan path to either a normal mode or a mode in which input data is output as is (so-called transparent mode).

[Effect]

In this invention, the data shifted in first can set the subsequent scan canvas to which the functional block circuit under test is connected to the so-called transparent mode. Block circuits can be tested.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a test auxiliary circuit according to an embodiment of the present invention, in which 1 is a scan register, 2 is a parallel input terminal, 3 is a parallel output terminal, 4 is a mode switching terminal, 5 is a serial input terminal, and 6゜7 is a clock input terminal,
8 is a serial output terminal, 11a and llb are AND circuits,
12a, 12b.

12c is an OR circuit, 13 is a NOT circuit, 14 is a selector circuit, and 15.16 is a clock output terminal. The scan register 1 is operated by two-phase clocks, and is capable of directly transmitting information from the serial input terminal 5 to the serial output terminal 8 when the two-phase clocks are active at the same time.

Next, the operation will be explained.

In the figure, numerals 1 to 7 indicate the same or equivalent parts as in FIG. 3, and the circuit operates in the same way as the circuit in FIG. 3.

However, scan registers SRa and SRb are added for setting the operation mode.

First, in order to initialize the circuit, the clock input terminal 6 is
．． 7 are activated (logic "1") at the same time, scan registers SR□1 to SR0, SRa, and SRb are
The clock input terminals are the AND circuit 11a and the OR circuit 1.
Both phases become active by control of 2a, etc., and enter a data transparent state. At this time, the logic “
If "0" is set, all scan registers are initialized to "0". When the clock is made inactive, the initialization is completed.

To set the operating mode, first set the mode switching terminal 4 to the serial shift mode, and while applying a two-phase clock to the clock input terminals 6 and 7, convert the logic signal through the serial input terminal 5.
1" is shifted in. Following this, a bit for operating mode setting is shifted in. After that, a clock is applied and the shift operation is continued. When the first logic "1" shifted in reaches the scan register SRb, the AND circuit 11b is shifted in. , O
Under the control of the R circuit 12a and the NOT circuit 13, the clock signal CLK2 is no longer applied to the scan registers SRa and SRb, and even if a clock is applied to the clock input terminal 6.7, the data in the scan registers SRa and SRb are held. At this time, the scan register SRb contains the logic “
1'', the shifted-in operation mode setting bit is set in the scan register SRa.

The selector circuit 14 has the scan register SRb set to logic “0”.
”, the switch is switched to the side that inputs a fixed logic “0”. Therefore, the serial output terminal 8 remains at logic “0” until the contents of the scan register SRb reach logic “61”. Retained. When the content of the scan register SRb becomes logic "1", the selector circuit 14 switches to output the serial output from the scan register SR0 to the serial output terminal 8.

At this time, if the scan register SRa is set to logic "0", the OR circuits 12b and 12c do not act and transmit the two-phase clock input to the clock input terminals 6 and 7 to the clock output terminals 15 and 16. , it is possible to apply a normal clock to the scan canvas connected to the subsequent stage and have it perform a normal shift operation. On the other hand, if the scan register SRa is set to logic "1", the OR circuits 12b and 12C simultaneously make the clock output terminals 15 and 16 active (logic "1"), and input the scan canvas connected to the subsequent stage. It is possible to create a data transparent state in which data is output as is.

FIG. 2 shows the configuration of a semiconductor device equipped with the circuit of this embodiment. In FIG. 2, 1 is a scan register, 2 is a parallel input terminal, 3 is a parallel output terminal, 4 is a mode switching terminal, 5 is a serial input terminal, 6 and 7 are clock input terminals, 8 is a serial output terminal, 9. 10 is a separate functional block circuit, 17 is a conventional m-bit scan canvas, and 18 is a test auxiliary circuit of this embodiment, which has n-bit parallel input/output.

Initially, if the operation mode of the test auxiliary circuit 18 is set to the transparent mode using the same method as shown above, the clock input terminals of the scan canvas 17 will be in the active state for both phases, and the signal of the serial input SI of the scan canvas 17 will be It is transmitted directly to the serial output SO. In other words, the scan canvas 17 is in a data transparent state, and data can be read from the functional block circuit 9 by n shift operations. Note that if the operation mode of the test auxiliary circuit 18 is set to the normal mode, data can be read from the functional block circuit 10 by m shift operations, as in the conventional case.

In this way, in the circuit of this embodiment, when the operation mode setting bit shifted in after initialization is logic "0", the subsequent scan canvas 17 can be set to the normal mode, and the logic "1" is set.
”, you can set it to so-called data transparency mode.
By setting the operating mode setting bit to logic "0", it is possible to test the functional block circuit 9 using the scan canvas 18 without performing unnecessary shift operations, and by setting the operating mode setting bit to logic "1". Then, the functional block circuit 10 can be tested using the scan canvas 17 at the subsequent stage. Therefore, a semiconductor device having a plurality of functional block circuits can be tested in a short time without unnecessary shift operations.

In the above embodiment, the OR circuits 12b and 12C are used to control the clock so that both phases are always active, but even if only one phase is controlled to be always active, it will not work when the other phase is active. Since the scan canvas connected to the subsequent stage becomes data transparent, the same effect can be obtained.

Further, although only one test auxiliary circuit is used in the semiconductor device shown in FIG. 2, the same effect can be obtained even if a plurality of test auxiliary circuits are connected in series.

〔Effect of the invention〕

As described above, according to the present invention, depending on the data shifted in first, the two-phase clock output of the scan canvas is supplied to the scan canvas connected to the subsequent stage either as is or in an active state. However, since an operation mode setting means is provided for setting the subsequent scan canvas to either a normal mode or a mode in which input data is output as is, by setting the scan canvas connected to the subsequent stage to transparent mode, Functional block circuits can be tested using the scan canvas in the previous stage without unnecessary shift operations, and therefore semiconductor devices having multiple functional block circuits can be tested in a short time without unnecessary shift operations. , which has the effect of lowering test costs.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a test auxiliary circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing a semiconductor device using the circuit of this embodiment, and FIG. 3 is a block diagram showing a conventional test auxiliary circuit. , FIG. 4 is a block diagram showing a semiconductor device using a conventional test auxiliary circuit. In the figure, 1 is a scan register, 2 is a parallel input terminal,
3 is a parallel output terminal, 4 is a mode switching terminal, 5 is a serial input terminal, 6.7 is a clock input terminal, 8 is a serial output terminal, 9.10 is a functional block circuit, lla, l
lb is an AND circuit, 12a, 12b, 12c are OR circuits, 13 is a NOT circuit, 14 is a selector circuit, 15.16
is a clock output terminal, 17 is a conventional scan canvas circuit,
Day 1 shows the test auxiliary circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) Perform a shift operation using two-phase clocks, and
It is equipped with a scan path that can directly transmit information on the serial input terminal to the serial output terminal when the phase clocks are active at the same time, and is controlled by the first data shifted in in the test auxiliary circuit that tests semiconductor devices. The serial output of the scan path is supplied as is to the scan path connected to the subsequent stage of the scan path, and the two-phase clock output of the scan path is supplied either as is or in an active state. . A test auxiliary circuit characterized by comprising operation mode setting means for setting the latter stage scan path to either a normal mode or a mode in which input data is output as is. (2) The operation mode setting means includes a first scan register that receives as input the serial output from the scan path, a first clock, and the output of a first OR circuit (to be described later); a second scan register that receives the first and second clocks as input; an AND output of the first and second clocks from the scan path; and an inverted signal of the second clock and the serial output of the second scan register. and a selector circuit that connects the serial output of the scan path to the serial output terminal connected to the subsequent scan path only when the serial output of the second scan register is active. , the serial output from the first scan register and the first
a second O which receives a clock as an input and outputs its output to a first clock output terminal connected to the latter scan path;
R circuit; and a third OR circuit that receives the serial output of the first scan register and the second clock from the scan path as input, and outputs the OR output to a second clock output terminal connected to the scan path in the latter stage. A test auxiliary circuit according to claim 1, characterized in that the test auxiliary circuit comprises: