JPH04141746A - Information processor - Google Patents

Abstract

PURPOSE:To eliminate the need for a number of control signal lines by constructing a shift path with several partial shift pathes and providing a bypass function for the several partial shift pathes. CONSTITUTION:In a logic circuit 1 consisting of a single LSI, all the partial shift pathes composed of first partial shift pathes 10-1 to 10-n with the bypass function and second partial shift pathes 11-1 to 11-n without the bypass function are connected in series to form one shift path. The first partial shift pathes with the bypass function and the second shift pathes without the bypass function can be connected in the arbitrary order and plural number of each of them can be connected consecutively. A shift input signal line 101, a shift output signal line 102 and a shift clock signal line 103 are shared in shift operation. Thus, the number of signal lines required for constructing and controlling the shift path can be reduce.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device that uses a scanning method as an inspection and initialization method, and particularly relates to an information processing device in which a shift path is composed of a plurality of partial shift paths, and a plurality of partial shift paths. The present invention relates to an information processing device having a bypass function.

[Conventional technology]

In an information processing device including a sequential circuit, as a testing and initialization method used, in addition to the circuit for normal operation, a shift path is provided in which flip-flops in the device are connected in series to operate as a shift register. There is a scan method that allows data to be written and read. Since the length of the shift path increases almost in proportion to the circuit scale of the device, as the device becomes larger, the time required for testing and initializing the scanning method increases. Furthermore, when high-speed reading and writing is required for a specific register, there is a method of shortening the length of the shift path by providing a bypass function on a partial shift path that connects other routers and removing it from the shift path. This type of shift path configuration control has been performed by applying a bypass selection signal from outside the device to each partial shift path having a bypass function.

FIG. 4 is a block diagram of an example of a conventional information processing device. 20-1 to 20-n are partial shift paths having a bypass function, and 21-1 to 21-m are partial shift paths not having a bypass function. All the partial shift paths are connected in series to form one shift path, which takes in information from the input data signal line 202 and sends the shift output to the output data signal line 203 under the control of the data shift clock 201 (7). Partial shift hash 20- with bypass function
1 to 20-n each have a bypass selection signal! 204
-1 to 204-n are connected, and the configuration of the shift path is controlled by control signals supplied through these signal lines.

[Problem to be solved by the invention]

The footpath control system in the conventional information processing device described above controls the shift path configuration so as to shorten the length of the shift path by excluding any partial shift path that does not require inspection or initial setting. One bypass selection signal is required for each shift pass, and as the number of bypasses increases, a large number of control signal lines are required.

[Means to solve the problem]

An information processing device of the present invention includes a shift path including at least two partial shift paths having a bypass function, a bypass control register that controls the shift path, and a shift input signal that is shared by the shift operation of the shift path and the bypass control register. line, a shift output signal line, a shift clock signal line, a mode signal line indicating whether the target of the shift operation is the shift path or the bypass control register, and the shift clock signal according to the instructions of the mode signal line. clock switching means for supplying a line shift clock to either the shift path or the bypass control register; and a shifter for selectively outputting the shift output of the shift path or the bypass control register to the shift output signal line according to instructions from the mode signal line. and output selection means.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In a logic circuit 1 composed of one LSI, first partial soft paths 10-1 to 10- have a bypass function.
n and a second partial shift path 1 with bypass function 2 without
All the partial shift hubs 1-1 to 11-m are connected in series to form one 7-foot path. The first partial shift path with the bypass function and the second partial shift path without the bypass function can be connected in any order, and a plurality of each can be consecutive.

The bypass control register 12 is a shift register with a number of bits equal to the number of first partial shift paths, and the value of each bit is output as a bypass control signal to the first partial shift paths 10-1 to 10-n, and Determine the configuration of

The clock switching circuit 13 has a shift clock signal line 103.
A shift clock is inputted from the input signal line 104, and the shift clock is sent to either the data shift clock signal line 105 or the configuration information shift clock signal line 106 according to the information indicated by the mode signal line 104. The first and second partial shift paths 10 and 11 take in data by shifting the shift clock supplied from the data shift clock signal line 105 and the data input signal line 101, and output a shift signal to the shift output selection circuit 14. do.

The bypass control register 12 takes in data through a shift operation between the shift clock supplied from the configuration information shift clock signal line 106 and the data input signal line 10-1, and outputs a shift signal to the shift output selection circuit 14.

The shift output selection circuit 14 selects, as an input, a signal for performing a shift operation according to the information on the mode signal line 104 from among the shift signals of the first and second partial shift paths 10.11 or the bypass control register 12, and outputs the signal as a data output. Output to signal line 102.

FIG. 2 is a block diagram showing the partial shift path of this embodiment. When the bypass control signal 109 is logic "1", the data shift clock 105 is applied to the partial shift path 15 via the clock control circuit 16, and the data Data is taken into partial shift path 15 from input signal line 107 . The 7-foot signal output of the partial shift path 15 is selected by the bypass control circuit 17 and sent to the data output signal line 108.

Furthermore, when the bypass control signal 109 is at logic "0", the bypass control circuit 17 selects the data input signal line 107, bypasses the partial shift path 15, and sends it as is to the data output signal line 108. In addition, the clock control circuit 1
6 stops supplying the clock to the partial shift path 15 to suppress the shift operation of the partial shift path 15.

With the above configuration, partial shift path 10.11 of logic circuit 1
To write and read data to the mode signal line 1, first
In step 04, the bypass control register 12 is selected as a shift operation target, and the same number of clocks as the bit lines of the bypass control register 12 are applied from the shift clock signal line 103 via the clock switching circuit 13, and the shift input signal line 101
The configuration control information of the partial shift path 10.11 is input from the partial shift path 10.11 to enable shift writing and reading to the target partial shift path 10.11.

Next, the mode signal line 104 selects partial shift paths 1o and ii for the shift operation, and the shift clock signal line 1
A shift clock is applied from 03 to each partial shift path 10, 11 via the clock switching circuit 13, and the shift input signal line 101 is applied to the target partial shift path 10°11.
7-foot output selection circuit 14.
Reading is performed from the soft output signal line 102 via the soft output signal line 102. Even when the number of LSIs in the logic circuit 1 is two or more, the LS
The input/output signals of I can be connected and handled in the same way as if there were only one.

FIG. 3 is a block diagram showing a system including a plurality of LSIs in the logic circuit of this embodiment, and the LSIs are distinguished by names M1 to M. The Ml/ft output signal line 102 is Ml. , and supply a common clock signal and mode signal to the shift clock signal line 103 and mode signal line 104 of each LSI, respectively. Here, i is an integer greater than or equal to 1 and less than.

In this way, writing and reading data to and from the shift path composed of partial shift paths of each LSI is performed by the LSI.
Using the shift input signal line 101 of the IM, the /ft output signal line 102 of the LSIMK, the shift clock signal line 103 and the mode signal line 104 commonly connected to all LSIs, it is possible to perform the same operation as when there is only one LSI. can be done.

〔Effect of the invention〕

As described above, the present invention provides a bypass control register for controlling the configuration of the shift path to shorten the length of the shift path by excluding arbitrary portions of the 7-foot path that do not require inspection or initialization, and a shift operation of the shift path and the bypass control register. By sharing the /ft input signal line, the shift output signal line, and the /ft clock signal line, it is possible to reduce the number of signal lines required for controlling the configuration of the shift path.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a block diagram showing parts/footpaths of this embodiment, Fig. 3 is a block diagram showing a plurality of devices of this embodiment connected, and Fig. 4 1 is a block diagram showing an example of a conventional information processing device. 1... Logic circuit, 10-1 to 10-n... First partial shift path, 11-1 to 11-m... Second partial shift path, 12... Bypass control register, 13...
・Clock switching circuit, 14...shift output selection circuit,
15... Partial shift path, 16... Clock control circuit, 17... Bypass control circuit.

Claims (1)

[Claims] A shift path including at least two partial shift paths having a bypass function, a bypass control register that controls this shift path, and a shift input signal line, a shift output signal line, and a shift shared by the shift operation of the shift path and the bypass control register. a clock signal line, a mode signal line indicating whether the target of the shift operation is the shift path or the bypass control register; A clock switching means for supplying one of the bypass control registers, and a shift output selection means for selectively outputting the shift path or the shift output of the bypass control register to the shift output signal line according to instructions from the mode signal line. Characteristic information processing device.