JPS63204836A - Clock crossover circuit - Google Patents

Abstract

PURPOSE:To prevent unstable operation in case of clock crossover by using a 1st clock so as to detect the leading edge and the trailing edge of an input data, converting the result into an output synchronously with a 2nd clock and then using the converted output so as to reproduce a data synchronously with the 2nd clock. CONSTITUTION:The 1st clock is used so as to detect the leading edge and the trailing edge of the input data at a leading edge/trailing edge detection means 9. Then the two detection outputs are given to a leading edge clock crossover means 10 and a trailing edge clock crossover means 11 to convert them into the detection output synchronously with the 2nd clock. Then the detection output converted by the data reproduction means 12 is used to reproduce the data synchronously with the 2nd clock. Since no intermediate clock (CK) is used in this way, the possibility of unstable operation in case of clock crossover is improved.

Description

[Detailed Description of the Invention] [Summary] In a clock switching circuit, a rising edge and a falling edge of input data are detected by a rising edge/falling edge detection means using a first clock, and these two detection outputs are After converting the data into an output synchronized with the second clock, this converted output is used to reproduce data synchronized with the second clock, thereby improving the possibility of unstable operation when switching clocks. It is.

[Industrial application field]

The present invention relates to improvements in clock switching circuits.

FIG. 4 shows a clock switching circuit connection diagram.

In the figure, when receiving and passing data between the first device and the second device, the two devices have the same period, but the Glock CK-1, CK of different systems are out of phase with each other.
-2, the clock switching circuit converts data synchronized with the clock CK-1 of the first device into data synchronized with the clock CK-2 of the second device (this is called clock switching). and sends it to the second device.

At this time, it is necessary to reduce the possibility that the switching operation becomes unstable.

[Prior Art] FIG. 5 is a block diagram of a conventional example, and FIG. 6 is a time chart of FIG. 5. The symbols on the left side indicate the waveforms of the portions with the same symbols in FIG. The operation shown in FIG. 5 will be explained below with reference to FIG.

First, a write clock (hereinafter abbreviated as W-CK) and data as shown in Figure 6-■ and ■ are applied to the D-type flip-flop (hereinafter abbreviated as D-FF) 1. Then, the data shifted by 1 bit as shown in FIG. 6-2 is sent to the D-FF7.

Next, D-FF 2 takes in the 1 added to the D terminal at the rising edge of -CK and adds it to the AND gate 4.
The FF 3 takes in the 1 applied to the D terminal at the rising edge of the read clock (hereinafter abbreviated as R-CK) as shown in FIG.

Therefore, when both inputs are 1, the output 1 of this AND gate 4 is applied to the CLR terminals of D-FFs 2 and 3 via an inverter (hereinafter abbreviated as INV) 5.
The two D-FFs are cleared.

However, since 1 is captured and cleared at each rising edge of W-CK and R-CK, the waveforms shown in Figure 6-■ and ■ are applied to the AND gate 4, and from there the waveforms shown in Figure 6-■
A waveform shown in (hereinafter referred to as intermediate CK) is applied to the CK terminal of the D-FF 7 via the buffer 6.

For this reason, the above data synchronized with W-GK is shown in Figure 6-■
As shown in the figure, the data is converted to data synchronized with the intermediate GK.
It is added to the D terminal of FF 8, but since R-CK is added to the CK terminal here, it is punched out to R-C as shown in Figure 6 - [Phase]! ? -Data synchronized with CK is obtained, and clock switching is completed.

[Problem that the invention seeks to solve]

In general, the width of the CK is regulated depending on the device used, so the width of the intermediate GK mentioned above must also be adjusted so that it satisfies the regulations.
For example, a plurality of NV5s are connected in a cascade manner, and the clearing timing is shifted to provide a delay.

However, there is a problem that, for example, when the delay is reduced and the clock width is narrowed in order to reduce the circuit scale, the operation of the D-PF 7 may become unstable.

[Means for solving problems]

The above problem is solved by the clock switching circuit shown in FIG.

9 is a rising edge/falling edge detection means for detecting the rising edge and falling edge of data synchronized with the first clock; 10.11 is a rising edge/falling edge detection means for detecting the rising edge/falling edge of data synchronized with the first clock;
These are rising edge clock switching means and falling edge clock switching means for converting the output from the falling edge detection means into an output synchronized with the second clock.

Further, 12 uses the output of the rising edge clock switching means and the falling edge clock switching means,
This is data reproducing means for reproducing data synchronized with the second clock.

[Effect]

In the present invention, a rising edge and a falling edge of human data are detected by a rising edge/falling edge detection means 9 using a first clock, and these two detection outputs are detected by a rising edge clock switching means 10. After converting the detection output into a detection output synchronized with the second clock by a falling edge switching means 11, the data reproduction means 12 uses the converted detection output to reproduce data synchronized with the second clock. That is, since the intermediate CK is not used, the possibility of unstable operation at the time of clock switching is improved.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a time chart of FIG. 2, where the symbols on the left indicate the waveforms of the portions with the same symbols in FIG. Incidentally, D-FFs 91 to 93 are the constituent parts of the rising edge/falling edge detection means 9;
-FF 101 is a rising edge clock switching means 10. The D-FF 111 is a component of the falling edge clock switching means 11, and the JK-FF 121 is a component of the data reproducing means 12.

The operation of FIG. 2 will be described below with reference to FIG. 3, with W-CK as the first clock and R-GK as the second clock.

First, as shown in Fig. 3-■, As shown, the data shifted by 1 bit and the inverted data are used as the clock D.
-Added to GK terminal of FF 92 and 93.

Therefore, at the rising edge of these clocks, the 1 added to the D terminal is taken in, and as shown in FIG.

As shown in (2), l is applied from the Q terminals of D-FFs 92 and 93 to the D terminals of D-PFs 101 and 111.
This is the I? added to the CK terminal. -CK is punched out, 1 is output from the Q terminal, and 0 is output from the Q terminal.

For this reason, D-PF 92.93 is cleared by the latter and the Q terminal changes from 1 to O as shown in Figure 3-■ and ■, but the above operation is repeated with the output from D-FF 91. .

The former becomes O by clearing D-FF 92.93, but this is repeated and outputs as shown in FIG. In addition, R- is connected to the CK terminal here via INV 122.
Since CK is added, R- as shown in Figure 3-0.
Data synchronized with C is output.

That is, since only -GK and R-CK are used when changing the clock, the possibility of unstable operation is improved.

〔Effect of the invention〕

As described above in detail, the present invention has the effect of reducing the possibility of unstable operation.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a time chart of Fig. 2, Fig. 4 is a clock switching circuit connection diagram, and Fig. 5 is a conventional block diagram. An example block diagram, FIG. 6 shows the time chart of FIG. In the figure, 9 indicates rising edge/falling edge detection means, 10 indicates rising edge clock switching means, 11 indicates falling edge clock switching means, and 12 indicates data reproducing means. /1-To Ming to Okiyurifu" D rough diagram, !p1 diagram /i'-To Ming's cannon included Jof"'O so Z diagram 77z diagram■ 7' N7t ribusi 8B'j'! , fLfB'1.41
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Claims (1)

[Claims] Rising edge/falling edge detection means (9) for detecting rising edges and falling edges of data synchronized with a first clock; and an output from the rising edge/falling edge detection means. Using a rising edge clock switching means and a falling edge clock switching means (10, 11) that convert into an output synchronized with a second clock, and the outputs of the rising edge clock switching means and falling edge clock switching means, A clock switching circuit comprising data reproducing means (12) for reproducing data synchronized with the second clock.