JPH01253337A - Multi-frame synchronism inspecting circuit - Google Patents

Abstract

PURPOSE:To ensure highly reliable synchronism inspection in a simple constitution by transmitting a synchronizing abnormal signal to a multi-frame synchronizing means in the timing of the frames set every prescribed number of pieces in case a prescribed bit of one of said frames is equal to '1'. CONSTITUTION:When the synchronism is secured, a received FA signal = 1 passes directly through an AND gate 212-3 and produces a signal x = '1'. An FA synchronism protecting circuit 206 stores (a=1*x=1). When a received FA signal = '1' is detected by some reason for a period up to the next gate signal a='1', a signal x = '0' is obtained in the timing of the gate signal a='1'. Thus the circuit 206 stores (a=1*x=0). Then the circuit 206 decides an FA synchronism step-out state at the time point when the (a=1*x=0) is continuously stored twice and transmits an FA synchronism detecting signal ='0' to show the occurrence of said step-out. An M synchronism detecting action is also carried out in the same way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-frame synchronization verification circuit in ISDN.

[Prior art] Regarding the multiframe structure in ISDN, see C.
It is found in CITT Recommendation I 430.

FIG. 2 is a diagram showing an overview of the multiframe structure and Q-bit identification. In the figure, a network terminal equipment (NT) sends a multiframe to a terminal equipment (TE). Each frame includes an FA bit and an M bit for frame synchronization, the FA bit has a content of “1” every 5 frames, and the M bit has a content of “1” every 5 frames.
0 frames every frame has a content of 1”. TE has M bits =
1 to identify the first frame of a multiframe, and while synchronization is established, a frame with FA bit = 1 sends Q to the NT.
Send n bits. Also, it is “0” while out of synchronization.
Send. In order to obtain and maintain this synchronization, the TE uses M synchronization (sync of M bit = 1 and FA bit = 1).
, and FA synchronization (FA bit = 1).

[Problems to be Solved by the Invention] However, conventionally, a multi-frame synchronization verification circuit that achieves the above with a simple configuration and high reliability has not been disclosed.

The present invention has been made in view of the background of the prior art described above, and its purpose is to propose a multi-frame synchronization verification circuit that has an extremely simple configuration and can perform highly reliable synchronization verification. be.

[Means for Solving the Problems] In order to achieve the above object, the multiframe synchronization verification circuit of the present invention includes a frame synchronization means that receives a bit string of a multiframe configuration and synchronizes each frame, and a frame synchronization means that synchronizes each frame by receiving a bit string of a multiframe configuration. multi-frame synchronization means detecting that a predetermined bit of the frame is °゛l'' and synchronizing the frames every predetermined number; and any one of the frames every predetermined number.
2. Memorizing that the predetermined bit of one frame is "1" and outputting a synchronization abnormal signal to the multi-frame synchronization means at the timing of every predetermined number of frames.
The outline is to provide a value holding means.

[Operation] In this configuration, the frame synchronization means receives the bit string of the frame structure and synchronizes each frame. The multi-frame synchronization means detects that a predetermined bit of each predetermined number of frames is "1°°" and synchronizes the predetermined number of frames. The predetermined bit of any one frame is “1”
, and outputs a synchronization abnormality signal to the multi-frame synchronization means at the timing of every predetermined number of frames.

[Description of Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a multi-frame synchronization verification circuit according to an embodiment. In the figure, a frame synchronization detection circuit 204 receives a frame signal, performs synchronization detection for the frame, and outputs a frame synchronization detection signal indicating the presence or absence of frame synchronization. An FA counter circuit 205 outputs a gate signal a (=1) by counting 5 frames after inputting each received FA signal=1. 212 is a reception zero verification circuit, and out of the FA bit array for 5 frames [1, O, O, 0゜0], the FA bit array for 4 frames is [0, O, O , Ol and the FA bit of the next frame is "l", outputs "l" as the received zero test signal X. Or similarly, 20
Array of M bits for one frame [1, O, O, O,...
, the M-bit array for 19 frames of Ol is [0
, O, O, . . . , and if the M bit of the next frame is "1", "1" is output as the received zero test signal y. Reference numeral 206 denotes an FA synchronization protection circuit, which takes in the contents of the received zero verification signal X into an internal shift register at the timing of the gate signal a=1. Then, when the content of the received reception zero verification signal
It determines that A is out of synchronization and outputs an FA synchronization detection signal to that effect. This synchronous/asynchronous determination method takes into consideration erroneous reception of FA bits due to noise or the like. 207
is an M-counter circuit, which outputs a gate signal b (=1) by counting 20 frames after receiving the received FA signal and the received M signal at the same time. Reference numeral 208 denotes an M synchronization protection circuit, which takes in the contents of the received zero verification signal y into an internal shift register at the timing of the gate signal b=1. When the content of the received reception zero test signal y is "1" three times in a row, it is determined that the M synchronization is established, and
When it is "O" twice in succession, it is determined that the M synchronization is out of state, and an M synchronization detection signal to that effect is output.

Further, a negative signal of the frame synchronization detection signal is led to the FA synchronization protection circuit 206. This enables the operation of the FA synchronization protection circuit 206 when frame synchronization is achieved, and resets the FA synchronization protection circuit 206 when frame synchronization is lost. Further, each negative signal of the frame synchronization detection signal and the FA synchronization detection signal is led to the M synchronization protection circuit 208. As a result, the M synchronization protection circuit 208 is enabled when frame synchronization and FA synchronization are established, and the M synchronization protection circuit 208 is reset when frame synchronization or FA synchronization is lost.

FIG. 3 is a timing chart of the received FA signal and the received M signal in the embodiment. In the figure, a frame signal is received from the line side. There are an FA bit and an M bit at predetermined positions in one frame signal. The received FA signal is a signal that is set when the FA bit=1 and reset when the FA bit=O.

Received M signal is set with M bit = 1, M bit = 0
This is a signal that is reset by

FIG. 4 is a circuit diagram showing details of the reception zero verification circuit 212 of the embodiment. Although the figure shows the input of the received FA signal, the same applies to the input of the received M signal. In the figure, 212-1 is a flip-flop circuit (FF), and when a clock signal (a clock signal that counts up the number of frames) is input under the conditions that the received FA signal = "L" and the gate signal a = "O". Set (output Q="l")
When a clock signal is input with gate signal a="1", it is reset (output Q="O").

AND gate 212-3 connects the received FA signal and FF 212-
The output Q/ (/ means negation) of 1 is input. As a result, if there is no received FA signal between the time when a certain gate signal a="1" and the time when the next gate signal a="l" (that is, the middle 4 frames), the AND gate 212-3 If all the FA bits for one frame are "O"), the content of the received FA signal of the fifth frame ("1" or "0") is passed through as is.

FIG. 5 is a timing chart explaining the FA synchronization verification operation of the embodiment. In the figure, the output Q of the FF 212-1 is "O" at least until the first received FA signal = 1 is received. When the first received FA signal = 1 is received, the count is loaded into the FA counter circuit 205.
The frame count value is forced to "O°". Also, since the frame count value was not "4" at this timing, the gate signal a="O", so the output Q of the FF is "1°". Therefore, the output Q/ of the FF is “0” until the next gate signal a is generated, and therefore the next receiving FA
Signal=1 does not pass through AND gate 212-3. By the way, at this point, the gate signal a="1" and the reception FA signal="1" are generated simultaneously. Therefore, FF212-
1 is reset, and its output Q becomes "0°". Thus, if synchronization is achieved, the received FA signal will be "0" in all four frames until the next gate signal a is generated. Therefore, the FF 212-1 remains reset.As a result, the next received FA signal = 1 passes through the AND gate 212-3 as it is, forming the signal X = "1".Then, the FA synchronization protection circuit 2o6 is gate signal a="1"
and signal X="1", the first (a=1*x=1
). Further, when this synchronized state is maintained, the second and (a=1*x=1) are continuously accumulated.

At this point, the FA synchronization protection circuit 206 determines that FA synchronization has been established, and outputs an FA synchronization detection signal = "1" to that effect.

In addition, due to some reason (noise, malfunction on the transmitting side, etc.), the received FA signal =
“1” may be detected.

In this case, since the FF 212-1 is set, the signal X becomes "O" at the timing of the next gate signal a="1". As a result, the FA synchronization protection circuit 206
a= 1 *x=O) is accumulated. Furthermore, gate signal a=
For some reason, the content of the received FA signal (FA bit) itself may be "0" at the timing of "1".

In this case as well, the FA synchronization protection circuit 206 (a=1*x=
O) is accumulated. Then, when (a=1*x=o) is accumulated twice in a row, the FA synchronization protection circuit 206
It is determined that the synchronization is out of synchronization, and the FA synchronization detection signal to that effect = “O”
Output.

Note that the M synchronization verification operation is also performed in the same manner as described above.

FIG. 6 is a diagram showing the mutual relationship between frame synchronization, FA synchronization, and M synchronization in the embodiment. In FIG. 0, frame synchronization is established in state l. As a result, the FA synchronization protection circuit 206
operation becomes possible and FA synchronization verification begins. state 2
Then FA synchronization is established. As a result, M synchronization protection circuit 2
08 operation is enabled and M synchronization verification is started. In state 3, M synchronization is established. This completes the establishment of multiframe synchronization. In state 4, frame synchronization is lost for some reason, so the FA synchronization protection circuit 206 and M synchronization protection circuit 208 are reset, and F''A synchronization and M synchronization are removed.Furthermore, in state 5, FA synchronization is lost for some reason. M synchronization is removed because of the disconnection.In this case, FA synchronization and M
You can try syncing again. Further, in state 6, only M synchronization is out of order for some reason. In this case, all you have to do is perform M synchronization again.

[Effects of the Invention] As described above, according to the present invention, reliable multi-frame synchronization verification can be performed with an extremely simple configuration.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the multi-frame synchronization verification circuit of the embodiment, Fig. 2 is a diagram showing an overview of the multi-frame structure and Q bit identification, and Fig. 3 is the timing of the received FA signal and received M signal in the embodiment. 4 is a circuit diagram showing the details of the reception zero test circuit 212 of the embodiment. FIG. 5 is a timing chart explaining the FA synchronization test operation of the embodiment. FIG. 6 is a frame synchronization and FA synchronization of the embodiment. , M is a diagram showing the mutual relationship of synchronization. In the figure, 204... frame synchronization detection circuit, 205...
・FA deer 92 circuit, 206...-FA synchronization protection circuit,
2o7...M counter circuit, 208...M synchronization protection circuit, 212...reception zero verification circuit.

Claims (1)

[Scope of Claims] Frame synchronization means receives a bit string having a multi-frame configuration and synchronizes each frame; a multi-frame synchronization means for synchronizing frames; and a multi-frame synchronization means that stores that the predetermined bit of any one frame between the predetermined number of frames is "1", and A multi-frame synchronization verification circuit comprising binary holding means for outputting a synchronization abnormality signal to the multi-frame synchronization means.