JPH01253336A - Multi-frame synchronism inspecting circuit - Google Patents

Abstract

PURPOSE:To smoothly set up and reset up the multi-synchronism in a simple constitution and with sure actions by setting up the synchronisms independently of each other and giving the prescribed priority orders to these set-up actions. CONSTITUTION:When the frame synchronism is set up, an FA synchronism protecting circuit can start to start the FA synchronism inspection. Then an M synchronism protecting circuit 208 can work to start the M synchronism inspection for set-up of the M synchronism after the FA synchronism is set up. When the frame step-up occurs, both circuits 206 and 208 are reset and both FA and M synchronisms are stepped out. At the same time, the M synchronism is stepped out when the FA synchronism is stepped out. Thus both synchronisms are set up again and the M synchronism is set up again in case only this synchronism is stepped out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-frame synchronization verification circuit in I5DN.

[Prior art] Regarding the multiframe structure in ISDN, see C.
It is in CITT Recommendation I430.

FIG. 2 is a diagram showing an overview of the multiframe structure and Q-bit identification. In FIG. 0, a network terminal equipment (NT) sends a multiframe to a terminal equipment (TE). Each frame includes an FA bit and an M bit for frame synchronization, the FA bit has a content of “1” every 5 frames, and the M bit has a content of “1” every 5 frames.
It has a content of "1" for every 0 frames. The TE identifies the first frame of a multiframe with the M bit=1 and sends the Qn bit to the NT in frames with the FA bit=1 while synchronization is established. Also, while out of synchronization, “O
In order to obtain and maintain this synchronization, the TE needs to perform M synchronization (synchronization of M bit = 1 and FA bit = 1) and FA synchronization (FA bit = 1).

[Problems to be Solved by the Invention] However, conventionally, a multi-frame synchronization verification circuit that achieves the above with high reliability has not been disclosed.

The present invention has been made in view of the background of the prior art described above, and its purpose is to propose a multi-frame synchronization verification circuit that can perform highly reliable synchronization verification with a simple configuration.

[Means for Solving the Problems] In order to achieve the above object, the multi-frame synchronization verification circuit of the present invention includes a first frame synchronization means that receives a bit string having a multi-frame configuration and synchronizes each frame;
a second frame synchronization means that detects a first predetermined bit of each first predetermined number of frames and synchronizes the first predetermined number of frames; A second predetermined bit of every predetermined number of frames is detected and the second predetermined bit is detected.
a third frame synchronization means for synchronizing frames every predetermined number of frames, the second frame synchronization means is activated by synchronization establishment of the first frame synchronization means, and the third frame synchronization means The general outline is that the frame synchronization means is activated by establishing synchronization between the first and second frame synchronization means.

[Operation] In this configuration, the first frame synchronization means receives a bit string having a multi-frame configuration and synchronizes each frame. The second frame synchronization means detects a first predetermined bit of each first predetermined number of frames and synchronizes the first predetermined number of frames. The third frame synchronization means detects a second predetermined bit of a second predetermined number of frames larger than the first predetermined number, and synchronizes the second predetermined number of frames. The second frame synchronization means is activated by the establishment of synchronization of the first frame synchronization means, and the third frame synchronization means is activated by the synchronization established by the first frame synchronization means.
Activated by the establishment of synchronization of the frame synchronization means.

[Description of Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[First embodiment] In the first embodiment, the FA bit is “1” and the M bit is “l”.
Multi-frame synchronization verification is performed with a simple configuration by checking ``.

FIG. 1 is a diagram showing a multi-frame synchronization verification circuit of the first embodiment. In the figure, a frame synchronization detection circuit 204 manually detects synchronization of the frame by manually inputting the frame signal, and outputs a frame synchronization detection signal indicating the presence or absence of frame synchronization. 205 is an FA counter circuit, which outputs a gate signal a (=1) by counting 5 frames after inputting each received FA signal=1. 206 is an FA synchronization protection circuit, and gate signal a=1
The contents of the received FA signal are taken into the internal shift register at the timing of . When the content of the received received FA signal is "1" three times in a row, it is determined that the FA synchronization is established, and when it is "0" twice in a row, it is determined that the FA synchronization is out of synchronization. Outputs an FA synchronization detection signal indicating this.

This synchronous/asynchronous determination method takes into consideration erroneous reception of FA bits due to noise or the like.

207 is an M counter circuit which outputs a gate signal b (=1) by counting 2o frames after receiving the received FA signal and the received M signal simultaneously. 208
is an M synchronization protection circuit, which captures the content of the received M signal into the internal shift register at the timing of gate signal b=1, and when the content of the captured received M signal is "1" three times in a row, It is determined that the M synchronization is established, and when it is "0" twice in a row, it is determined that the M synchronization is out, and an M synchronization detection signal to that effect is output.

Further, a negative signal of the frame synchronization detection signal is led to the FA synchronization protection circuit 206. This enables the operation of the FA synchronization protection circuit 206 when frame synchronization is achieved, and resets the FA synchronization protection circuit 206 when frame synchronization is lost. Further, each negative signal of the frame synchronization detection signal and the FA synchronization detection signal is led to the M synchronization protection circuit 208. As a result, the M synchronization protection circuit 208 is enabled when frame synchronization and FA synchronization are established, and the M synchronization protection circuit 208 is reset when frame synchronization or FA synchronization is lost.

FIG. 3 is a timing chart of the received FA signal and the received M signal in the first embodiment. In the figure, a frame signal is received from the line side.

There are an FA bit and an M bit at predetermined positions in one frame signal. The received FA signal is a signal that is set when the FA bit=1 and reset when the FA bit=O. Receive M
The signal is a signal that is set when M bit=1 and reset when M bit=0.

FIG. 4 is a timing chart illustrating the operation of establishing FA synchronization in the first embodiment. It is assumed that frame synchronization is achieved. In state 1, FA counter circuit 2
05 is count loaded (
1st, 2nd, and 3rd gate signals a by counting the subsequent 5 frames.
occurs. If the received FA signal is "1" at these three consecutive gate timings, the FA synchronization detection signal becomes "1" in state 2. Also, if synchronization is lost for some reason and the received FA signal is "0" at two consecutive gate timings, the FA synchronization detection signal is "O" in state 3.
become.

Note that the M synchronization test is performed in the same manner as above by setting the count number to 20.

FIG. 5 is a diagram showing the mutual relationship between frame synchronization, FA synchronization, and M synchronization in the first embodiment. In FIG. 0, in state 1, frame synchronization is established.

This enables the FA synchronization protection circuit 206 to operate and starts the FA synchronization verification. In state 2, FA synchronization is established. This enables the M synchronization protection circuit 20B to operate, and the M synchronization verification is started. In state 3, M synchronization is established. This completes the establishment of multiframe synchronization. In state 4, frame synchronization is lost for some reason, so F
The A synchronization protection circuit 206 and the M synchronization protection circuit 208 are reset, and FA synchronization and M synchronization are removed.

In state 5, FA synchronization is lost for some reason, so M synchronization is lost. In this case, FA synchronization and M synchronization can be re-performed, and in state 6, only M synchronization is out of order for some reason. In this case, all you have to do is perform M synchronization again.

[Second Embodiment] In the second embodiment, a strict multi-frame synchronization test is performed by inspecting the FA bit pattern of a plurality of consecutive frames and the M bit pattern of a plurality of consecutive frames.

FIG. 6 is a block diagram of a multi-frame synchronization verification circuit according to the second embodiment. Note that components equivalent to those in FIG. 1 are given the same numbers and their explanations will be omitted. In the figure, reference numeral 112 denotes an FA synchronization pattern verification circuit, which accumulates the contents of the received FA signal for five consecutive frames and examines the pattern.

113 is an M synchronization pattern verification circuit, and 20 consecutive
The contents of one frame's worth of received M signals are accumulated and their patterns are inspected.

FIG. 7(A) is a circuit diagram showing details of the FA synchronization pattern verification circuit 112 of the second embodiment.

In the figure, 112-1 is a five-stage shift register;
2-2 is an AN with 4 inverters, 112-3 is a 5-person AN
This is the D gate. The received FA signals for each frame are sequentially shifted into the shift register 112-1. In this way, the output FA synchronization pattern detection signal C is transferred to the shift register 112.
-1 becomes "1" when the oldest content is [1, O, O, O, O].

FIG. 7(B) shows the M synchronization pattern verification circuit 1 of the second embodiment.
13 is a circuit diagram showing details of FIG. In the figure, 113-
1 is a 20-stage shift register, 113-2 is a 19-inverter, and 113-3 is a 20-manpower AND gate. The received M signal for each frame is transferred to the shift register 113-1.
Shift in sequentially. In this way, the output M synchronization pattern detection signal d becomes "1" when the contents of the shift register 113-1 are [1, O, O, O, . . . , O] (7) from the oldest one.

FIG. 8 is a timing chart explaining the FA synchronization verification operation of the second embodiment. In the figure, received FA signal = 1
When the FA counter circuit 205 receives the count load (
reset). The FA counter circuit 205 outputs 0.1, 2, 3, 4, etc. according to the subsequent frame signals. O (load), 1°2.3.4. ...and count. When the count value=4, it is the timing of the signal a=1. The FA synchronization pattern verification circuit 112 outputs a signal c=1 when the contents of the shift register 112-1 are [1, O, O, 0, 03. As a result, if FA synchronization is established, FA
The synchronization protection circuit 206 stores the first (a=1*c=1). In this way, if this synchronized state continues, the second,
Accumulate the third (a=1*c=1). When the FA synchronization protection circuit 206 accumulates the third consecutive signal (a=1*c=1), it determines that FA synchronization is established and outputs "1" as the FA synchronization detection signal. And as long as this synchronization state continues, F
Outputs the A synchronization detection signal '1'.

Further, when the FA synchronization pattern [1, O, O, O, O] cannot be detected at the timing of signal a=1 for some reason, the signal C=O. The FA synchronization protection circuit 206 is the first (
a=1*c==o) is accumulated. This is the case when synchronization is lost or when synchronization is achieved but the FA bit specified in the ISDN multiframe is not received. However, in the first case (a=1*c=o), it is not determined that synchronization has been lost. This is to prevent malfunctions due to noise.

However, if this asynchronous state continues, the second (a
=1*c=o). When the FA synchronization protection circuit 206 accumulates the second consecutive (a=1*c=o), it determines that the FA synchronization has been lost, and outputs the FA synchronization detection signal "O".

Note that the same applies to the M synchronization verification operation, except that the signal a=1 at a count value of 19.

[Effects of the Invention] As described above, according to the present invention, synchronization is established separately and a predetermined priority is given to these operations.
The configuration is simple, the operation is reliable, and multi-synchronization can be established and re-established smoothly.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the multi-frame synchronization verification circuit of the first embodiment, Fig. 2 is a diagram showing an overview of the multi-frame structure and Q-bit identification, and Fig. 3 is a diagram showing the received FA signal and reception of the first embodiment. A timing chart of the M signal; FIG. 4 is a timing chart explaining the operation of establishing FA synchronization in the first embodiment; FIG. 5 is a diagram showing the interrelationship between frame synchronization, FA synchronization, and M synchronization in the first embodiment; FIG. 6 is a block diagram of the multi-frame synchronization verification circuit of the second embodiment, FIG. 7(A) is a circuit diagram showing details of the FA synchronization pattern verification circuit 112 of the second embodiment, and FIG. 7(B) is the M synchronization pattern verification circuit 1 of the second embodiment.
FIG. 8 is a timing chart explaining the FA synchronization verification operation of the second embodiment. In the figure, 204... frame synchronization detection circuit, 205...
・FA deer 92 circuit, 112...FA synchronization pattern verification circuit, 206...FA synchronization protection circuit, 207...
M counter circuit, 113...M synchronization pattern verification circuit, 208...M synchronization protection circuit.

Claims (1)

[Scope of Claims] First frame synchronization means that receives a bit string having a multi-frame configuration and synchronizes each frame; a second frame synchronization means for synchronizing frames every predetermined number of frames; a third frame synchronization means for synchronizing each frame; the second frame synchronization means is activated by synchronization establishment of the first frame synchronization means; and the third frame synchronization means synchronizes the first frame synchronization means. A multi-frame synchronization verification circuit characterized in that it is activated by establishing synchronization between first and second frame synchronization means.