JPS6323437A - Synchronous detecting circuit - Google Patents

Abstract

PURPOSE:To reduce the synchronous locking time by providing plural synchronizing pulse train pattern detection circuits. CONSTITUTION:When any of pattern detection circuits 21, 22-2p detects a pattern, a pattern detection signal S1 is fed to a clock blocking circuit 4 via an OR circuit 3, the gate closing is released to input a clock pulse to a frame counter 5. In receiving the pulse, the frame counter 5 gives a synchronous detecting trigger S2 to pattern detection circuits 21, 22,-2P after m-bit to command the pattern collation. Since the frame counter 5 is an m-bit counter, an output being the frequency division of the input pulse by 1/m appears and the result is frequency-divided further into 1/r by a multi-frame counter 6. On the other hand, a pattern sequencing circuit 7 receiving the output of the pattern detection circuits 21, 22-2p detects which synchronizing pulse train pattern is to be collated and the result is loaded to the multi-frame counter 6, which receives it and sends a frame phase signal S3 to the reception section.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a synchronization method for a communication device having a frame structure in which frame synchronization pulses are distributed, and the present invention relates to a synchronization method for a communication device having a frame structure in which frame synchronization pulses are distributed. The present invention relates to a synchronization detection circuit that reads out and matches a predetermined pattern.

BACKGROUND OF THE INVENTION In order to perform digital communication, a frame structure is determined in order to match the phase of codes, and a frame synchronization pulse for synchronization is placed at a determined position within the frame structure. Depending on how the synchronization pulses are arranged, there are two methods: (a) jump method and (b) sequence method.

As shown in Figure 2(a), the jumping method uses m bits for 1
When frames are constructed and one multiframe is composed of r frames, the shaded position in the figure is determined as the synchronization pulse arrangement position, and for example, when r = 4, 0100 is predetermined as the synchronization pulse pattern. An example of a synchronization pulse detection circuit using this jumping method is shown in FIG. In the figure, 1 is a storage circuit with r shift registers 11 + 12 m...-1
From r to υ, 1. , 1. , . . . -1r are all m-bit shift registers. (However, this does not necessarily have to be a shift register.) 1 or O signals for every m bits of the input pulse signal are output to the r output terminals of the memory circuit 1, and this output signal is shifted over time. I'm going to go. When this output reaches 0100 from the bottom, it is determined in advance.

If the synchronization pulse train pattern is 0100, the pattern detection circuit 2 outputs a pattern detection signal Sl indicating that the comparison matches, and opens the gate of the clock blocking circuit 4. When the gate opens, the clock pulse causes the multi-frame counter 8 to operate, outputs the synchronization detection trigger signal S2 after N bits, and causes the pattern detection circuit 2 to perform verification. Since the output of the memory circuit 1 is 0100 for every N bits, the gate of the clock blocking circuit 4 is opened each time, the clock signal is inputted to the multi-frame counter 8, and the synchronization detection trigger S2 is given to the pattern detection circuit 2. A match is made. By repeating this, synchronization with the input pulse signal is achieved.

Once synchronization is achieved, an input pulse signal and various clock pulses are sent to the receiver.

Problems to be Solved by the Invention The above-described jump-type synchronization detection circuit cannot perform verification unless the input pulse is shifted by one multiframe (N bits). Therefore, a time delay of at least N bits occurs. Also in the case of the sequence method shown in FIG. 2(b), even if the predetermined synchronization pulse train pattern is, for example, 0100, it is not possible to immediately determine that matching is complete upon receiving this pattern. The reason is that 0100 can also exist in the information pulse. That is, it must be confirmed that 0100 appears every N bits. Therefore, this method also requires at least N bits of time for verification.

As described above, the conventional synchronization detection circuit has the drawback of causing a time delay of at least N bits.

Means to Solve the Problem In a digital communication device in which one frame is composed of m bits, one multiframe is composed of r frames, and a synchronization pulse is placed at a predetermined position in each frame, m bits of input pulses are used. A memory circuit that outputs each pulse in parallel, a plurality of pattern detection circuits that can each check multiple types of synchronous pulse patterns based on the output of this memory circuit, and an OR output of the outputs of these pattern detection circuits. A clock blocking circuit that gates clock pulses using the output of this OR circuit, and a clock blocking circuit that divides the output pulse of this clock blocking circuit by 1/m and collates the synchronizing pulse pattern with each of the pattern detection circuits. A frame counter that sends out a synchronization detection trigger signal that means
A synchronization detection circuit includes a multi-frame counter that divides the frequency, and a pattern sequence circuit that loads which synchronization pulse train pattern has been matched upon receiving the output of the pattern detection circuit into the multi-frame counter and sends a frame phase signal to the receiving section. was constructed.

Function: Since the synchronization detection circuit of the present invention is configured as described above, it is possible to match many types of synchronization pulse patterns, whereas in the conventional circuit, matching could not be performed without waiting for one multiframe (N bits). In the circuit of the present invention, the number of pattern detection circuits is, for example, r, and pattern detection circuits whose matching patterns are shifted by one bit are provided.
, N/r=m bits, the matching of the synchronization pulse train pattern is completed, and the receiving section can immediately enter the synchronization state.

Example Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. The input pulse signal consists of 1 frame with m bits and 1 frame with r frames.
Since it composes a multi-frame, one multi-frame is N.
(N=mr) bits. In the figure, 1 is a memory circuit that outputs signals for every m bits of input pulses in parallel, 21+22 . ...2p is a pattern detection circuit that checks whether this output matches a predetermined pattern. Conventionally, only one type of this circuit was provided, but in the present invention, a plurality of (p) types of this circuit are provided. ) established.

For example, if 2x is 0100, then 2□ is 10.
00.23 is predetermined to detect a pattern shifted one bit at a time, such as 0001, . . . . For example, synchronous pulse train pattern to 100
If this is the case, 0100 appears in the output of the memory circuit every N bits of the input pulse, and the pattern detection circuit 21 collates and detects this. Then, after m bits, the pattern detection circuit 22 reads 1000, and after another m bits, 23 becomes 0.
001 is collated and detected. Pattern detection circuit 2. , 22
, . . 2p detects a pattern, it sends a pattern detection signal Sl to the clock blocking circuit 4 via the OR circuit 3, releases the gate closure, and inputs a clock pulse to the frame counter 5. In response to this, the frame counter 5 sends a synchronization detection trigger S2 to the pattern detection circuit 21*22+...2p after m bits to instruct pattern matching.

Since the frame counter is a counter of sVim bits, an output obtained by frequency-dividing the input pulse by 1/m appears, which is further divided by the multi-frame counter 6 into l/r. On the other hand, pattern detection circuit 2. .

In response to the outputs of 2h, .

In response to this, the multi-frame counter 6 sends a frame phase signal S3 to the receiving section.

Since the synchronization detection circuit of the present invention is configured as described above, the receiving section enters the synchronization state earlier than in the case of the conventional method. In other words, as mentioned in the section on conventional technology, in the conventional method it takes one multiframe (N bits), usually more, to achieve synchronization even in the best of circumstances. According to the invention, the pattern detection circuit 2
1, 2! If any of L...-2p matches the synchronization pulse train pattern, the receiver enters the synchronization state. The time required to enter synchronization is the pattern detection circuit 21, 2□,...
The larger the number of 2p, the shorter it becomes. p=r
In this case, the time required for the conventional method is l/r.

Effects of the Invention In a digital communication system, synchronization must be achieved between transmitting and receiving in order to match the phases of codes, but the time it takes to achieve this synchronization is a loss. According to the present invention, by providing a plurality of synchronization pulse train pattern detection circuits, there is an advantage that the synchronization pull-in time can be significantly shortened.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the synchronization detection circuit of the present invention, and FIG.
The figure is a diagram for explaining a general synchronization pulse train, and FIG. 3 is a circuit diagram of an example of a conventional synchronization detection circuit. l...Memory circuit, 2, 21, 2□,...2p
... Pattern detection circuit, 3 ... OR circuit, 4 ... Clock blocking circuit, 5 ...
Frame counter, 6... Multi-frame counter, 7... Pattern sequential circuit, 8...
・Multi-frame counter, Sl...Pattern detection signal, S2...Synchronization detection trigger, S3...
...Frame phase signal. :d tatetsuri 7 Figure 2 Figure 3

Claims (1)

[Claims] In a digital communication device in which m bits constitute one frame, r frames constitute one multiframe, and synchronization pulses are placed at predetermined positions in each frame, pulses for every m bits of input pulses are output in parallel. A memory circuit, a plurality of pattern detection circuits capable of receiving the output of the memory circuit and collating a plurality of types of synchronization pulse train patterns, an OR circuit for obtaining an OR output of the outputs of these pattern detection circuits, and the OR circuit. A clock blocking circuit gates a clock pulse by the output of the clock blocking circuit, and a clock blocking circuit divides the frequency of the pulse outputted by this clock blocking circuit by 1/m and sends a synchronization detection trigger signal to each of the pattern detection circuits, which means to check a synchronization pulse train pattern. a multi-frame counter that further divides the output of this frame counter by 1/r; and a receiving section that receives the output of the pattern detection circuit and loads information on which synchronization pulse train pattern has been matched into the multi-frame counter and sends it to the receiving section. A synchronization detection circuit consisting of a pattern sequential circuit that sends out a frame phase signal.