JPH02305130A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To reduce and simplify the circuit scale by detecting only part of a pattern in a frame pattern till synchronization is taken. CONSTITUTION:A noncoincidence state detection signal 38 is inputted to an out of synchronism confirming circuit 21 and when the signal is counted by a preset number of times, an out of synchronism confirming signal 42 is fed to a terminal S of a set/reset circuit 22. Thus, an out of synchronism state signal 44 representing out of synchronism is outputted from an output terminal 23 of the set/reset circuit 22. The number of times of the count is set in response to an error rate of a data bit and when it is set larger, the discrimination accuracy of out of synchronism is improved. Thus, the circuit scale is reduced and simplified.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a frame synchronization circuit, and in particular, when performing multiplex data transmission, synchronization is performed for a data signal having a frame pattern inserted at predetermined bit intervals. This paper relates to a frame synchronization circuit that takes

[Conventional technology]

Conventionally, as this type of frame synchronization circuit, CCITT (
X according to the recommendations of the International Telegraph and Telephone Advisory Committee).

A 50 frame synchronization circuit is often used.

In this x, 50 frame synchronization circuit, 20 bits of x
, 50 frame patterns are inserted every 8 bits to synchronize with the input data signal.

For example, as shown in FIG. 2, d+Sds, d+t, .
...A total of 20 bit frame patterns are arranged at the position dl, 3.

Conventionally, a multi-point monitoring method has been used as a means to monitor such input signals and achieve frame synchronization, and by detecting and monitoring the 20-bit frame pattern inserted into the human signal at once, the frame They were in sync.

[Problem to be solved by the invention]

In this way, in conventional frame synchronization circuits, frame synchronization is achieved by simultaneously monitoring and detecting all bits of the entire frame pattern inserted into the input signal, which has the disadvantage of complicating the circuit. was there.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a simple frame synchronization circuit which is smaller in circuit scale than the conventional multi-point monitoring frame synchronization circuit.

[Means to solve the problem]

In the present invention, (i) extraction means for extracting a part of the frame pattern inserted into the input data signal;
) synchronization means for synchronizing frames using a part of the frame pattern extracted by the extraction means;
) The frame synchronization circuit is provided with monitoring means for monitoring the entire frame pattern at a stage when frame synchronization is achieved by the synchronization means.

In the present invention, synchronization is achieved by first extracting a frame pattern of a predetermined number of bits from among all frame patterns, and thereafter the synchronization state is monitored by monitoring all frame patterns.

〔Example〕 Hereinafter, the present invention will be described in detail with reference to Examples.

FIG. 1 shows a frame synchronization circuit in one embodiment of the present invention.

In this circuit, a human input data signal 31 inputted from an input terminal 11 passes through a buffer circuit 12 to a Dl of a memory circuit 13.
It is becoming more and more human-powered.

The data signal 32 read from the memory circuit 13 and ~D7 is sent to the flip-flop 14 and the buffer circuit 1.
2 to D2 to D of the memory circuit 13 described above. This buffer circuit 12 is controlled to be high impedance while reading from the memory circuit 13. The buffer circuit 12, the memory circuit 13, and the flip-flop circuit 4 are supplied with a manually input clock signal 33 from the clock input terminal 24.

A1 to A3 of the memory circuit 13 are connected to a divide-by-8 counter 15, and an address signal 39 is used when reading and writing data.
is input. Also, D+ -Do of the memory circuit 13
The data signal 35 read out is supplied to the first pattern detection circuit 16. This first pattern detection circuit 1
The coincidence state detection signal 36 from G is input to the second pattern detection circuit 18 and at the same time is also input to the reset terminal R of the set reset circuit 22 via the synchronization confirmation circuit 17.

This set/reset circuit 22 is composed of an SR flip-flop or the like.

The memory circuit 13 is connected to a 12-stage shift register 19, and each stage is connected to a second pattern detection circuit 18. The mismatch state detection signal 38 from the second pattern detection circuit 18 is supplied to the set terminal S of the set reset circuit 220 via the out-of-synchronization confirmation circuit 21, and a discrimination signal is output from the output terminal 23 of the set reset circuit 22. It is now possible to do so.

The operation of the frame synchronization circuit configured as above will be explained.

First, the operation up to the stage of synchronizing with the input data signal will be explained.

The input data signal 31 is input from the input terminal 11, temporarily stored in the buffer circuit 12, and then sequentially input to Dl of the memory circuit 13. This human data signal 31 is
As shown in Figure 2, di, a,
, dl7, ......, 20 in total at the position of dl,3
A frame pattern of bits is arranged.

FIG. 3 is for explaining the movement of data within the memory circuit 13.

Addresses (D, , Bl) of the memory circuit 13 The manually input data signal 31 is incremented by the address signal 39 from the divide-by-8 counter 15, which changes at a predetermined timing, and becomes the address (D+
, BI) to (D, , Be) in the same row address. Then, depending on the timing that follows, addresses (D+, Bs) to (D7,
The data (No. 1 32) sequentially read from B, ') are input to Dl to D of the flip-flop circuit 14, respectively.
When data is manually input to all of ~D, the gates of the flip-flop circuit 14 and the buffer circuit 12 are opened at the timing of the clock signal 33, and the data signal 32 output from Q, ~Q, passes through the buffer circuit 12. It is input to D2 to D8 of the memory circuit 13.

In this way, the address (
The data of D+, Be) to (D7, Bs) are respectively addressed to (D2, Be) to (D,
, Ba), and thereafter moves in the same row address in the same manner.

On the other hand, the address (D+,
The 8-bit data signal 35 sequentially read from Ba) to (Da, B-) is input to the first pattern detection circuit 16 and compared with 8 bits of the 20-bit frame pattern.

In this way, the memory circuit 13 can store 8 of the human input data signal 31.
It operates in the same way as a shift register that shows each bit.

Then, as shown in FIG. 3, 8-bit data d1, d2, . . . of the 20-bit frame pattern.
When d411Sd57 is located at the address indicated by the arrow in the memory circuit 13, the first pattern detection circuit 16 detects an 8-bit frame pattern and outputs a -dispersed state detection signal 36.

This scattered state detection signal 36 is input to the synchronization confirmation circuit 17, and when it is counted a preset number of times,
A synchronization confirmation signal 41 is supplied to the terminal R of the set-reset circuit 22.

As a result, the output terminal 23 of the set-reset circuit 22 outputs a synchronization state signal 43 indicating that synchronization is achieved. The number of times this count is performed is set according to the error rate of data bits, and by setting this number to a large value, it is possible to improve the accuracy of determining that synchronization has been achieved.

Next, the operation after synchronization with the input data signal is established will be explained.

In a synchronized state, the bit positions of the frame pattern included in the input data signal 31 are known, so the remaining frame patterns can be extracted from the input data signal 31 every 8 bits. Then, this remaining frame pattern, that is, the 9th bit to the 2nd bit
12 bits of data up to bit 0 are stored in shift register 1.
9 and stored manually. These 12-bit wide data signals 37 are then used in the second pattern detection circuit 1.
8 is input.

On the other hand, the second pattern detection circuit 18 receives the coincidence state detection signal 36 output from the first pattern detection circuit 16.
is also entered. Therefore, this second pattern detection circuit 18 ends up monitoring the entire frame pattern of 20 bits, and outputs a mismatch state detection signal 38 when frame synchronization is lost.

This mismatch state detection signal 38 is transmitted to the out-of-synchronization confirmation circuit 2.
1, and when it is counted a preset number of times, an out-of-synchronization confirmation signal 42 is supplied to the terminal S of the IJ upper set path 22.

As a result, an out-of-synchronization state signal 4 indicating that the synchronization is out is output from the output terminal 23 of the set-reset circuit 22.
4 is output. The number of times this count is performed is set according to the error rate of data bits, and by setting this number to a large value, it is possible to improve the accuracy of determining that synchronization has been lost.

In the manner described above, a signal representing a synchronization state or an out-of-synchronization state with respect to the human input data signal is obtained.

〔Effect of the invention〕

As described above, according to the frame synchronization circuit of the present invention, only a part of the frame pattern is detected until synchronization is achieved, so that the circuit scale can be reduced and simplified. Therefore, there is an effect that the cost of the circuit can be reduced.

[Brief explanation of drawings]

The drawings are for explaining one embodiment of the present invention, of which Fig. 1 is a circuit diagram showing a frame synchronization circuit, and Fig. 2 is a circuit diagram showing a frame synchronization circuit.
The figure is an explanatory diagram showing the structure of the human input data signal, and FIG. 3 is an explanatory diagram showing the movement of data within the memory circuit 13 of FIG. 1. 11...Input terminal, 12...Buffer circuit, 13...Memory circuit, 14...Flip-flop circuit, 15...
...8 frequency division counter, 16...First pattern detection circuit, 17...
... Synchronization 1i11 recognition circuit, 18 ... Second pattern detection circuit, 19 ... Shift register, 21 ... Out-of-synchronization confirmation circuit, 2 2 ...
... Seso Tori Sesoto Circuit
, 23... Output terminal.

Claims (1)

[Scope of Claims] Extraction means for extracting a part of the frame pattern inserted into the input data signal; synchronization means for performing frame synchronization using the part of the frame pattern extracted by the extraction means; A frame synchronization circuit comprising: monitoring means for monitoring the entire frame pattern at a stage when frame synchronization is achieved by the synchronization means.