JPH04280525A - Bit collation circuit - Google Patents

Abstract

PURPOSE:To reduce a synchronism recovery time by shifting bits of an input signal by a bit number in matching with an appearance timing of plural bits detected by an information confirming circuit and comparing the bits. CONSTITUTION:An n-bit information latch circuit 7 latches n-bit information from an input signal and fed to an n-bit information confirmation circuit 9. The circuit 9 finds out the n-bit information in a distuff signal and generates an n-bit information pulse P3 representing a timing position of the information and sends it to a missing clock generating circuit 8. The circuit 8 generates a missing clock by a phase difference between the pulse P3 and n-bit information pulse P2 obtained by delaying an n-bit information pulse P1, and the clock is given to a memory circuit 3 as a read clock, which implements phase matching. A bit comparator circuit 4 compares bits to detect an error, and an error counter 6 outputs a bit error data.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a bit matching circuit.
In particular, the present invention relates to a bit matching circuit for detecting errors in a circuit that performs stuff synchronous digital signal processing.

0002

2. Description of the Related Art A conventional bit matching circuit of this type repeats the operation of comparing an input signal and an output signal bit by bit, and if they do not match, shifting the input signal by 1 bit and comparing again.

FIG. 3 is a block diagram of a conventional bit matching circuit that operates as described above.

In the figure, an input signal is synchronized by a stuff synchronization circuit 1 to an output clock asynchronous to the input clock, and becomes an output signal. In order to detect bit errors occurring in the stuff synchronization circuit 1, a bit comparison circuit for input signals and output signals is implemented as follows.

First, the output signal of the stuff synchronization circuit 1 is
In order to compare each bit with the input signal, the destuff circuit 5 synchronizes it with the input clock. Further, the input signal is sent to a bit comparison circuit 4 through a delay circuit 2 for compensating the delay time in the stuffing synchronization circuit 1 and the destuffing circuit 5 and a memory circuit 3 in order to compare it with the output signal. The bit comparison circuit 4 compares this signal with the output signal of the destuffing circuit 5 bit by bit to check for errors. The error counter 6 is connected to the bit comparison circuit 4.
generates bit error data by counting the pulses emitted when an error is detected. For example, if a bit error rate of 10-3 or more is detected, it is determined that the state is out of synchronization, that is, the phase of the input signal and the output signal are shifted, and a signal indicating out of synchronization is sent to the synchronization protection circuit 11. is sent, a 1-bit toothless clock generation circuit 10 generates a toothless clock, which is applied as a read clock to the memory circuit 3, and the input signal to the bit comparison circuit 4 is shifted backward by one bit. In this way, bit comparison is performed while shifting the input signal one bit at a time until a synchronized state is achieved.

[0006]

[Problems to be Solved by the Invention] In the conventional bit matching circuit described above, when a predetermined bit error rate is exceeded, the bit error rate is changed each time by shifting one bit to match the phase of the input signal and the output signal. The disadvantage is that it takes too much time to return to synchronization.

[0007]

[Means for Solving the Problems] The bit matching circuit of the present invention compares the bits of an input signal with a destuffing signal of an output signal obtained by stuff-synchronizing the input signal and detects out-of-synchronization due to a bit error in the output signal. , a bit matching circuit that shifts the input signal and compares the bits until synchronization is recovered when out-of-synchronization is detected; an information holding circuit that periodically holds a plurality (n) bits of the input signal; and an information confirmation circuit that detects a portion that matches the plurality of (n) bits of the information confirmation circuit, and the input signal is shifted by a number of bits matching the appearance timing of the plurality of (n) bits detected by the information confirmation circuit. It is characterized by bit comparison.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. The output signal obtained by stuff-synchronizing the input signal with the stuffing synchronization circuit 1 is returned to a destuffing signal synchronized with the input clock in the destuffing circuit 5 for comparison with the input signal. Further, the input signal is passed through a delay circuit 2 and a memory circuit 3 for compensating for the amount of delay in the stuffing synchronization circuit 1 and the destuffing circuit 5 in order to match the phase with the output signal. Further, the input signal is held as n-bit information by the n-bit information holding circuit 7 and sent to the n-bit information confirmation circuit 9, and an n-bit information pulse indicating the timing position of the n-bit is sent to the delay circuit 2. It will be done.

The n-bit information confirmation circuit 9 searches for n-bit information in the destuff signal, generates an n-bit information pulse P3 indicating the timing position of this information, and sends it to the blank clock generation circuit 8. In the toothless clock generation circuit 8,
By creating a clock that is sharp by the phase difference between the n-bit information pulse P3 and the n-bit information pulse P2 obtained by delaying the n-bit information pulse P1 with the delay circuit 2, and giving it to the memory circuit 3 as a read clock. , the phases of the n-bit information portions of the input signal and the output signal are matched.

The bit comparison circuit 4 compares the bits of the input signal and the output signal to detect errors. Further, the error counter 6 counts the pulses sent by the bit comparator circuit 4 when an error is detected, and outputs bit error data indicating the number of bit errors.

FIG. 2 is a block diagram showing an example of the configuration of the n-bit information confirmation circuit 9 in this embodiment. The output signal of the destuffing circuit 5 is converted into parallel n bits by the shift register circuit 91, and the n
The bit information is compared with the n-bit comparator circuit 92, and a pulse is output when both match in all n bits. The pulse comparison circuit 93 uses the n bit synchronization generated by the n bit pulse generation circuit 94 to indicate the n bit position.
When the timings of the bit pulse and the pulse given from the n-bit comparison circuit 92 match, a pulse indicating a synchronized state is sent to the synchronization protection circuit 95, and the pulse suppression circuit 96 outputs an n-bit information pulse P3. On the contrary, when the timings of the n-bit pulse and the output pulse of the n-bit comparison circuit 92 do not match, it is assumed that the synchronization is out of synchronization, and the synchronization protection circuit 95 also determines that the synchronization is out of synchronization, and the pulse suppression circuit 96 The output of the n-bit information pulse P3 is stopped. At the same time, the n-bit pulse generation circuit 94 is also made to stop outputting n-bit pulses and n-bit information pulses.

The n-bit comparator circuit 92 continues to operate even when the synchronization is out of order, and when it detects a match of n bits, it generates an n-bit pulse n-bit information pulse A at the same timing.
2 is output from the n-bit pulse generation circuit 94, the output pulse of the pulse comparison circuit 93 indicates that the out-of-synchronization state has been released, and in response, the n-bit pulse generation circuit 94 outputs the
A bit pulse and an n-bit information pulse are generated in synchronization with the output pulse of the n-bit comparison circuit 92. That is, the n-bit pulse starts to be generated in m-bit synchronization, matching the n-bit position when the out-of-synchronization state is released. From now on, the pulse comparison circuit 93 continues to compare until the synchronization protection circuit 95 releases the out-of-synchronization state, and only when the synchronization protection circuit 95 releases the out-of-synchronization state, the pulse suppression circuit 96 suppresses the output. is released, starts outputting n-bit information pulse P3, and transitions to a synchronized state.

[0014]

Effects of the Invention As explained above, the present invention can restore synchronization by capturing the portion of the output signal that matches the information of multiple (n) bits in the input signal when synchronization is lost. This has the effect of making the time shorter than before.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the invention.

FIG. 2 is a block diagram of an embodiment of the invention.

FIG. 3 is a block diagram of a conventional circuit.

[Explanation of symbols]

1 stuff synchronization circuit 2 delay circuit 3 memory circuit 4 bit comparison circuit 5 destuff circuit 6 error counter 7 n-bit information holding circuit 11, 95 synchronization protection circuit 8, 10 toothless clock generation circuit 9 n
Bit information confirmation circuit 91 Shift register circuit 92 N-bit comparison circuit 93 Pulse comparison circuit 94 N-bit pulse generation circuit 96 Pulse suppression circuit

Claims (1)

[Claims] 1. A bit comparison is made between an input signal and a destuffing signal of an output signal obtained by stuff-synchronizing the input signal to detect out-of-synchronization due to a bit error in the output signal, and when out-of-synchronization is detected, the input signal is synchronized with the input signal until synchronization is recovered. The bit matching circuit that compares the bits by shifting the bits includes an information holding circuit that periodically holds a plurality of (n) bits in the input signal, and a portion that matches the plurality of (n) bits in the destuff signal. Equipped with an information confirmation circuit to detect,
A bit comparison circuit characterized in that the input signal is shifted by the number of bits matching the appearance timing of the plurality of (n) bits detected by the information confirmation circuit and the bits are compared.