JPS58161546A - Multiplex transmitter - Google Patents

Abstract

PURPOSE:To detect and correct a single error by a transmitter, by adding a multiplexing synchronizing signal generating circuit at the transmitting side and a multiplexing signal transmission error detecting circuit and a counter common with each channel at the receiving side respectively. CONSTITUTION:At the transmitting side, an error detecting signal given from a multiplexing signal error detecting signal generating circuit 32 is added to each channel signal and then transmitted as a multiplexing signal 6T. When a bit error is produced during the transmission, a multiplexing signal 6R to be received is set at 1 unlike the signal 6T only at that part. The signal 6R is received at a receiving part 7, and an error is detected by a multiplexing signal transmission error detecting circuit 35. When the circuit 35 detects an error, a counter 36 counts up thereafter synchronizing signals SYCH. Thus the contents of the counter 36 show the number of bits produced after the generation of an error. The erroneous bit is detected from the contents of the counter 36 and by an error detecting circuit 51. On the other hand, a reproduced signal is fed to the circuit 51. Thus the error of the unit bit is corrected, and a normal data 48 is delivered.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiplex transmission apparatus that multiplexes and transmits transmission signals of a plurality of channels, and particularly relates to a multiplex transmission apparatus having a function of correcting a single transmission error.

FIG. 1 shows an example of the configuration of a conventional multiplex transmission device that multiplexes and transmits a plurality of channels, and FIG. 2 is an explanatory diagram of its transmission format.

1 and 2, on the transmitting side, n multi-channel transmission signals 11 to 1n are synchronized by the synchronization signal 41 of each channel.
, data 42, and a check signal 43, which are synchronized by the bit synchronization circuit 1 with the signal from the timing generation circuit 2 to generate signals 110 to 120 .・・・・・・
After being set to 1nO, it is sampled by the multiplexer 3, and a synchronization signal 5YCH for multiplexing is output from the generation circuit 4 and added by the transmitter 5, and is multiplexed like the multiplexed signal 6 on the transmission path. be converted into Here, the multiplexing method is such that each channel's signal is taken one bit at a time, and one frame of the multiplexed signal is composed of n bits. For example, bit d of signals 110 to 1nO in FIG.
1 to d, are put in one frame of signal 6, and bit! in the next frame. , ~e, are inserted.

On the receiving side, the multiplexed signal 6 is received by the receiving section 7, and the synchronization signal 5YC detected by the multiplexed synchronization signal detection circuit 8
The transmission signals of a plurality of channels are separated by the distributor 10 according to the timing of H, and held in the data hold device 1lt30 to obtain reproduced signals 21 to 2n. Each circuit on the receiving side is synchronized with the timing generated by the timing generation circuit 9.

By the way, in one or more conventional devices, the multiplexed transmission signal 6 does not include a transmission error detection signal. For example, as shown in E in Figure 2, the fact that the data 42 (occurred in the portion corresponding to the reproduced signal) as a whole is an error means that the channel signal 11
Although it can be determined from the next check signal 43 added to the next check signal 43, there is a drawback that no correction is made in the transmission device. With this method, even for single-bit errors that occur even when the equipment is normal, if the transmission signals 11 to ln of each channel are not cyclic signals, retransmission by another means or correction is required, and the transmission It reduces efficiency.

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned drawbacks of the prior art and to provide a multiplex transmission device that allows the transmission device to detect and correct single errors.

The present invention adds a transmission error detection signal for multiplexed signals, which has not been added in the past, to the multiplexed signal, and uses this detection signal to detect transmission errors that are unique to each channel. The present invention is characterized by having a mechanism for detecting the bit position where an error has occurred from the detection time information and correcting it.

The present invention will be explained in detail below using a timing chart including an embodiment shown in FIG. 3 and a transmission format example shown in FIG.

In the configuration shown in FIG. 3, the transmission error detection signal C for multi-electrification signals is
A generating circuit 32 that generates HK is added to the transmitting side, and the receiving side includes an error detection circuit 35 for multiplexed signals, a counter 36 common to each channel, and an error detection and correction device 51 for each channel (this is Only the reproduction signal 21 is shown,
The same applies to other channels).

Therefore, as shown in Figure 4, if each channel signal 110, 120, 130, etc. to be transmitted is input as a signal that can detect errors by inverting two consecutive transmissions, this becomes a multiplexed signal. It is transmitted as a frame with a detection signal CHK inserted, as shown by 6T. If a transmission error (single error) occurs in the bit shown by E in Figure 4 during this transmission, the received multiplexed signal 6R will be 1, unlike the main signal 6T in this part. .

This signal 6R is received by the receiver 7, the synchronization signal detection circuit 8 detects the synchronization signal 5YCH, and the detection circuit 35 detects I19 as a multiplexed signal using the signal CHK. This multiplexed signal error is detected by the detection circuit 35.
When detected at time t, the counter 36 is cleared by the output, and thereafter counts up by one each time the synchronizing signal 5YCH is detected by the detection circuit 8.

However, since 1 bit corresponds to the reproduced signal 21 which is reproduced by 1 minute for each of the synchronization signals 5YCH, the contents of the counter 36 are as follows after the transmission wA#:J occurs (p)E.
It shows how many bits have passed in the reproduced signal 21. The contents of this counter 36 are the data length (8 bits in this case).
The value subtracted by the subtracter 39 from the output of the setter 38 is input to the buffer register 37, and
7 is set in the down counter 44 by the output of the end detection port w&34 at the data end time point t of the signal 21. In this case, 8-2=6 is set. This set value indicates how many bits from the beginning of the data are incorrect.

After the data end time t, the reproduction signal 210
The inverted signal portion is input, and is compared in the coincidence circuit 40 with a signal 21R, which is an inverted signal delayed by one data in a shift register 461 of one data length (8 bits).

Therefore, in the example of FIG. 4, a mismatch is detected at time t and thereafter at the 6th bit.

On the other hand, the contents of the down counter 44 are also set at time t by the clock of the channel timing generation circuit 33, so that the sympathies 6 becomes smaller and becomes 0 at the 6th bit at time t.

This is detected by the decoder 45, and the output of the decoder 45 and the output of the coincidence circuit 40 are turned on, and the AND gate 52 is turned on, and the output of the shift register 461 is inverted by the gate circuit 53 and transferred to the shift register 462.

That is, errors in unit bits of the data portion are corrected, and normal data 48 is output from the shift register 462.

At this time, the AND gate 47 does not output anything because the output of the detection circuit 35 and the output of the coincidence circuit 40 are shifted by approximately one word.

On the other hand, when a transmission error occurs at EC in FIG. 4, that is, within an inverted frame as a check signal.

The coincidence circuit 40 detects an error at this error bit position EC, and the detection circuit 35 also detects this error at the same time, so the AND gate 47 outputs a signal indicating the error, but the output of the decoder 45 is not on. Therefore, the gate circuit 53 does not invert the input to the shift register 462, and the normal data portion is output from the shift register 462 as is.

In this embodiment, it is assumed that the data lengths of the signals 11 to 1n of each channel are the same, so the counter 36 can be shared by each channel. However, if the data lengths of the channels 11 to 1n are different, This counter 36 may be provided for each channel.

As is clear from the above description, according to the present invention, by using different independent transmission error mechanisms.

The error position can be uniquely determined, and single errors can be automatically corrected by the transmission device itself.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a configuration example of a conventional multiplex transmission device, FIG. 2 is a diagram showing a transmission format in the device of FIG. 1, FIG. 3 is a diagram showing an embodiment of the present invention, and FIG. FIG. 4 is an explanatory diagram of the operation of the embodiment of FIG. 3; 11 to 1n...Channel signal, 4...Synchronization signal generation circuit for multiplexing, 6...Multiplex signal, 8...Synchronization signal detection circuit for multiplexing, 32...Error detection for multiplexed signal Signal generation circuit, 34... Data end detection circuit, 35...
Transmission error detection circuit for multiplexed signals, 36... Counter, 3
7... Buffer register, 38... Data length setter, 39... Subtractor, 40... Matching circuit, 44...
Down counter, 45...decoder, 461, 462
...Shift register, 47...Add gate, 48
...Single-error corrected data, 51...Error detection and correction device, agent Masuji IwIIIl Sendai Sho 1 1st
mouth

Claims (1)

[Claims] 1. A first means for multiplexing signals of a plurality of channels, each of which is attached with a channel check signal, and adding a multiplexing check signal to the output of the multiplexing means and transmitting the multiplexed signal to a transmission path. a transmitter comprising a second means; a third means for receiving the multiplexed signal, detecting its synchronization signal, and separating the multiplexed signal into signals of each channel to create a reproduced signal; a fourth means for detecting a single-bit transmission error occurring in the multiplexing signal using the multiplexing check signal; a fifth means for detecting the number of bits when the generated bit position in the channel is the odd position in the data of the core channel; a sixth means for detecting an error in the signal, and when the time point of the single bit error position detected by the fifth means coincides with the time point when the error is detected in the reproduced signal by the sixth means; and seventh means for determining that a single error bit of a reproduced signal is an error in the data portion and correcting the error bit.