JP3005435B2 - Magnetic recording / reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic recording / reproducing apparatus, and more particularly to a digital signal magnetic recording / reproducing apparatus used for a digital VTR for recording / reproducing digital data such as a digital video signal.

[0002]

2. Description of the Related Art Consumer digital VTRs for recording and reproducing digital data such as digital video signals are disclosed in, for example, Nikkei Electronics Book "Data Compression and Data Modulation", p. 137 ~
p. 150. FIG. 18 is an illustrative view showing a magnetic tape as viewed from a surface in contact with a magnetic head in order to show a recording format in such a VTR. The magnetic head scans from the bottom to the top of a recording track.

[0003] Four types of data are recorded on one track. These data are insert data, track information, audio data, video data, and subcode data in the order in which the magnetic head scans. As shown in FIG. 19, there are 10 such tracks (FIG.
(In the case of the TSC system, in the case of PAL and SECAM, the number is 12) Collectively, an image of one frame is formed. The video data is recorded as 135 sync blocks per track (FIG. 19), each of which is numbered 0, 1,..., 134 to represent track 0, and shows the arrangement of the blocks. FIG. 20 shows a detailed data format of one of the blocks.

[0004] That is, each block has video data (DATA) and its data parity (DATA PA).
RITY), a synchronizing signal (SYNC), an ID signal (ID) having information such as a block number, and a parity signal (IDP) of the ID signal are added to form an array as shown in FIG. In this synchronization signal, a 16-bit fixed pattern signal composed of a predetermined combination of 0 and 1 is recorded. When a signal of this fixed pattern is detected during reproduction, a synchronization signal (detected synchronization signal: FIG. 21), which is used as a reference signal for signal processing. However, since the signal of the fixed pattern has a finite number of bits (2 bytes), the same pattern signal may appear in the data bit string, and this is detected as an error synchronization signal. Further, the synchronization signal may be lost due to a scratch on the recording medium.

In order to prevent erroneous detection or omission of the synchronizing signal, a method as shown in FIG. 21 has conventionally been used, that is, a gate signal having an arbitrary width has been created, and a mask has been masked during periods other than the gate. In addition, when there is no synchronization signal in the gate, a method of protecting the synchronization with a protection synchronization signal created by a counter is used. This operation will be described with reference to the conventional magnetic recording / reproducing apparatus 1 shown in FIG.

A reproduction signal input from an input terminal 1a is amplified by a preamplifier 1b, demodulated by a demodulator 1c, and then a predetermined synchronization signal pattern is detected by a synchronization signal detection circuit 1d. A clock is generated by giving the output from preamplifier 1b to PLL circuit 1b '. The detected synchronization signal includes
The gate circuit 1f gates according to the gate signal generated by the gate signal generation circuit 1e. The gate signal generation circuit 1e is first opened at the leading edge of the RF switching pulse of the head, and the gate circuit 1f is initially in a non-gate state. When the synchronization signal is detected in this state, the gate signal creation circuit 1e creates a gate signal by a counter (not shown) using the fact that the interval between the synchronization signals is constant. The detected synchronization signal will be gated. When the synchronization signal is gated and there is no synchronization signal within the gate period, the protection synchronization signal generation circuit 1h
Synchronization protection circuit 1g by the protection synchronization signal created in
Is protected.

Further, when the state where there is no synchronizing signal continues during the gate period and the synchronizing loss count value (value indicating how many synchronizing signals are lost) in the synchronizing loss counting circuit 1i becomes a predetermined value, the gate is lost. Is opened once and the gate is closed again once the synchronization signal is detected. The synchronization loss count circuit 1i is a circuit for preventing an error of a synchronization signal from propagating. The synchronization signal protected in this way is used as a reference, and the subsequent signal processing is performed on the output of the pulse generator 1j that generates the synchronization signal based on the reference.

On the other hand, the signal output from the demodulation circuit 1c is delayed based on the reference signal output from the pulse generator 1j after the delay required for the above-described synchronization signal processing circuit is delayed by the delay circuit 1k. The ID signal is detected by the ID detection circuit 11. The detected ID signal is checked by a parity check circuit 1m for an error. On the other hand, in the detected ID signal, a sync block number is detected by a block number detection circuit 1n, and is input to one terminal of a switch 1o, and a +1 adder adds "1" to the latch circuit 1p and the sync block number. The signal is input to the other terminal of the switch 1o through 1q. The switch 1o is controlled by a switch control signal output from the gate circuit 1r. The switch 1o falls upward when the parity check of the ID is OK (pass) during normal reproduction, and falls downward when the parity check is NG (fail).

That is, the parity check of the ID is OK.
In the case of (1), the detected sync block number is input as a row address of an error correction memory (not shown) of the error correction circuit 1s. When the parity check of the ID is NG, the sync number one sync block before is set to "1". "
Is input as the row address of the error correction memory. The column address of the error correction memory is input from the column address counter 1t. Further, the write enable signal input from the input terminal 1u is used as a write control signal for the error correction memory after passing through the gate circuit 1r.

The signal delayed by the delay circuit 1k is converted into a serial / parallel signal by a serial / parallel conversion circuit 1v based on a signal output from the pulse generator 1j.
This data is written to the address of the error correction memory that has been subjected to the parallel conversion and detected earlier. In this manner, the data written in the error correction memory in block units is input to the frame memory 1w after the error correction is performed by the error correction circuit 1s and the error is corrected. In the frame memory 1w, a flag indicating whether or not data input from the error correction circuit 1s is correct is referred to.
Data is written only when the data is correct. That is, if the data is incorrect, the data of the previous frame remains on the frame memory 1w. Therefore, if the data is incorrect, the signal can be interpolated with the data of the previous frame. it can. Since the data interpolated in this manner is compressed at the time of recording, it is returned to the original data by the data decompression circuit 1x, converted to an analog signal by the D / A conversion circuit 1y, and output from the output terminal 1z.

[0011]

The tracks shown in FIG. 19 are recorded by magnetic heads having different azimuth angles for the odd track and the even track.
That is, odd tracks are recorded by a magnetic head of A azimuth, and even tracks are recorded by a magnetic head of B azimuth.

Therefore, during the trick play, the magnetic head traces over each track, so that the output level is small while the magnetic head traces the track for reverse azimuth recording, and the synchronization signal is output at regular intervals. Often not. For this reason, conventionally, a method is used in which the gate is opened in advance during the special reproduction and no protection is applied. However, in this method, since the gate is open even when the magnetic head is tracing a track having the same azimuth, there is a high possibility that an erroneous synchronization signal is regarded as a correct synchronization signal.

In the above-mentioned prior art, masking is performed by a gate signal in order to prevent detection of an error synchronization signal. However, when a recording medium is damaged or a traveling system is unstable, a clock is applied. In some cases, the generation PLL circuit 1b 'malfunctions, and the synchronization signal is output at a position shifted from the position where it is originally output. The synchronization signal at this time is not an error synchronization signal. However, if the width of the gate signal is too small, it may not be detected, and if it is too large, the probability of detecting the error synchronization signal increases. Therefore, the performance of detecting the synchronization signal depends on the width of the gate.

Although the gate width depends on the performance of the running system, it has been experimentally confirmed that most of the synchronizing signals fall within ± 2 bits with respect to the position of the normal synchronizing signal in a substantially stable running system. I have. Therefore, the gate width is generally set to a width of 5 bits. However, although rare, due to scratches on the recording medium, etc., it may not be within ± 2 bits. For example, if the synchronization signal is shifted by 3 bits or more with respect to the normal position, conventionally, this synchronization signal is ignored and replaced with a protection synchronization signal. Subsequent processing is performed based on the erroneous protection synchronization signal, so that the data of this block becomes erroneous data. In addition, since the gate position for the next synchronization signal is created based on the erroneous protection synchronization signal, this error is propagated until the next gate is opened for the set number of times of loss of synchronization. There was a point.

Further, during special reproduction, the error correction circuit 1
Regarding writing to the error correction memory in s, the switch 1o is always tilted upward by controlling the gate circuit 1r with a special reproduction signal, and the write enable signal is masked when the result of the ID parity check is NG. Then, the writing to the memory is stopped, and the data of the previous track is used.

That is, at the time of trick play, the likelihood of a signal is determined based on the result of the parity check of the ID. If the result of the parity check of the ID is NG, it is determined that there is an error in the detected sync block number and data. Then, the writing to the error correction memory in the error correction circuit 1s is stopped, and only when the result of the parity check is OK, it is determined that the data is correct and the writing to the error correction memory is performed.

Certainly, it has been experimentally confirmed that the data is correct with a considerable probability when the ID parity check is OK. However, the result of the parity check is NG
However, this does not necessarily mean that there is an error in the sync block number and the data, and the sync block number and the data may be correct even if the result of the parity check is NG. For example, this corresponds to a case where a portion of the ID signal other than the sync block number is erroneous due to a scratch on the recording medium or the like. Further, even if a portion corresponding to the sync block number in the ID signal is erroneous, the error correction circuit 1s outputs 1
Bit or two-bit errors can be corrected. In this case, just because the result of the ID parity check is NG does not mean that the sync block number and data are incorrect. Nevertheless, conventionally, since such data is not stored in the error correction memory, there has been a problem that the amount of correct data stored in the error correction memory does not increase.

[0018] Therefore, a main object of the present invention is to provide a magnetic recording / reproducing apparatus capable of storing more correct data.

[0019]

[0020]

SUMMARY OF THE INVENTION The present invention, synchronization signal composed of a digital signal, respectively, the block including parity signal of the ID signal and the ID for chromatic <br/> the block numbers are arrayed on the magnetic tape becomes Te track reproduce a magnetic tape having a plurality formed a magnetic recording and reproducing apparatus, ID detection circuit for detecting an ID signal, the detected I D
A parity check circuit that determines whether the signal is correct,
Block number detecting circuit for detecting the block number from the detected I D signal, blocks that have been detected from the correct ID signal
Latch circuit that latches the block number, the current block number and
A comparator for comparing with the latched block number , and
The current block number is higher than the latched block number.
When the value is larger,
This is a magnetic recording / reproducing apparatus including an error correction storage unit for writing data .

[0021]

[0022]

[0023]

[Action] ID signal detected by the I D detection circuit whether the correct parity check circuit is determined. Correct I
Only the D signal is input to the comparator. In the comparator, the current of the probe
Lock number and the previously detected and ID signal is correct Bro
Is compared with the lock number . Only when the current block number is higher is the data written to the error correction storage means, otherwise it is not written.

[0024]

[0025]

[0026]

Effects of the Invention According to the present invention, although the results of the ID parity check is NG, it is possible to properly store information there is no error in the block number and data,
Since more correct data can be obtained, a good special reproduction image can be obtained.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below. However, since the recording format of the tape is the same as that shown in FIGS. Referring to FIG. 1, a magnetic recording / reproducing apparatus 10 according to this embodiment includes a preamplifier 1
2 inclusive. The preamplifier 12 receives a reproduction signal from an input terminal 14, amplifies the signal at the preamplifier 12, demodulates the signal at the demodulation circuit 16, and detects a predetermined synchronization signal pattern by the synchronization signal detection circuit 18. The output from the preamplifier 12 is given to the PLL circuit 15,
A clock is generated. The synchronization signal detection circuit 18 prevents detection of an error synchronization signal. The specific operation is as follows. A serial signal sequence of 0 and 1 obtained from the preamplifier 12 is supplied to a shift register (not shown) in the synchronization signal detecting circuit 18, and the contents of the shift register and the synchronization signal prepared in advance are provided. The detection pattern is compared. If they match,
A synchronizing signal (detected synchronizing signal) is generated as a synchronizing signal. The detected synchronization signal is gated by the gate circuit 22 by the gate signal generated by the gate signal generation circuit 20.

The gate signal generation circuit 20 is provided, for example, in FIG.
It is configured as shown in FIG. Here, a description will be given assuming that one sync block shown in FIG. 20 is 750 bits. The gate signal creation circuit 20 shown in FIG. 2 includes a counter 23 for setting a position for opening a gate. When the counter 23 receives the protection synchronization signal shown in FIG. 3B from the protection synchronization signal generation circuit 38 (described later), the counter 23 starts counting clocks shown in FIG. 3A (FIG. 3D). , Counter 2
3 is connected to a gate width setting circuit 24 including, for example, a selector.
The initial value in is set. The gate width setting circuit 24 can set the gate width according to the envelope detection output. In this embodiment, the gate width when the high-level envelope detection output is given is set to 5 bits.
That is, “2” is set to make the gate width ± 2 bits, and is given to the counter 23. When the count value of the counter 23 becomes “748”, a low-level signal is output from the decoder 26 as shown in FIG. This signal is supplied to the counter 28 and to the JK-FF 32 via the inverter 30. J
After one clock based on this signal, the K-FF 32 outputs a low-level gate signal as shown in FIG. 3G to open the gate.

On the other hand, when the signal from the decoder 26 is input, the counter 28 starts counting the clock (FIG. 3 (E)), and gives the count value to the comparator 34 as P. “2” is given to the comparator 34 from the gate width setting circuit 24, and “4” obtained by doubling the value is stored as the reference count value Q. When P = Q in the comparator 34, a low-level pulse as shown in FIG.
F32. The JK-FF 32 outputs the signal 1
After the clock, that is, based on the rise of the signal, a high-level gate signal is output, and the gate is closed.

The PRE terminal of the JK-FF 32 is supplied with a low-level gate open pulse for keeping the gate open at all times. While the gate open pulse is being supplied, a low-level gate signal is output from the JK-FF 32, and the gate is always opened. As this gate open pulse, in addition to the low level envelope detection output, an RF switching pulse and a gate open signal from a synchronization loss count circuit 40 (described later) are used.

The gate signal generating circuit 20 receives the RF switching pulse of the magnetic head shown in FIG. 4A given from the input terminal 35 to the gate circuit 22 which is initially not gated. At the leading edge, a gate signal for opening the gate is supplied first, and the first detected synchronization signal (FIG. 4B) is passed. When the detection synchronization signal is obtained in this state, the gate signal generation circuit 24
The gate signal is generated by counting the count value of the counter 23 using the fact that the interval between the synchronization signals is constant (FIG. 4C), and the synchronization signal detected from the next is used. Is gated like the gate signal A shown in FIG. When the gate signal A is given to the gate circuit 22, the gate circuit 2
2 outputs a synchronization signal A as shown in FIG.

When a low-level envelope detection signal is supplied to the gate signal generation circuit 20, a gate signal B as shown in FIG. 4 (F) is supplied to the gate circuit 22. A synchronization signal B as shown in FIG. 4 (G) is output. Referring back to FIG. 1, the synchronization signal detected by the synchronization signal
Given to. When the gate circuit 22 is opened by the gate signal generated by the gate signal generation circuit 20, the synchronization signal detected during the gate period passes through the gate circuit 22. On the other hand, the error synchronizing signal generated by the fact that the same bit string as the synchronizing signal pattern happens to be outside the gate period is masked. Synchronous signal protection circuit 36 by signal
Is protected. In other words, if the synchronization signal passes through the gate circuit 22, the synchronization signal protection circuit 36 selects and outputs the passed synchronization signal, and if the synchronization signal does not pass through the gate circuit 22, the synchronization signal protection circuit 36 Selects and outputs the protection synchronization signal obtained from the protection synchronization signal generation circuit 38. The protection synchronization signal is supplied to the synchronization signal protection circuit 3
6 is generated by a counter (not shown) in the protection synchronization signal generation circuit 38 which uses the output signal of FIG. 6 as a reset signal.

Further, when there is no synchronization signal in the gate and the synchronization loss count value (a value indicating how many times the synchronization signal has been lost) in the synchronization loss counting circuit 40 becomes a predetermined value, the gate open signal is output. Is supplied to the gate creation circuit 20. Then, the gates are once all opened by the gate signal generation circuit 20, and once the synchronization signal is detected, the gates are closed again. This is to prevent the propagation of the error of the synchronization signal.

The signal amplified by the preamplifier 12 is compared with an arbitrarily set reference level and an output level of the envelope by an envelope detection circuit 42, and the gate signal creation circuit 20 is controlled based on the comparison result. When the result of the envelope detection is equal to or lower than an arbitrarily set reference level, that is, when the magnetic head is tracing a reverse azimuth track during special reproduction such as double speed or triple speed, the output level becomes small. The gate circuit 22 is controlled so as to open the gate by the gate signal B shown in FIG. Thereby, the synchronization signal detection circuit 1
The synchronizing signal detected at step 8 acts so as to be regarded as a normal synchronizing signal. By opening the gate in this manner, a situation in which the synchronization signal is not detected due to a positional shift of the synchronization signal during double-speed reproduction is avoided. In other words, an error synchronization signal is also taken in,
The required correct synchronization signal can always be detected.

Conversely, when the head traces the positive azimuth during special reproduction or during normal reproduction, the envelope detection result becomes larger than the reference level, and the gate signal A (FIG. 4D) is gated. The signal is supplied to the circuit 22. At this time, if the synchronization signal is not included in the gate period, the protection synchronization signal created by the protection synchronization signal creation circuit 38 is regarded as a normal synchronization signal, and is used as a reference signal for the subsequent signal processing. The operation is performed.

The synchronization signal protected in this way serves as a reference, and the subsequent signal processing is performed at the output of the pulse generator 44 which generates a reference signal based on the reference. The pulse generator 44 outputs a pulse for detecting an ID signal, a pulse required for serial / parallel conversion of the signal, and a pulse for creating a column address.

On the other hand, the signal output from the demodulation circuit 16 is delayed by the delay circuit 46 for the time required for the above-mentioned synchronous signal processing circuits (18 to 40),
The detection circuit 48 detects the ID signal based on the reference signal output from the pulse generator 44. The block number included in the ID signal detected by the ID detection circuit 48 is used as a row address of an error correction memory (not shown) in the error correction circuit 64 described later.

That is, the parity check circuit 50 checks whether the ID signal detected by the ID detection circuit 48 has an error. On the other hand, in the detected ID signal, the sync block number is detected by the block number detection circuit 52, and is input to one terminal of the switch 54, and at the same time, the latch circuit 56 and +1 for adding "1" to the sync block number are added. Switch 5 through the container 58
4 is input to the other terminal. The switch 54 is controlled by a switch control signal output from the gate circuit 60.

Here, the gate circuit 60 is, for example, shown in FIG.
It is configured as shown in FIG. Gate circuit 60 shown in FIG.
Includes OR circuits 60a and 60b, a NOR circuit 60c, and an inverter 60d. The OR circuit 60a has a special reproduction signal from the input terminal 61 ("high level" during special reproduction).
And an ID parity check output ("OK""highlevel") from the parity check circuit 50, and a switching control signal is output. Also, the NOR circuit 60
To c, a special reproduction signal is supplied via an inverter 60d and an ID parity check output is supplied. The OR circuit 60b receives a write enable signal from the input terminal 62 together with the output of the NOR circuit 60c, and outputs a write enable signal from the OR circuit 60b.

Therefore, during normal reproduction, the switch 54 falls upward when the parity check of the ID is OK, and falls downward when the parity check is NG. When the ID parity check is OK, the detected sync block number is input as the row address of the error correction memory in the error correction circuit 64. When the ID parity check is NG, the sync block number one sync block before is added. The value obtained by adding “1” is input as the row address of the error correction memory.

The count value of the column address counter 65 becomes the column address of the error correction memory in the error correction circuit 64. Here, an image diagram of the error correction memory is shown in FIG. Video data area 64 shown in FIG.
Data is stored in a. Also, as can be seen from FIG. 5, the write enable signal input from the input terminal 62 is used as a write control signal for an error correction memory in the error correction circuit 64 after passing through the gate circuit 60.

The signal delayed by the delay circuit 46 is subjected to serial / parallel conversion by a serial / parallel conversion circuit 66 in accordance with a signal output from the pulse generator 44, and the signal of the error correction memory in the error correction circuit 64 is output. It is written as data on the address. In this manner, the data written in the error correction memory in block units is input to the frame memory 68 after the error correction circuit 64 corrects the error and corrects the error. In the frame memory 68, a flag indicating whether the data input from the error correction circuit 64 is correct is referred to, and the data is written only when the data is correct. That is, if the data is incorrect, the frame memory 68
The data one frame before remains on the top,
Therefore, when the data is wrong, the signal can be interpolated by the data of one frame before. Since the data interpolated in this manner is compressed at the time of recording, it is returned to the original data by the data decompression circuit 70, converted into an analog signal by the D / A conversion circuit 72, and output from the output terminal 74.

The operation of the magnetic recording / reproducing apparatus 10 will be described with reference to FIG. First, when an RF switching pulse is input in step S1, the gate is opened in step S3. On the other hand, when step S1 is "NO", that is, after the RF switching pulse is output, the process proceeds to step S5. In step S5, a gate signal having a predetermined width is created by the gate signal creation circuit 20, and the process proceeds to step S7. In step S7, the envelope detection circuit 42 determines whether or not envelope detection output> reference level. Step S7 returns "N
If "O", the gate width is changed in step S9. In this embodiment, a gate signal that always opens the gate is generated and the gate width is changed. When "YES" in step S7, step S3 is performed. After the processes in S9 and S9, the process proceeds to step S11.

In step S11, a synchronization signal is detected by the synchronization signal detection circuit 18. Thereafter, in step S13, when a synchronization signal is detected, step S13 is executed.
Go to 15. If the synchronization signal has not been detected in step S13, the process proceeds to step S17. Step S1
If the gate open signal is output from the synchronization loss counting circuit 40 in step 7, the gate is opened in step S19 and the process returns to step S11.

On the other hand, if the gate open signal is not output in step S17, the protection synchronization signal is created by the protection synchronization signal creation circuit 38 in step S21, and the flow advances to step S15. In step S15, I
The ID signal is detected by the D signal detection circuit 48, and step S
Proceed to 23. In step S23, if the parity check of the ID signal is correct in the parity check circuit 50, the sync block number is loaded into the error correction memory in the error correction circuit 64 in step S25. On the other hand, if the parity check is incorrect in step S23, "1" is added to the sync block number one sync block before in step S27, and the value is loaded into the error correction memory in step S29.

Instead of the envelope detection circuit 42, a control circuit 76 for controlling the gate width depending on the locked state of the PLL as shown in FIG. 8 may be used. FIG.
Includes an edge detection circuit 78 for detecting an edge of data output from the preamplifier 12. The output from the edge detection circuit 78 is provided to an AND circuit 82 via a monostable multivibrator 80. A
A clock is applied to the ND circuit 82 via an inverter 84, and the output of the AND gate 82 is
6 to a comparator 88. The comparator 88 compares the signal with a predetermined reference signal, and an output corresponding to the comparison result is supplied to the gate signal generation circuit 20.

In the control circuit 76 thus configured, when the PLL is locked, the output from each circuit is as shown in FIG. 9A, and the output of the comparator 88 is low. On the other hand, when the PLL is not locked, the output from each circuit is as shown in FIG. 9B, and the output of the comparator 88 is at a high level. Next, a magnetic recording and reproducing apparatus 100 according to another embodiment will be described with reference to FIG. In the magnetic recording / reproducing apparatus 100, the same components as those of the magnetic recording / reproducing apparatus 10 shown in FIG. 1 are denoted by the same or similar reference numerals, and the duplicate description will be omitted.

In this magnetic recording / reproducing apparatus 100, an ID signal is detected by an ID signal detection circuit 48a from a signal obtained through a delay circuit 46 based on a protected synchronization signal, and a block number detection circuit 52a detects a block number. Is detected. Here, the delay circuits 46 and 102a are provided for adjusting the timing of the signal input to the ID signal detection circuit 48a.

At this time, the parity check is performed by the parity check circuit 50a. If the result is OK, the detected block number is regarded as correct, and the value of the detected block number is stored in the error correction memory 64 in the error correction circuit 64 as it is. If the address is NG, the latch circuit 5
The switch 54a responds to the signal from the parity check circuit 50a so that the value obtained by adding "1" to the block number one sync block before latched in 6a by the +1 adder 58a becomes the row address of the error correction memory. To switch.

On the other hand, the synchronization signal (FIG. 11A) detected by the synchronization signal detection circuit 18 is also supplied to the gate circuit 22b. Width b created by gate signal creation circuit 20b
When the gate circuit 22b is opened by the gate signal (a <b), the synchronization signal detected during the gate period passes. On the other hand, an error synchronizing signal generated due to the fact that the same bit sequence as the synchronizing signal pattern happens to be outside the gate period is masked.

Based on the synchronization signal passed through the gate circuit 22b, the signal obtained through the delay circuit 46
The ID signal is detected by the D signal detection circuit 48b, and the block number is detected by the block number detection circuit 52b. Then, a parity check is performed by the parity check circuit 50b to check whether or not there is an error in the ID signal.

The block number detected from the ID signal by the block number detection circuit 52b
04. The block number one sync block before, which is output via the switch 54b, is latched by the latch circuit 56b, and a value obtained by further adding "1" by the +1 adder 58b is given to the comparator 104. The comparator 104 compares these two inputs to determine whether the block number is correct.

As described above, in the processing relating to the synchronization signal passed through the gate circuit 22b, the parity check of the ID signal and the block number are also performed. When both of them are OK, the switches 54b and 106 Are both lower terminals, that is, the switch 54b selects the output from the block number detection circuit 52b, and the switch 106 selects the synchronization signal output from the gate circuit 22b. In other cases, that is, the result of the ID parity check in the parity check circuit 50b and the block number detection circuit 52b
When at least one of the detection results is NG, the switches 54b and 106 each have an upper terminal, that is, the switch 54b selects the output of the switch 54a, and the switch 106 selects the output of the delay circuit 108a. .

The delay circuits 102b, 108a and 108b are for adjusting a time delay caused by passing a signal through a circuit system. The output of the switch 54b, that is, the block number is output to the error correction circuit 64.
Used as the row address of the error correction memory
The output of switch 106 is input to pulse generator 110, and the output from pulse generator 110 is used as a reference signal for serial / parallel converter 66 and column address counter 65.

As described above, the signal output from the delay circuit 46 is subjected to serial / parallel conversion by the serial / parallel conversion circuit 66 and then stored in the error correction memory in the error correction circuit 64. , The output of the column address counter 65 determines the column address of the error correction memory in the error correction circuit 64, and the block number output from the switch 54b determines the row address of the error correction memory in the error correction circuit 64. .

The operation of detecting the synchronization signal of the magnetic recording / reproducing apparatus 100 will be more apparent with reference to FIG. That is, FIG. 11A shows an output waveform of the synchronization signal detection circuit 18, in which 示 し indicates a correct synchronization signal, and × indicates an error synchronization signal. That is, in this figure, 6
It is assumed that the second synchronization signal (Sync6) is an error synchronization signal.

FIG. 11B shows a gate signal having a width a, that is, the output of the gate signal generation circuit 20a. This gate signal is output from the synchronization signal protection circuit 3 shown in FIG.
The gate signal generation circuit 20a generates the signal based on the output signal of No. 6, ie, the protected synchronization signal, using a counter or the like. The absence of the gate signal having the width a near the synchronization signal (Sync5) is caused by the gate opening signal (FIG. 11D) output from the synchronization loss count circuit 40 immediately before the gate signal is generated. Then, the gate signal generation circuit 2 is operated according to the synchronization signal detected thereby.
This is because the counter in 0a is reset. In addition,
This embodiment shows a case where the gate circuit 22a is forcibly opened when the state where there is no synchronizing signal in the gate signal of width a continues twice, and the gate is closed again when the next synchronizing signal is detected in that state. ing.

Here, for example, in the case of only the gate circuit 22a, although the synchronization signal (Sync2) and the synchronization signal (Sync3) shown in FIG. 11 are correct synchronization signals,
The mask signal is masked by the gate signal and detected as an error synchronization signal. Instead, a synchronization signal (obtained from the protection synchronization signal) marked with x as shown in FIG. 11E is erroneously detected.

FIG. 11C shows a gate signal having a gate width b.
That is, it shows the output signal of the gate circuit 22b, and the synchronization signal gated by this gate signal is as shown in FIG. In FIG. 11 (F), the synchronization signal with a circle is a correct synchronization signal, the result of the parity check circuit 50b is OK, and the comparison result of the comparison circuit 104 indicates that the comparison result matches.
The switch 106 shown in FIG.
1 (F), that is, the synchronization signal of FIG. 11 (J) is selected.

On the other hand, since the synchronization signal marked with x in FIG. 11F is an error synchronization signal, the result of the parity check circuit 50b becomes NG (low level) as shown in FIG. As shown in FIG. 11H, the comparison result of the comparison circuit 104 becomes non-coincidence (low level). At this time, the switch 106 is switched upward, and FIG.
(E), that is, the synchronization signal of FIG. 9 (I) is output. Thus, the synchronization signal output from the switch 106 is as shown in FIG. 11 (K), and a correct synchronization signal without error is detected.

The operation of such a magnetic recording / reproducing apparatus is shown in FIG.
2 and FIG. As shown in FIG. 12, the step numbers with "a" are the gate signals a.
As shown in FIG. 13, step numbers with "b" attached thereto indicate processes related to the gate signal b. These processes are performed in parallel, but for convenience of explanation, the process related to the gate signal a will be described first.

First, in step S41a, when an RS switching pulse is input, in step S43a, the gate of the gate circuit 22a is opened by the gate signal generation circuit 20a. On the other hand, at step S41a is "NO", that is, at the time after the input of the RF switching pulse, the gate a is created by the gate signal creation circuit 20a in step S45a. After the processing of steps S43a and S45a, step S47a
Proceed to.

In step S47a, a synchronization signal is detected by the synchronization signal detecting circuit 18, and the process proceeds to step S47.
Proceed to 49a. If no synchronization signal is detected in step S49a, the process proceeds to step S51a. If it is determined in step S51a that the gate open signal has been output from the synchronization loss count circuit 40, the process proceeds to step S53a.
In, the gate of the gate circuit 22a is opened, and the process returns to step S47a. If it is determined in step S51a that the gate open signal has not been output, step S55a
In, the protection synchronization signal is generated by the protection synchronization signal generation circuit 26a. When the synchronization signal is detected in step S49a and after the processing in step S55a, the process proceeds to step S57a, where the ID signal is detected by the ID signal detection circuit 48a, and the process proceeds to step S59a. In step S59a, if the ID parity check by the gate signal b is OK, the process proceeds to step S61a. In step S61a, if the value obtained by adding "1" to the sync block number one sync block before by the gate signal b matches the block number from the block number detection circuit 52b,
Switches 54b and 106 are connected to the lower terminal,
The process proceeds to step S55b described below.

When step S59a is "NO" or when step S61a is "NO", the flow proceeds to step S63a. In step S63a, if the parity check of the ID signal is OK in the parity check circuit 50a,
In step S65a, the sync block number is loaded into the error correction memory in the error correction circuit 64. On the other hand, if "NO" in the step S63a, "1" is added to the block number one synchronization signal before in a step S67a, and the value is stored in the error correction memory in a step S69a.

On the other hand, when an RF switching pulse is applied in step S41b shown in FIG. 13, the gate of the gate circuit 22b is opened in step S43b. If step S41b is "NO", step S41b
At 45b, the gate signal b is created by the gate signal creation circuit 20b and supplied to the gate circuit 22b. After the processing of steps S43b and S45b, step S47b
Proceed to.

In step S47b, the gate signal a
When the gate open signal is output by step S
Proceed to 49b. In step S49b, the gate of the gate circuit 22b is opened, and the process proceeds to step S51b. The process also proceeds to step S51b when step S47b is “NO”. In step S51b, the synchronization signal detection circuit 1
In step S53b, the ID signal is detected by the ID detection circuit 48b, and the process proceeds to step S55b.

If the ID parity check by the parity check circuit 50b is OK in step S55b, the sync block number is detected by the block number detection circuit 52b in step S57b, and the flow advances to step S59b. In step S59b, if the value obtained by adding "1" to the block number one sync block before and the block number from the block number detection circuit 52b match, the sync block number in the error correction circuit 64 is changed in step S61b. It is stored in the error correction memory.

When step S55b is "NO" or when step S59b is "NO", the flow proceeds to step S59a. When step S61a is “YES” and the process proceeds to step S55b, steps S55b and S59b naturally become “YES”. Step S55b
When the process proceeds to step S59a because S59b is “NO”, step S59a is naturally “NO”.

Further, a magnetic recording / reproducing apparatus 120 according to another embodiment will be described with reference to FIG. The magnetic recording / reproducing device 120 does not change the gate width of the gate signal generated by the gate signal generating circuit 20 according to the detection result of the envelope detecting circuit 42 as in the magnetic recording / reproducing device 10 shown in FIG. Although the configuration is basically the same, the switch operation is controlled by the output of the parity check circuit 50 and the mask operation of the mask 122 is released during the normal reproduction, so that the circuit operation is also shown in FIG. This is the same as the magnetic recording / reproducing device 10. Therefore, duplicate description is omitted by assigning the same number.

Therefore, in the following, among the operations relating to the special reproduction, the main points to be noted are described.
The sync block number output from the switch 54 is input to the comparator 124 and the latch circuit 126. The output of the latch circuit 126 is reset at the leading edge of the RF switching pulse, and initially has a value of “0”. Then, the output of the parity check circuit 50 of the ID signal is checked, and the sync block number output from the switch 54 is latched by the latch circuit 126 only when the parity check is OK.

That is, the output of the latch circuit 126 is I
D is updated only when the parity check is OK, and among the sync block numbers smaller than the current sync block number, those whose ID parity check is OK are always output. The comparator 124 compares this value with the current sync block number. If the current sync block number is smaller than the sync block number from the latch circuit 126, the comparator 124 outputs a low level write enable mask signal. , Mask circuit 12
At 2, the write enable signal is masked, and writing to the error correction memory in the error correction circuit 64 is stopped.
On the other hand, when the current sync block number is larger, a high-level write enable mask signal is output from the comparator 124, and data is written on the sync block number and the address created by the Karamo address counter 65.

Here, mask circuit 122 is configured, for example, as shown in FIG. Mask circuit 1 shown in FIG.
22 includes an OR circuit 128, a NOR gate 130, and an inverter 132. The NOR circuit 130 receives a signal from the input terminal 61 via an inverter 132 and a write enable mask signal from a comparison circuit 124. The output of the NOR circuit 130 and the write enable signal from the input terminal 62 are
8 and the output of the OR circuit 128 is
2 is given to the error correction circuit 64 as an output.

In the mask circuit 122, if the special reproduction signal and the low level write enable mask signal are output, the write enable signal is output to the error correction circuit 6
4 is not output. On the other hand, when the high-level write enable mask signal is being output, the write enable signal is given to the error correction circuit 64. Referring to FIG. 16, the synchronization signal protection circuit 36 outputs
A protection synchronization signal as shown in FIG. 16A is output, and the pulse generator 44 outputs an ID detection pulse as shown in FIG. The parity check circuit 50 outputs a signal as shown in FIG. The protection synchronization signal (Sync) shown in FIG.
Since 2) is incorrect, the output from the parity check circuit 50 goes low accordingly.

At this time, assuming that the sync block number output via the switch 54 is “30 → 25 → 32 → 33 → 34” as shown in FIG. Wrong sync block number. Accordingly, the sync block number from the latch circuit 126 is “29 → 30 → 30 → 32 → 33”. As can be seen by comparing FIG. 16D and FIG. 16E, the latch circuit 126 does not hold the wrong sync block number “25”, but holds “30” captured before it. The comparator 124 compares the two input signals. If the current sync block number shown in FIG. 16D is smaller than the sync block number from the latch circuit 126 shown in FIG. ,
As shown in FIG. 16F, the comparator 124 outputs a low-level write enable mask signal to the mask circuit 122. Then, the write enable signal is not output from the OR circuit 128 of the mask circuit 122, and the error correction circuit 6
The writing of data to the error correction memory 4 is stopped.

The main operation of the magnetic recording / reproducing apparatus 120 will be described with reference to FIG. First, in step S71 shown in FIG. 17, when an RF switching pulse is given, the process proceeds to step S73. Step S73
In, the gate of the gate circuit 22 is opened. on the other hand,
If “NO” in the step S71, a gate signal of a predetermined width is created in a step S75, and a gate is set. After the processing in steps S73 and S75, the process proceeds to step S77. In step S77, the synchronization signal is detected by the synchronization signal detection circuit 18, and if no synchronization signal is detected in step S79, the process proceeds to step S81. If a gate open signal has been output from the synchronization loss count circuit 40 in step S81, the gate of the gate circuit 22 is opened in step S83, and the process returns to step S77. On the other hand, if the gate open signal is not output in step S81,
In step S85, the protection synchronization signal is created by the protection synchronization signal creation circuit 38, and the process proceeds to step S87. When step S79 is "NO", the process proceeds to step S87.

In step S87, the ID detection circuit 4
8, the ID signal is detected, and in step S89a, the ID parity check is OK in the parity check circuit 50.
If so, in step S91a, the latch circuit 126
The sync block number is latched in step S9.
Proceed to 3. If the parity check of the ID signal is NG in step S89a, the process directly proceeds to step S93 without updating the sync block number. In step S89b after the process of step S87, the current sync block number is detected by the block number detection circuit 52, and the process proceeds to step S93.

In step S93, the comparator 124 compares the current sync block number with the sync block number from the latch circuit 126. If the current sync block number is larger, the current sync block number is changed to the error correction circuit 6 in step S95.
4 is written to the error correction memory. Step S9
In 3, if the current sync block number is equal to or smaller than the sync block number from the latch circuit 126,
In step S97, the writing of data to the error correction memory in the error correction circuit 64 is stopped.

In the above embodiment, the magnetic recording / reproducing apparatus for recording digital data on a magnetic tape has been described. However, it goes without saying that the present invention can also be applied to an optical recording type recording / reproducing apparatus.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a reproducing system of a magnetic recording / reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a gate signal generation circuit.

FIG. 3 is a timing chart for explaining the operation of the gate signal generation circuit.

FIG. 4 is a timing chart for explaining main operations of the embodiment in FIG. 1;

FIG. 5 is a circuit diagram illustrating an example of a gate circuit.

FIG. 6 is an illustrative view showing a memory image of an error correction memory;

FIG. 7 is a flowchart showing a main operation of the embodiment in FIG. 1;

FIG. 8 is a block diagram illustrating an example of a control circuit that controls a gate width based on a locked state of a PLL.

9A is a timing chart showing the operation of the control circuit when the PLL is locked, and FIG. 9B is a timing chart showing the operation of the control circuit when the PLL is not locked.

FIG. 10 is a block diagram showing a main part of a reproducing system of a magnetic recording / reproducing apparatus according to another embodiment of the present invention.

FIG. 11 is a timing chart for explaining main operations of the embodiment in FIG. 10;

FIG. 12 is a flowchart showing main operations of the embodiment in FIG. 10;

FIG. 13 is a flowchart showing a continuation of the operation in FIG. 12;

FIG. 14 is a block diagram showing a main part of a reproducing system of a magnetic recording / reproducing apparatus according to another embodiment of the present invention.

FIG. 15 is a circuit diagram illustrating an example of a mask circuit.

FIG. 16 is a timing chart for explaining main operations of the embodiment in FIG. 14;

FIG. 17 is a flowchart showing a main operation of the embodiment in FIG. 14;

FIG. 18 is an illustrative view showing a recording format of a digital VTR;

FIG. 19 is an illustrative view showing a recording state of a signal of the digital VTR;

FIG. 20 is a block diagram showing a detailed configuration of one sync block of a signal in the digital VTR.

FIG. 21 is an illustrative view showing a synchronizing signal protection operation;

FIG. 22 is a block diagram showing a conventional technique.

[Explanation of symbols]

 10, 100, 120 ... magnetic recording / reproducing device 15 ... PLL circuit 18 ... synchronization signal detection circuit 20, 20a, 20b ... gate signal creation circuit 22, 22a, 22b, 60 ... gate circuit 36 ... synchronization signal protection circuit 38 ... protection synchronization Signal generation circuit 40 Synchronization loss count circuit 42 Envelope detection circuit 48, 48a, 48b ID detection circuit 50, 50a, 50b Parity check circuit 52, 52a, 52b Block number detection circuit 54, 54a, 54b, 106 ... Switches 56, 56a, 56b, 126 Latch circuits 58, 58a, 58b +1 adder 64 Error correction circuit 76 Control circuits 104, 124 Comparator 122 Mask circuit

Claims (1)

(57) [Claims] 1. A synchronizing signal consists of each digital signal, the block including a parity signal of the ID signal and the ID having the block numbers to play tape track comprising a plurality of sequences are plurally formed on the magnetic tape a magnetic recording and reproducing apparatus, ID detection circuit for detecting an ID signal, the parity check circuit the detected I D signal to determine whether correct or not, the block number for detecting the block number from the detected I D signal Detector circuit, block detected from correct ID signal
Latch circuits for latching the lock number, comparator for comparing the current block number and the latched block number, and the current block number the La
When the block number is larger than the
Write data regardless of the judgment result of the check circuit
A magnetic recording / reproducing apparatus, comprising: an error correction storage unit for performing the following .