JPH06259888A - Digital signal reproducing device and method therefor - Google Patents

Abstract

PURPOSE:To improve a detecting rate of a sub-code by reproducing sub-codes respectively according to a track reference signal in reproducing at an ordinary speed, and according to recording finish timing of a digital signal in a search mode. CONSTITUTION:In reproducing at an ordinary speed, a selecting circuit 12 selects a PCM area finish signal 34 generated in an area generating circuit 11 by a mode switching signal from a mode switching signal input terminal 15, and outputs it to a VSC timing generation circuit 13. A circuit 13 generates a VSC start signal 33 with timing of 1.1H by the output from the circuit 12. Since a signal 33 can be always and constantly generated, a sub-code can be stably reproduced. In search mode, the circuit 12 selects an address area finish signal 40 generated in a block address counter 10 and outputs it to a circuit 13. The circuit 13 generates the signal 33 with timing of 1.1H in the same way as reproducing at an ordinary speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to reproducing a digital signal, and more particularly to a digital signal reproducing apparatus suitable for reproducing a sub-code which is an additional information signal recorded in an area different from that of the digital signal. And method.

[0002]

2. Description of the Related Art In a recording / reproducing apparatus using a magnetic tape,
Generally, it has a drawback that it is difficult to search for a cue and the like as compared with a disc. In a VTR or the like, a method of recording a cueing signal separately from a video signal has been considered.

In a VTR for recording a video signal and a PCM audio signal using different areas on a tape, a cue signal and a subcode indicating time code information are provided between the video signal area and the PCM audio signal area. As a device for recording the data, there is an information signal recording / reproducing device described in JP-A-64-86304.

[0004] This is two tapes for a rotating cylinder.
In a PCM audio 8 mm VTR wrapped around 16 °, as shown in FIG. 2A, a PCM area 20 is provided in front of a 180 ° video area 22 to record PCM audio, and the PCM area 20 and the video area 22 are further recorded. A subcode area 21 is provided between the two to record the subcode.

This sub-code area 21 is shown in FIG.
As shown in (1), area tolerance absorption, erase code area 23 for pulling in the reproduced clock, search mark area 24 for recording / reproducing a cue signal, data area 25 having an information capacity of 25 bytes for recording / reproducing a time code, And an end mark area 26 indicating the end of the sub code area.

A PC recorded in the PCM area 20
The M audio recording format has 132 blocks per track according to the block structure having the block format shown in FIG. Here, 27 is a sync signal indicating the beginning of each block, 28 is a block address indicating the recording order of the block, and 29 is a check code for error detection added to the block address 28 and other data. In the figure, Q and P are error correction parities added to the data.

[0007] This sub-code is capable of post-recording to be recorded later while reproducing a video signal or a PCM audio signal which has already been recorded, and is very suitable for finding the beginning or the like.

[0008]

When the tape recorded by the above apparatus is reproduced, the subcode area 21 for reproducing the subcode is generated based on the block address 28 of the reproduced PCM audio signal. To be done.

In the normal reproduction mode in which the PCM voice is reproduced normally, the subcode area 21 is generated relatively accurately and the subcode can be reproduced well.

However, in the variable speed reproduction and the search mode,
Since it is necessary to change the rotation frequency of the rotary head in order to keep the relative speed of the head and the tape constant, the position of the subcode area 21 changes with respect to the track reference signal, so that the PCM sound is reproduced well. When it disappears, the block address 28 is not accurately detected, and the subcode area 21 cannot be accurately determined.
However, in the search mode, a miracle of the head extends over a plurality of tracks, so that the PCM sound cannot be completely reproduced, and there is a section in which a reproduction signal cannot be obtained.
The end point of the M area 20 may be erroneously detected. . Also, the subcode is recorded so that it can be searched for even in the search mode.However, in the search mode, the subcode area cannot be accurately determined and the subcode cannot be played back. There is a problem of disappearing.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a digital signal reproducing apparatus in which the subcode area is well generated even in the search mode and the subcode detection rate is improved.

[0012]

In order to achieve the above object, a track composed of a plurality of areas is formed, and a plurality of blocks are formed in a first area in the track, and at least a digital signal, and A sync signal indicating the beginning of a block, a block address indicating the recording order in the first area of the block, and at least a check code for error detection added to the digital signal are recorded. In a reproducing device for reproducing a recording medium in which a subcode indicating additional information to the digital signal is recorded in a second area different from the area
A servo circuit that generates a track reference signal that indicates the reproduction cycle of the track, and a first digital area signal that indicates the reproduction timing of the first area based on the track reference signal that is output by the servo circuit, and An area signal generating circuit for generating a second digital area signal indicating the reproduction timing of the second area, and a digital signal reproducing circuit for reproducing the recording medium according to the first digital area signal output by the area generating circuit. When,
An area end detection circuit that detects an end point of the first area from the digital signal reproduced by the digital signal generation circuit to generate a digital area end signal,
In a first mode in which the recording medium is reproduced at a normal speed, a second digital area signal output by the area signal generating circuit is selected, and a second digital area signal is reproduced at a speed different from the normal speed. In the mode, a selection circuit for selecting the digital area end signal output by the area end detection circuit, and a subcode reproduction circuit for reproducing the recording medium according to the area signal output by the selection circuit,
A synchronizing signal detecting circuit for detecting the synchronizing signal from the digital signal reproduced by the digital signal reproducing circuit, and the digital signal reproduced by the digital signal reproducing circuit by the check code reproduced by the digital signal reproducing circuit. A check circuit for determining whether or not the signal is correct, and a sync signal from the reproduction start point of the first area until the sync signal detection circuit determines that the sync signal is detected in the first area. In the detection section and the synchronization signal detection section from when the synchronization signal detection circuit determines that the synchronization signal is detected in the first area to when the end of the first area is detected, the block By providing the area end detection circuit that changes the load condition of the block address of the address counter It is made.

[0013]

By detecting the end point of the PCM voice area by the area end detection circuit, the subcode area can be accurately determined even in the search mode in which the position of the area changes with respect to the track reference signal. In addition, by changing the block address processing algorithm in the search mode in the area end detection circuit, it is possible to prevent the block address counter from malfunctioning even in a section where the reproduction signal cannot be obtained, and detect the end point of the area by mistake. Can be prevented, and the reliability of the generated subcode area can be improved.

[0014]

EXAMPLE An example of the present invention will be described below with reference to FIG.

FIG. 1 is a block diagram of a PCM voice signal processing circuit and a subcode processing circuit of an 8 mm VTR.
Is a rotary cylinder, 2 is a reproduction amplifier, 15 is a mode switching signal input terminal for switching the normal mode / search mode, 16 is a subcode output terminal, and 17 is an audio output terminal.

First, the PCM voice reproducing operation will be described.

During reproduction, the signal reproduced by the rotary cylinder 1 is sent to the reproduction circuit 3 via the reproduction amplifier 2.
Waveform equalization and reproduction clock generation are performed.

From the reproduced signal 31 generated by the reproducing circuit 3, the synchronous detecting circuit 5 detects the synchronous signal 27 and after demodulating by the demodulating circuit 6, the block address 28 is obtained by the address checking circuit 9. The error is detected, and the error detection circuit 7 uses the check code 29 to detect an error. Further, the block address counter 10 is operated according to the PCM area signal 32 generated by the area generation circuit 11 on the basis of the head switching signal which is the track reference signal and is generated by the servo circuit which controls the operation of the rotary cylinder. The block address counter 1 compares the internal block address 70 generated by the block address counter 10 with the reproduced block address 28 reproduced.
The address check circuit 9 controls the operation of 0.

The data demodulated by the demodulation circuit 6 and the internal address 70 of the block address counter 10 are sent to the PCM processing circuit 8 to be subjected to error correction and the like, and then output as an audio signal from the audio output terminal 17.

Next, the generation of the sub code area signal 33 will be described with reference to FIGS.

The area generation circuit 11 causes the PCM area end signal 3 at a timing of 255.7H (H is a horizontal period in the video signal) from the edge of the head switching signal.
4 is generated. This corresponds to the end point of the PCM area signal as shown in FIG. In addition, the internal block address 70 is set to the PCM area 20 by the block address counter.
When the value indicating the end of is reached, the address end signal 40 is generated.

In normal speed reproduction, the selection circuit 12 generates the P generated by the area generation circuit 11 in response to the mode switching signal input from the mode switching signal input terminal 15.
The CM area end signal 34 is selected and output to the VSC timing generation circuit 13. The VSC timing generation circuit outputs V at the timing of 1.1H from the output of the selection circuit 12.
The SC start signal 33 is generated. Therefore, in the case of normal speed reproduction, the VSC start signal 33 is the head switching signal 30.
It is fixedly generated at the timing of 256.8H from the edge of. In accordance with the VSC start signal 33 generated by the VSC timing generation circuit 13, the VSC reproduction circuit 14 detects the search mark 24 and the data 25, and outputs from the subcode output terminal 16.

Since the erase code 23 is a signal for pulling in the clock, it is not necessary to reproduce and output it. Therefore, reproduction after the search mark may be performed. VSC start signal 3
3 is the timing indicating the start point of the area of the search mark 24.

In normal reproduction, since the rotation cycle of the rotary cylinder 1 is constant, the VSC area 21 is also at a constant position with respect to the edge of the head switching signal 30.
There is no problem with the above method. In addition, even if the PCM audio signal is not reproduced due to dropout or the tape on which the PCM audio signal is not recorded is reproduced, V
Since the SC start signal 33 is not affected by the PCM audio signal and is constantly generated, the subcode can be stably reproduced.

In the search mode in which the tape feeding speed is changed, the selection circuit 12 selects the address area end signal 40 generated by the block address counter 10 by the mode switching signal input from the mode switching signal input terminal 15. VSC timing generation circuit 13
Output to. The VSC timing generation circuit 13 generates the VSC start signal 33 at the timing of 1.1H from the output of the selection circuit 12 and outputs it to the VSC reproduction circuit 14, as in the normal reproduction. As a result, even when the time from the edge of the head switching signal of the subcode area 21 that is actually reproduced is different from that during normal reproduction, the block address 28 in the PCM audio signal can be used to know the area shift. The sub code area 21 can be corrected.

For example, when the rotation cycle of the rotary cylinder 1 is shortened, the PCM area 20 becomes earlier than the PCM area signal generated by the area generation circuit 11 as shown in FIG. Check circuit 9
By detecting the block address 28 at, the block address counter 10 is operated in synchronization with the area of the actually reproduced PCM audio signal, and the time when the block address counter 10 reaches a predetermined end address is set to P.
By considering it as the end of the CM area, the address end signal can be accurately output at the timing of the subcode area 21, and the subcode can be reproduced well. When the address end signal generated by the block address counter 10 is not used, the VSC start signal has the timing shown by the broken line in FIG.
You will not be able to play the subcode.

Even when the rotation cycle of the rotary cylinder 1 is delayed, the subcode area can be accurately generated in the same manner as shown in FIG. 4B. When the address end signal generated by the block address counter 10 is not used, the VSC start signal has the timing shown by the broken line in the figure, and in this case, the PCM area 20
The signal inside is reproduced as a subcode, and the probability of erroneous detection of the subcode increases.

As described above, by using the present invention, the subcode area can be accurately generated even in the search mode.

By the way, in the search mode, the track on which the rotary head scans the tracks on the tape extends over a plurality of tracks, and while the reverse azimuth track is being reproduced, the signal cannot be reproduced due to the azimuth loss. In this signal unreproducible section, the probability that the block address counter 10 malfunctions increases due to erroneous detection of the block address 28, and as a result, the VSC start signal 33 is generated at an incorrect timing. Therefore, it is necessary to prevent the block address counter 10 from malfunctioning in the search mode. In particular, when the sync signal 27 at the head of the track is erroneously detected and the block address is not reproduced well thereafter, the block address counter 10 malfunctions, so that the algorithm for detecting the head sync signal becomes a problem.

FIG. 5 shows a block diagram of a digital signal reproducing apparatus when the head synchronization signal detection algorithm in consideration of the above points is used. The operation of the apparatus shown in FIG. 5 will be described below with reference to the timing chart shown in FIG. In the reproduction signal 31 of FIG. 6, block addresses 60 to 64, 6
The ◯ mark added to 7 to 69 means that the block address was correctly reproduced.

(A) is an operation when there is no error in the reproduced signal 31. The sync detection circuit 5 sends a CRC check clock 52 to the error detection circuit 7 at the timing of the check code 29 based on the sync signal 27. The address check clock 53 is sent to the address check circuit 9 at the timing of the block address 28. During normal reproduction, the address check circuit 9 changes the head detection signal 51 sent to the block address counter from L to H when it is determined that there is no error as a result of error detection by the check code 29 for the head block (FIG. 6). Middle, the timing shown by the broken line).

In addition, in the search mode, in addition to the check result of the check code 29, the head synchronization detection circuit 50 checks whether the block address 61 of the next block is continuous with the block address 60 of the head block. , Head detection signal 51 only when continuous
To H (the timing shown by the solid line in FIG. 6). The block address counter 10 changes the load condition of the reproduction block address depending on the polarity of the head detection signal 51. For example, when the head detection signal 51 is L, loading is performed when the difference between the internal block address generated by the block address counter 10 and the reproduction block address is a predetermined value or less, and when the head detection signal 51 is H,
Load when the playback block addresses of consecutive blocks are consecutive. For example, the synchronization signal 6 in FIG.
If 3 and 64 are continuous, the load condition is satisfied.

As described above, when the reproduced signal 31 has no error,
Although there is no great difference between the operations in the normal reproduction and the search mode, if there is an error, the ability to protect erroneous data is different. For example, FIG. 6B shows an operation in the case where an error occurs in the reproduction signal 31 and the synchronization signal is detected before the head block is reproduced. In the same figure, 65 indicates that the data originally not a sync signal is the data reproduced as a sync signal because of a data error.

When the sync signal 65 is detected by the sync detection circuit 5, the CRC check clock 52 is set to 66 at the timing when the check code is reproduced based on the error sync signal 65.
And the reproduction signal 31 is generated by the error detection circuit 7.
Error detection. At the time of this error detection, there is a possibility of erroneous detection, and when it is judged that there is no error in the algorithm during normal reproduction, it is judged that the head synchronization signal has been detected, and the head detection signal 51 is inverted to H (see FIG. As indicated by the block address (b) 70, the block address counter 10 is incremented at the timing of the address check clock 53.

However, since the search mode algorithm checks the continuity of the block address 66 and the block address 67, if 65 is an erroneous synchronization signal, it is unlikely that both are continuous and head detection is performed. The signal 51 is never inverted to H (the timing shown by the solid line in the figure). Also, in the section where the head detection signal 51 is L, as shown in the block address (a) 70, by stopping the count-up of the block address counter 10, malfunction can be prevented.

As described above, in the search mode, by adding the block address continuity condition to the control of the head detection signal, it is possible to prevent the block address counter 10 from malfunctioning due to an error synchronization signal. This is because, especially in the search mode, when there are many signal unreproducible sections and the number of detected block addresses 28 decreases,
It is extremely effective in preventing malfunction of the block address counter 10.

When the block address continuation condition is taken into consideration in controlling the head detection signal, the head block is regarded as an error and is not used during normal reproduction. In the search mode, since it is originally impossible to reproduce all blocks, the present algorithm is adopted with an emphasis on protection of the block address counter 10.

In the above, PCM voice 20 and subcode 2
The description is for the case where the transmission rates of 1 are the same, and it is not necessary to change the processing in the reproducing circuit 3 between them.

However, PCM voice 20 and subcode 21
In some cases, it is necessary to change the fundamental frequency of the reproducing circuit due to the different transmission rates. For example, there is a mode in which the PCM voice 20 is recorded at a transmission rate of 16.615 MHz and the subcode is 11.58 MHz. In this case, the reproduction circuit 3 is provided with a PCM voice area 20 and a sub code area 2.
It is necessary to send the discrimination signal of 1. FIG. 7 shows a block diagram in this case. In the figure, reference numeral 70 denotes a VSC area signal generated by the VSC timing generation circuit, which becomes H at the timing of reproducing the subcode area 21 as shown in the timing of FIG.

The VSC area signal 70 changes to H based on the area end signal output from the selection circuit 12, and changes to L when the end mark 26 is detected. Further, in consideration of the case where the end mark is not detected, the edge of the head switching signal 30 is also reset to L. Figure 8 (a)
Indicates the operation timing at the time of normal reproduction, and the X mark hidden in the subcode area 21 indicates that the reproduction state of the subcode area is bad and the end mark 26 is not detected. When the end mark 26 is reproduced normally, 8
It is reset at the timing of 0.

When the end point of the PCM area signal 32 always comes before the edge of the head switching signal 30 as in normal reproduction, no problem arises, but the cycle of the head switching signal changes in the search mode, PCM area signal 3
A problem arises if the end point of 2 comes after the edge of the head switching signal 30.

As shown in FIG. 8B, in the search mode in the above state, when the reproduction state of the PCM voice 20 is bad and the end mark 26 is not detected, the block address counter 10 synchronizes with the reproduction signal 31. However, the PCM area signal 32 is generated at the same timing as the normal reproduction as shown in the figure, and the VSC signal 70 remains set to H after the edge of the head switching signal 30. I will end up. As a result, when reproducing the PCM audio signal 85 in the next track, the reproducing circuit 3
It becomes a mode to play the sub code 21, and the PC
It becomes impossible to reproduce the M audio signal 85.

Therefore, as shown in FIG. 9, the area generation circuit outputs the VSC area reset signal 71 even at a predetermined timing from the edge of the head switching signal 30 and before the reproduction timing of the PCM audio signal 20. Be sure to reset the VSC area signal to L. In FIG. 9, the VSC area reset signal 71 is output at a timing of 100H from the edge of the head switching signal 30. As a result, even in the same reproduction state as in FIG. 8B, the PCM audio signal 9 of the track next to the defective track is generated.
At the playback timing of 3, the VSC area signal becomes L,
This PCM audio signal 93 can be reproduced well.

Although the PCM voice 20 is recorded on the tape and the subcode area 21 is generated by using the PCM voice, the PC has been described above.
With a tape on which no M voice is recorded, it is very difficult to determine the area when performing a subcode search. Therefore, the sub code area signal is input from the outside and the PCM
A method of determining the area can be considered regardless of the area signal 32.

FIG. 10 is a block diagram of a device capable of inputting a VSC area input signal 101, which is an input signal of a subcode area, from a VSC area input terminal 100.

As shown in FIG. 11A, the VSC area input signal 10 input from the VSC area input terminal 100 is input.
1 is sent to the reproducing circuit 3 as the VSC area 70. VS
Although not shown, the C area input signal 101 can be accurately determined in the search mode by being generated by, for example, the servo 4 that controls the rotation of the rotary cylinder 1.

Further, as shown in FIG. 11 (b), VSC
By setting the rising edge of the area signal 70 to the falling point 111 of the PCM area signal, the area can be more accurately determined.

[0048]

According to the present invention, in a device for reproducing a sub-code recorded in an area different from that of a PCM audio signal, there is a signal reproduction impossible section such as a search mode and the signal changes after the rotation cycle of the rotary cylinder. However, the subcode area can be accurately determined, and the subcode detection rate can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital signal reproducing apparatus according to the present invention.

FIG. 2 is a diagram showing a recording format on a magnetic tape in FIG.

FIG. 3 is a timing chart showing the operation of the area generation circuit in FIG.

FIG. 4 is a timing chart showing the operation of the VSC reproduction circuit shown in FIG.

FIG. 5 is a block diagram showing another embodiment of the digital signal reproducing apparatus according to the present invention.

6 is a timing chart showing the operation of the head synchronization detection circuit in FIG.

FIG. 7 is a block diagram showing another embodiment of the digital signal reproducing apparatus according to the present invention.

FIG. 8 is a timing chart showing the operation of the VSC timing generation circuit in FIG.

9 is a timing chart showing the operation of the VSC timing generation circuit in FIG.

FIG. 10 is a block diagram showing another embodiment of the digital signal reproducing apparatus according to the present invention.

11 is a timing chart showing the operation of the VSC timing generation circuit in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Rotating cylinder, 3 ... Reproduction circuit, 4 ... Servo circuit, 5 ... Synchronization detection circuit, 7 ... Error detection circuit, 9 ... Address check circuit, 10 ... Block address counter, 11 ... Area generation circuit, 12 ... Selection circuit, 13 ... VSC timing generation circuit, 14 ... VSC reproduction circuit, 50 ... Head synchronization detection circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location G11B 27/28 F 8224-5D

Claims (12)

[Claims] 1. A track comprising a plurality of regions is formed,
A plurality of blocks in the first area in the track, at least a digital signal, a synchronization signal indicating the beginning of the block, and a block address indicating the recording order of the block in the first area, At least a check code for error detection added to the digital signal is recorded, and a second code different from the first field is recorded.
In a reproducing device for reproducing a recording medium in which a subcode indicating additional information to the digital signal is recorded in the area of, a servo circuit for generating a track reference signal indicating a reproduction cycle of the track, and the servo circuit, Area signal generation for generating a first digital area signal indicating the reproduction timing of the first area and a second digital area signal indicating the reproduction timing of the second area based on the output track reference signal A circuit, a digital signal reproducing circuit for reproducing the recording medium in accordance with the first digital area signal output from the area generating circuit, and the first area based on the digital signal reproduced by the digital signal generating circuit. An end-of-area detection circuit that detects the end point of the area and generates a digital area end signal; In the first mode in which the medium is reproduced at a normal speed, the second digital area signal output by the area signal generation circuit is selected, and in the second mode in which the recording medium is reproduced at a speed different from the normal speed. A selection circuit for selecting the digital area end signal output by the area end detection circuit; and a subcode reproduction circuit for reproducing the recording medium according to the area signal output by the selection circuit. The sub-code is reproduced according to the track reference signal, and in the second mode, the sub-code is reproduced according to a recording end timing of the digital signal reproduced by the digital signal generating circuit. apparatus. 2. The area end detection circuit according to claim 1, further comprising: a block address counter capable of loading the block address reproduced by the digital signal reproduction circuit. A digital signal reproducing apparatus characterized by detecting an end point of the first area. 3. The synchronization signal detection circuit according to claim 2, which detects the synchronization signal from the digital signal reproduced by the digital signal reproduction circuit, and the check code reproduced by the digital signal reproduction circuit. A check circuit for determining whether or not the digital signal reproduced by the digital signal reproducing circuit is correct, and the synchronization signal detection circuit detects the synchronization signal in the first region from a reproduction start point of the first region. And the end of the first area is detected after it is determined by the synchronization signal detection circuit that the synchronization signal has been detected in the first area until it is determined that the synchronization signal has not been detected. In the synchronization signal detection period up to the above, the error condition for changing the load condition of the block address of the block address counter is changed. In the first mode, the synchronization signal detection circuit first detects the first synchronization signal in the first area, and then the check circuit outputs the first synchronization signal. In the second mode, the synchronization signal detection circuit starts the synchronization signal detection section when the check code in the first block including First detecting the first synchronization signal in the first block, the check circuit checks the check code in the first block including the first synchronization signal, and determines that the check code is correct, and further determines the synchronization. Starting the synchronization signal detection section when the signal detection circuit detects a second synchronization signal in the second block reproduced after the first block. Digital signal reproducing apparatus according to claim. 4. The digital signal reproducing apparatus according to claim 3, wherein in the second mode, the operation of the block address counter is stopped in the sync signal undetected section. 5. A track comprising a plurality of regions is formed,
A digital signal is recorded by forming a plurality of blocks in a first area in the track, and a subcode indicating additional information to the digital signal is recorded in a second area different from the first area. In a reproducing device for reproducing a recorded recording medium, a servo circuit for generating a track reference signal indicating a reproduction cycle of the track, and a track reference signal generated by the servo circuit or the reproduced digital signal is used as a reference. And an area generation circuit that generates an area signal indicating the reproduction timing of the second area, and a recording medium that is capable of switching the transmission rate according to the area signal generated by the area generation circuit. Data reproducing circuit for extracting a clock from the reproduced signal, and the area generating circuit generated by the area generating circuit In accordance with the above, a subcode reproduction circuit for reproducing the subcode from the output of the data reproduction circuit is provided, and the area generation circuit detects at least the specific data indicating the end of the subcode by the subcode reproduction circuit. The digital signal reproducing apparatus is characterized in that the area signal is terminated when the signal is generated and at a specific time from the reference signal. 6. A track comprising a plurality of regions is formed,
A digital signal is recorded by forming a plurality of blocks in a first area in the track, and a subcode indicating additional information to the digital signal is recorded in a second area different from the first area. In a reproducing device for reproducing a recorded recording medium, a track reference signal indicating a reproduction period of the track and a servo circuit generating a first area signal indicating a reproduction timing of the second area, and at least a reproduction circuit. And an area generation circuit for generating a second area signal indicating the reproduction timing of the second area based on the digital signal, and an end point of the reproduction timing of the first area detected by the area generation circuit. An area decompression circuit for generating a time point from the end point of the first area signal to the end point of the first area signal as a third area signal, and the second area signal. Signal or the third area signal, and a clock extracted from the reproduced signal reproduced from the recording medium, which can switch the transmission rate according to the area signal output by the selection circuit. And a sub-code reproducing circuit for reproducing the sub-code from the output of the data reproducing circuit according to an area signal output from the selecting circuit, the sub-code reproducing circuit being generated with reference to the digital signal. It is possible to select whether to reproduce the sub-code according to a second area signal or to reproduce the sub-code according to the third area signal generated by the area expansion circuit. . 7. A track comprising a plurality of regions is formed,
A plurality of blocks in the first area in the track, at least a digital signal, a synchronization signal indicating the beginning of the block, and a block address indicating the recording order of the block in the first area, At least a check code for error detection added to the digital signal is recorded, and a second code different from the first field is recorded.
In a reproducing method of reproducing a recording medium in which a subcode indicating additional information to the digital signal is recorded in the area of, a servo unit for generating a track reference signal indicating a reproduction period of the track, and the servo unit. Area signal generation for generating a first digital area signal indicating the reproduction timing of the first area and a second digital area signal indicating the reproduction timing of the second area based on the output track reference signal Means, digital signal reproducing means for reproducing the recording medium in accordance with the first digital area signal output by the area generating means, and the first area from the digital signal reproduced by the digital signal generating means. Area end detecting means for detecting an end point of the digital area end signal and generating a digital area end signal, In the first mode in which the medium is reproduced at a normal speed, the second digital area signal output by the area signal generating means is selected, and in the second mode in which the recording medium is reproduced at a speed different from the normal speed. In the first mode, there are provided selection means for selecting the digital area end signal output by the area end detection means, and subcode reproduction means for reproducing the recording medium according to the area signal output by the selection means. The sub-code is reproduced according to the track reference signal, and in the second mode, the sub-code is reproduced according to a recording end timing of the digital signal reproduced by the digital signal generating circuit. Method. 8. The area end detecting means according to claim 7, further comprising a block address counting means capable of loading the block address reproduced by the digital signal reproducing means. A digital signal reproducing method characterized by detecting the end point of the first area. 9. The synchronizing signal detecting means for detecting the synchronizing signal from the digital signal reproduced by the digital signal reproducing means, and the check code reproduced by the digital signal reproducing means according to claim 8. Checking means for judging whether or not the digital signal reproduced by the digital signal reproducing means is correct, and the synchronization signal detecting means detects the synchronization signal in the first area from a reproduction start point of the first area. The sync signal undetected section until it is determined that the sync signal is detected, and the end of the first area is detected after the sync signal is detected by the sync signal detecting means in the first area. In the synchronization signal detection section up to the above, the load condition of the block address of the block address counting means is changed. In the first mode, the rear end detection means is provided, and the first synchronization signal is first detected in the first area by the synchronization signal detection means, and then the first synchronization is performed by the check means. When the check code in the first block including a signal is checked and it is determined that the check code is correct, the synchronization signal detection section is started, and in the second mode, the synchronization signal detection means causes the synchronization signal detection section to start. After first detecting the first synchronization signal in the area, the checking means checks the check code in the first block including the first synchronization signal and determines that the check code is correct, and further, The synchronization signal detection section is started when the second synchronization signal in the second block reproduced after the first block is detected by the synchronization signal detection means. Digital signal reproducing method characterized by and. 10. The digital signal reproducing method according to claim 9, wherein in the second mode, the operation of the block address counting means is stopped in the sync signal undetected section. 11. A second area different from the first area in which a track including a plurality of areas is formed and a plurality of blocks are formed in the first area in the track to record digital signals. In a reproducing method for reproducing a recording medium on which a subcode indicating additional information is recorded in the digital signal, a servo means for generating a track reference signal indicating a reproduction cycle of the track, and a servo means generated by the servo means. The track reference signal or the reproduced digital signal as a reference, and area generating means for generating an area signal indicating the reproduction timing of the second area, and the area signal generated by the area generating means. Data reproducing means capable of switching a transmission rate and extracting a clock from a reproduced signal reproduced from the recording medium A subcode reproducing means for reproducing the subcode from the output of the data reproducing means according to the area generating means generated by the area generating means, wherein the area generating means includes at least the subcode reproducing means. The area signal is terminated when specific data indicating the end of the sub-code is detected by the method, and at a specific time from the reference signal. 12. A second area different from the first area in which a track composed of a plurality of areas is formed and a plurality of blocks are formed in the first area in the track to record digital signals. In a reproducing method for reproducing a recording medium on which a subcode indicating additional information is recorded in the digital signal, a track reference signal indicating a reproduction period of the track, and a reproduction reference indicating a reproduction timing of the second area. Servo means for generating one area signal; area generating means for generating at least a second area signal indicating reproduction timing of the second area with reference to the reproduced digital signal; and area generating The time from the end point of the reproduction timing of the first area detected by the means to the end point of the first area signal is set to the third area signal. An area decompressing means for generating the signal, a selecting means for selecting the second area signal or the third area signal, and a transmission rate can be switched according to the area signal output by the selecting means. Data reproducing means for extracting a clock from a reproduced signal reproduced from the recording medium, and subcode reproducing means for reproducing the subcode from the output of the data reproducing means in accordance with an area signal output by the selecting means. Whether to reproduce the sub-code according to the second area signal generated with reference to the digital signal or to reproduce the sub-code according to the third area signal generated by the area expanding means. A digital signal reproducing method characterized by being selectable.