JP2664558B2 - Digital signal recording medium playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal recording medium reproducing method wherein information data obtained by demodulating a digital signal read from a signal recording medium is temporarily stored in a memory and then read at a fixed timing. Related to the device.

[0002]

2. Description of the Related Art A digital signal recording medium reproducing apparatus for reading and reproducing a signal recording medium on which information data such as music information is recorded by a digital signal using a pickup is known. As a representative example of such a reproducing apparatus, a CD player is known.

[0003] By the way, as is well known, in addition to information data such as music information, a CD-type disc is also accompanied by one reproduction.
Sub data called a sub coding signal in which one block is completed at a period of / 75 seconds is recorded. The sub-coding signal is composed of eight channels of P to W channels. Among them, the P channel contains position index data indicating the position of the beginning of the song, and the Q channel contains the absolute progress from the start point of the signal track. Position index data indicating time, elapsed time for each song, song number, and the like are included. Therefore, the CD player can perform a search operation by using the position index data,
Reproduction of a specified song, repetition of a specified section, and the like can be performed.

[0004] Further, as is well known, a digital signal adopting a strong error correction code having a strong error correction capability called CIRC is recorded on a CD-type disc, so that errors in demodulated information data are lost. Since detection and error correction can be performed, and an error detection code called CRC is added to the Q channel of the sub-coding signal on the CD disc, the data (Q code) of the Q channel is used. Can be detected.

[0005] By the way, as a CD player, there are a portable type and a type with a built-in radio cassette, etc. Such types of CD players are often subjected to external shocks and swings, and are provided with mechanical vibration isolation measures. However, when an external shock is applied, the signal recorded on the disc is transmitted. It is not rare that the light beam used for reading can correctly follow the signal (tracking control) or focus (focusing control) is not possible, so a more powerful new anti-vibration measure is desired. Was rare.

Further, a portable CD player, particularly a portable CD player, cannot set the power supply voltage to a sufficiently high level, and cannot rotate the disc with a sufficiently large torque relative to the weight of the disc. Therefore, it is remarkably weak against swings such as rolling, and a new anti-vibration measure has been desired from this point.

[0007] Therefore, the applicant of the present application firstly stores information data obtained by demodulating a digital signal read from a signal recording medium in a memory and then reads out the information data at a fixed timing. The speed of writing data to the memory is made faster than the speed of reading from the memory, and when it is determined that the information data has an error, the information data read from the memory is not interrupted, and the erroneous information is read. A digital signal recording medium reproducing apparatus which is capable of re-reading a signal recording medium read position by a pickup so as to re-read data so that a digital signal including information data which could not be correctly read due to an external shock or swing can be read again. (See Japanese Patent Application No. 2-3191984).

As described above, if only the demodulated information data is stored in the memory, data other than the information data included in the digital signal recorded on the signal recording medium is not stored in the memory. The capacity of the memory can be used effectively.

[0009]

However, if only the information data is stored in the memory, it is not necessary to write the re-read information data to the memory because the position index data indicating the reproduction position is not included. When resuming, it is difficult to write the re-read information data subsequent to the last information data written in the memory, and some countermeasures have been required. That is, when the memory is in an overflow state or when the error correction of the demodulated information data cannot be performed, the writing of the information data to the memory is stopped, and then there is a margin for writing the information data to the capacity of the memory, When the information data is correctly read again, the writing of the information data to the memory is restarted. At this time, it is necessary to detect the information data following the last information data written to the memory immediately before the writing is stopped. Was.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has a memory in which information data demodulated by a signal processing circuit for processing a digital signal read from a signal recording medium is written. And a write control circuit that controls writing of information data to the memory; and rereads sample data corresponding to the information data written to the memory before the writing to the memory is stopped by the write control circuit. A data match determination circuit that compares the information data with the newly obtained information data and determines that the pieces of information data match each other, and a position included in the digital signal along with the signal processing of the digital signal by the signal processing circuit. Detecting means for detecting index data as needed, and detecting means for stopping writing of information data to the memory Search means for searching for a digital signal read by a pickup with the position index data being detected as a target, wherein the data match determination is performed when the position index data near the target in the search means is detected by the detection means. The comparison of data by the circuit is started.

[0011]

According to the present invention, only the information data is stored in the memory, and it is necessary to restart the writing of the information data to the memory, following the last information data written in the memory. Information data is detected, and the sample data corresponding to the information data written in the memory is compared with the information data newly obtained by re-reading, so that the data is written to the memory immediately before the writing is stopped. Detected information data. In that case, a search is performed with the position index data detected at the time when the writing of the information data in the memory is stopped as a target, and the information data written in the memory is reread when the vicinity of the target is searched. Compare with newly obtained information data,
Even if the reproduction position is different, such as a non-signal portion such as between music pieces, the same information data can be obtained, so that it is possible to prevent a mistake in the point at which the writing of the information data to the memory is restarted. .

[0012]

FIG. 1 shows an embodiment of the present invention, and is a circuit block diagram of a portable CD player which can be carried and used. In this CD player, the linear velocity is higher than the rated linear velocity of a CD type disc. The disc is rotated at a speed of, for example, 2 times, and a signal is read from the disc at a higher speed than a normal CD player.

In FIG. 1, reference numeral 1 denotes a pickup having a photodetector for projecting a light beam onto a CD type disc (not shown) and receiving a light beam reflected on a signal surface of the disc, and 2 denotes the pickup. An RF amplifier 3 for amplifying and shaping an RF signal obtained from the photodetector 1 and driving the pickup 1 with an output signal from the photodetector of the pickup 1 obtained via the RF amplifier 2; Focusing control for focusing the light beam of the pickup 1 on the signal surface of the disk and tracking control for following the light beam to a signal track on the signal surface are performed, and control for sending the light beam in the radial direction of the disk is performed. It is a servo circuit.

Reference numeral 4 denotes signal processing of an output signal (serial digital signal) generated from the RF amplifier 2, and information data (audio data) and error detection / correction data for error detection / correction of the information data. A signal processing circuit for demodulating various types of data. The signal processing circuit 4 includes an error detection and correction means 5 for detecting and correcting errors in the information data to be demodulated. The terminal 5a is provided so that the signal level changes from "L" to "H" when the error cannot be corrected by the means 5, and a non-correctable signal indicating that the error could not be corrected is generated. . Further, the signal processing circuit 4 is provided with an interpolating means 6 for delaying the information data and interpolating the missing information data which could not be corrected by the error detection and correction means 5 with the information data before and after the information data. When the erroneous information data continues so that interpolation cannot be performed, the interpolation means 6 enters a hold state in which the last correct information data is output until new correct information data is obtained. It is made as follows.

Reference numeral 7 denotes a first RAM for temporarily storing digital signals for rearranging the digital signals when demodulating various data by the signal processing circuit 4. The first RAM 7 is controlled by the signal processing circuit 4 to write and read digital signals. The timing of the writing and reading is controlled by a general CD player according to the rotation speed of the disk, that is, the speed at which signals are read from the disk. It has been made faster.

Reference numeral 8 denotes a program in which basic programs such as a method for reproducing a disk, various searching methods, and a method for introducing focusing of the pickup 1 are written, and performs various basic operation controls, and also controls time display and input control of operation keys. This is a system control circuit composed of a microcomputer that performs the operation. Further, the system control circuit 8 includes a Q code detecting means 9 for detecting Q channel data (Q code) from the sub-coding signal extracted by the signal processing circuit 4 as needed, and the servo circuit 3 A track jump control means 10 for supplying a track jump signal for displacing the reading position (trace position) in the radial direction of the disk is provided.

Reference numeral 11 denotes a serial / parallel conversion circuit for converting the information data of the serial digital signal demodulated by the signal processing circuit 4 into a parallel digital signal, and reference numeral 12 temporarily stores the information data output from the serial / parallel conversion circuit 11. The second RAM 13 is the second RAM 1
2 is a RAM management circuit that generates a write address for controlling writing of information data to the second RAM 2 and generates an address for reading information data from the second RAM 12.

The RAM management circuit 13 includes a second RAM 1
The timing at which information data is written to the signal processing circuit 4
The timing at which the information data is output from the second RAM 12 is matched with the sampling frequency at the time of recording the information data on the disk, and the timing at which the information data is written corresponds to the timing at which the information data is read. The writing and reading of the second RAM 12 are controlled so as to be faster than the timing.

A monitor 14 monitors a write address and a read address of the RAM management circuit 13, monitors an overflow of the second RAM 12, detects a state of occurrence of a non-correctable signal from the error detection and correction means 5, and interpolates based on the state of occurrence. By judging that the interpolation capacity of the means 6 is exceeded, the timing of stopping and restarting the writing of the information data to the second RAM 12 is detected, and the RAM management circuit 13 is controlled in accordance with the detected output to control the information to the second RAM 12. This is a write control circuit that controls data writing. Further, the write control circuit 14 includes a second RAM 1
When an overflow is detected, an overflow signal indicating the fact is generated, and when the interpolation capability of the interpolation means 6 is exceeded, an interpolation impossible signal indicating the fact is generated. A track jump signal for returning the reading position (trace position) of the data by one track is generated.

Reference numeral 15 is provided in the system control circuit 8,
WOK signal generating means for generating a writable signal (WOK signal) indicating that writing of information data to the second RAM 12 is possible. WOK signal generating means 1
5 generates a WOK signal in response to the occurrence of an overflow signal and an interpolation impossible signal from the write control circuit 14 and in accordance with the Q code detection status by the Q code detection means 9 and the operation status of the track jump control means 10; Specifically, when the overflow signal or the interpolation impossible signal is generated, the WOK signal is not generated, and the WOK signal is not generated simultaneously with the generation of the track jump signal from the track jump control means 10. When the jump is completed and a Q code indicating that it is within the target range of the disc (within three frames before and after the target frame) is detected, a WOK signal is generated.

Reference numeral 16 denotes a shift register (shown in FIG. 2) in which the information data output from the serial / parallel conversion circuit 11 is written in synchronization with the timing of writing the information data to the second RAM 12, and an overflow of the second RAM 12 is detected. And a latch circuit (shown in FIG. 2) for latching the information data written in the shift register when the information is written in the shift register. A data coincidence determination circuit that determines whether or not they match, and sets the timing for restarting the writing of information data to the second RAM 12.

Reference numeral 17 denotes a parallel-to-serial conversion circuit for converting information data of a parallel digital signal read from the second RAM 12 into a serial digital signal, and reference numeral 18 converts information data output from the parallel-serial conversion circuit 17 to an analog signal. It is a D / A converter.

Next, the operation of FIG. 1 will be described.

When the disk is traced by the light beam projected from the pickup 1, the signal recorded on the disk is read by the pickup 1 and the RF signal is read.
The signal is supplied to the RF amplifier 2 as a signal (high-frequency signal).
The RF signal is amplified by the RF amplifier 2, waveform-shaped, and supplied to the signal processing circuit 4 as a digital signal. The signal processing circuit 4 demodulates the digital signal and extracts various data included in the digital signal. Here, when the digital signal is processed by the signal processing circuit 4, the data is rearranged by using the first RAM 7. In FIG. 1, the disk is faster than the rated linear velocity of a normal CD player. Since the signal processing circuit 4 is rotated, the amount of the digital signal input to the signal processing circuit 4 per unit time is larger than before, so that the write and read timings of the first RAM 7 are faster in accordance with the input speed of the digital signal. It is.

When signal processing is performed by the signal processing circuit 4 to extract information data (audio data), the information data is subjected to error detection and error correction processing by the error detection and correction means 5, and interpolating means 6. The missing information data is interpolated. The information data output from the signal processing circuit 4 is converted from a serial digital signal to a parallel digital signal by a serial / parallel conversion circuit 11 and then converted to a RAM management circuit 1.
3 is written to the second RAM 12 in accordance with the write address from # 3. The information data written in the second RAM 12 is read in accordance with a read address from the RAM management circuit 13, and the information data is converted from a parallel digital signal to a serial digital signal by a parallel / serial conversion circuit 17. Is converted to The information data output from the parallel-to-serial conversion circuit 17 is converted into an analog signal by a D / A converter 18 and separated into stereo left and right channel components. ).

The timing of writing the information data to the second RAM 12 is set to be high-speed in accordance with the timing of outputting the information data from the signal processing circuit 4. The second R is read so that the information data is read out at the sampling frequency used for storing the information data.
It is slower than the writing timing to AM12. Therefore, when the reproduction proceeds, the second RAM 12 eventually overflows.

Here, the overflow of the second RAM 12 is detected by the write control circuit 14 by monitoring the write address and the read address of the RAM management circuit 13, and an overflow signal indicating the overflow is output from the write control circuit 14. It is supplied to the control circuit 8. Therefore, the track jump control means 1
From 0, a track jump signal for returning the disk reading position by the pickup 1 by one track is generated.
By returning the track, the same portion on the disk is repeatedly traced. In this case, the second RA
Since the information data written so far is sequentially read from M12, the information data is continuously reproduced without interruption.

When the overflow of the second RAM 12 is detected, a stop signal for stopping the writing to the second RAM 12 is output by the write control circuit 14 from that point, and the writing of the information data to the second RAM 12 is stopped. Therefore, only the reading of the information data is performed, and the amount of the information data written in the second RAM 12 decreases.

On the other hand, when the digital signal read by the pickup 1 is processed by the signal processing circuit 4, the Q code included in the digital signal is detected by the Q code detecting means 9 as needed, and the detection is performed. The obtained Q code is stored in a RAM (not shown) in the system control circuit 8. Therefore, the Q code at the time when the second RAM 12 overflows is stored in the RAM in the system control circuit 8, so that when the second RAM 12 overflows, the track jump control means 10 is operated and the pickup 1 The trace position is returned by one track of the disk, and the search is performed with the Q code stored in the RAM in the system control circuit 8 as a target. Then, the tracing position by the pickup 1 approaches the digital signal portion including the Q code at the time when the tracing position overflows, and the Q within the target range
When the code is detected by the Q code detecting means 9, the information data output from the serial / parallel conversion circuit 11 is taken into the data coincidence determination circuit 16.

Here, the data coincidence determination circuit 16 stores information data of a predetermined number of samples until the overflow of the second RAM 12 occurs, and when the information data from the serial / parallel conversion circuit 11 is fetched. The information data of the data match determination circuit 1
6 is compared with the information data stored in. And
When the coincidence of the information data is detected, a coincidence signal indicating that is detected is supplied to the write control circuit 14, and the second R
Writing of the information data to the AM 12 is restarted.

When the writing of the information data into the second RAM 12 is resumed, the resumed information data is stored in the second R12.
The last information data at the time when the writing is stopped due to an overflow in the AM 12 is sequentially written from the address next to the address where the last information data is stored, and is written following the last information data. Then, the second RAM 1
Since the information data whose writing to the data 2 has been resumed is continuous on the disk with the last information data, correct reproduction is continuously performed.

On the other hand, if a match signal cannot be obtained from the data match determination circuit 16 for some reason, the write control circuit 14 determines whether or not the write address and read address of the RAM management circuit 13 match and the second R
When the information data in the AM 12 is detected to be empty, the second
The writing to the RAM 12 is restarted. In this case, although the read information data is not connected correctly, the information data is written continuously to the last information data in the second RAM 12 so that the reproduction is not interrupted, and the newly written information is continuously written to the last information data. Data is read out.

By the way, if the signal of the disk is not correctly read by the pickup 1 due to an external shock or swing, or a scratch or dirt on the disk, the signal processing circuit 4 cannot correct the error of the information data. An uncorrectable signal is generated from 5a. When the write control circuit 14 detects that the non-correctable signal has been continuously generated at the interpolation capability of the interpolating means 6 or more, the write control circuit 14 generates an interpolation impossible signal,
The generation of the WOK signal from the K signal generation means 15 is stopped. Therefore, the RAM is controlled via the write control circuit 14.
The management circuit 13 is controlled to stop the writing of information data into the second RAM 12, and the track jump control means 10 generates a track jump signal for causing the pickup 1 to jump the track so as to return the trace position of the disk. Immediately before a digital signal block containing information data that cannot be corrected is read, the trace position of the disk by the pickup 1 is returned to search for the Q code of the digital signal block read.

If erroneous information data is generated due to an external impact or swing, the erroneous information data can be read again by tracing the same portion of the disk again by the pickup 1, and the correct information data can be read. Can be obtained, so that the data match determination circuit 16
The same information data as the information data immediately before the error is input,
The data match determination circuit 16 generates a match signal. The comparison of the information data by the data match determination circuit 16 is not performed immediately after the track jump of the trace position is completed, but is performed from the vicinity of the frame including the final information data written in the second RAM 12. At this time, the detection of the Q code is performed targeting the frame including the Q code corresponding to the final information data. In this case, even if the Q code is not detected in consideration of the failure of the Q code capture, A target frame is detected by adding one frame to the time information of the Q code stored at each timing when the frame is reproduced. Then, when the trace position reaches the vicinity of the target frame, information data to be compared is taken into the data coincidence determining circuit 16, and the data data acquired by the data coincidence determining circuit 16 are compared.

When a coincidence signal is generated by the data coincidence determination circuit 16, a start signal is generated from the write control circuit 14, and the correct information data read continuously from the information data immediately before the incorrect information data is read. Will be written.

Accordingly, in this case, the information data can be reproduced continuously without interruption.

On the other hand, when erroneous information data is generated due to a scratch or dirt on the disk, the erroneous information data cannot be read again even if the same portion of the disk is traced again by the pickup 1, and the correct information data cannot be read. I can't get it. Therefore, a match signal is not obtained from the data match determination circuit 16 and the information data in the second RAM 12 is only consumed, and the information data in the second RAM 12 may eventually become empty by the write control circuit 14. Is detected. When the detection is performed, tracing the same portion of the disc again is stopped, the track jump control means 10 is operated to trace the next portion, and a start signal is generated from the write control circuit 14, Writing of the information data to the 2RAM 12 is restarted. In this case, the read information data is not correctly connected to the information data written in the second RAM 12, but the information data is written continuously to the last information data in the second RAM 12 so that the reproduction is not interrupted. The newly written information data is read out continuously from the last information data.

As described above, since the range in which the information data is compared by the data match determination circuit 16 is limited, the possibility that the same information data can be obtained regardless of the reproduction position is reduced. Can do the second
It is possible to reduce the possibility of mistakenly rewriting the point at which the writing of the information data into the RAM 12 is restarted. In addition, by doing so, the following problems can be solved.

When the range in which the information data is compared by the data coincidence determination circuit 16 is not restricted, the second RAM 12 is used during reproduction of a non-signal portion such as a space between music pieces on a disk.
The track jump by the pick-up 1 causes an error in the information data so that the error correction of the information data cannot be continuously performed so as to exceed the interpolation capability of the interpolation means 6, or the trace position by the pickup 1 becomes a non-signal portion such as between music pieces. When returned, even if the trace position is a point different from the point where the writing of the information data into the second RAM 12 is stopped, the reread information data is no-signal data and is stored in the data match determination circuit 16. May match the information data for the sample. When this occurs, the second RAM is used at the point where the trace position by the pickup 1 is returned by the track jump.
The writing of the information data into the second RAM 12 is restarted, and before the reproduction to the point where the track jump is performed, the overflow of the second RAM 12 occurs again, the track jump is performed again, and the reproduction position is reversed. Occurs.

However, if the range in which the information data is compared by the data match determination circuit 16 is limited, the comparison is not performed immediately after the track jump is performed. Even if the same information data as the data is read by the pickup 1, the writing of the information data to the second RAM 12 is not restarted, and the information data stored in the second RAM 12 is consumed. Therefore, when the writing of the information data to the second RAM 12 is restarted and the second RAM 12 again overflows, the trace position by the pickup 1 does not exceed the point where the track jump is performed, and the reproduction is performed. The problem that the position is reversed does not occur.

Next, the data coincidence determination circuit 16 is used to restart the writing of the information data into the second RAM 12.
The method of comparing information data according to the above will be described in detail with reference to FIG.

FIG. 2 shows a specific configuration of the data match determination circuit 16 in FIG. 1 and its peripheral circuits. In FIG. 2, reference numeral 20 denotes a shift register into which serial information data demodulated by the signal processing circuit 4 is sequentially written, and reference numeral 21 denotes one sample (1
6 is a latch circuit for latching the information data of the shift register 20 when the information data is written with good division. The shift register 20 and the latch circuit 21 correspond to the serial / parallel conversion circuit 11 of FIG. Is composed.

Reference numeral 22 denotes a shift register in which the lower 8 bits of the information data latched by the latch circuit 21 are written in parallel, and the same bits are sequentially written by 16 samples. Reference numeral 23 denotes a shift register which is written in the shift register 22. The latch circuit 23 latches data of the shift register 22 by an overflow signal and an interpolation impossible signal generated from the write control circuit 14.

A comparison circuit 24 compares the data of the shift register 22 with the data of the latch circuit 23 for each bit and for each sample. The comparison circuit 24 compares each time data is written to the shift register 22. I do.

Reference numeral 25 denotes a shift register into which an uncorrectable signal generated from the terminal 5a of the signal processing circuit 4 is sequentially written. The shift register 25 delays information data output from the signal processing circuit 4 by the interpolation means 6. The transmission timing of the uncorrectable signal generated from the terminal 5a is delayed in order to correct the delay (4 bits).

Reference numeral 26 denotes a shift register into which the uncorrectable signal data output from the shift register 25 is sequentially written.
The non-correctable signal data is written for each bit in correspondence with the data written in.

Reference numeral 27 denotes a latch circuit for latching the uncorrectable signal data written in the shift register 26. Data latched by the comparing circuit 24 in accordance with the uncorrectable signal data latched by the latch circuit 27 is provided. It is determined.

The shift register 22, the latch circuit 23, the comparison circuit 24, the shift registers 25 and 26, and the latch 27 constitute the data match determination circuit 16 in FIG.

Next, the operation of FIG. 2 will be specifically described.

If the overflow of the second RAM 12 is detected by the write control circuit 14 or the error correction of the information data demodulated by the signal processing circuit 4 cannot be performed continuously, and the interpolation capability of the interpolation means 6 is exceeded. If the write control circuit 14 detects that the track jump control means 10 has been detected by the write control circuit 14, the track jump control means 10 is operated by the overflow signal or the interpolation impossible signal generated by the write control circuit 14, and the track position of the disk by the pickup 1 is returned by one track. It is. At this time,
The data written in the shift register 22 is latched by the latch circuit 23. Here, the lower 8 bits of the information data latched by the latch circuit 21 of the serial / parallel conversion circuit 11 are written in the shift register 22 in parallel. The latch circuit 21 of the serial / parallel conversion circuit 11 is used to generate parallel information data written in the second RAM 12. Therefore, the data written in the shift register 22 corresponds to the information data stored in the second RAM 12. In this case, the lower 8 bits of the information data immediately before the writing to the second RAM 12 is stopped are stored in the shift register 22. , The data of the shift register 22 is latched by the latch circuit 23.

On the other hand, when an overflow signal or an interpolation impossible signal is generated from the write control circuit 14, the writing of the information data to the second RAM 12 is stopped, and the lower register of the information data from the latch circuit 21 is stored in the shift register 22. The writing of 8 bits is stopped. When the trace position of the disk by the pickup 1 is returned by one track, a search is performed targeting the position index data of the Q code in the digital signal read immediately before the track jump is performed. When the trace position approaches the digital signal portion including the Q code having the target position index data as a result of the search, a WOK signal is generated from the WOK signal generating means 15, and the writing of data to the shift register 22 is restarted. ,
The comparison circuit 24 starts comparing the data in the shift register 22 with the data latched in the latch circuit 23. Here, in order to prevent the erroneous information data, which could not be corrected, from being compared by the comparing circuit 24 and to generate an erroneous comparison output, the shift register 26 corrects the erroneous information data so as to recognize the erroneous information data. The data to be compared by the comparison circuit 24 is selected by using the data of the latch circuit 27 into which the uncorrectable signal is written and the uncorrectable signal data of the shift register 26 is latched.

Then, a digital signal containing the information data immediately before the writing of the information data into the second RAM 12 is stopped is read out, and the immediately preceding information data demodulated by the signal processing circuit 4 is transferred to the shift register 20 and the latch circuit. 21 is written to the shift register 22 via
The pattern of the data written in the shift register 22 and the pattern of the data written in the latch circuit 23 become the same, and the comparison circuit 24 detects the coincidence of the data in the shift register 22 and the latch circuit 23, and generates a coincidence signal. Is done. Therefore, the write control circuit 14 is activated, and the latch circuit 21 of the serial / parallel conversion circuit 11 is operated.
Is written into the second RAM 12 again. At this time, since the information data latched by the latch circuit 21 is continuous on the disk with the last information data written in the second RAM 12, the information data in the second RAM 12 is correctly connected. .

In the comparison between the information data of a predetermined number of samples up to the last information data written in the memory and the information data newly obtained by rereading, all the data to be compared necessarily match. Therefore, it is not necessary to determine a match, and it is possible to determine a match based on the fact that most of the compared data matches.Also, it is not always necessary to compare all of the sample information data. Instead, the data match may be determined by comparing only appropriately selected information data, and the data match in the claims includes such meaning.

[0054]

As described above, according to the present invention, the sample data corresponding to the information data written in the memory is compared with the information data newly obtained by re-reading, and the data match. And the writing of the information data to the memory is resumed, so that the management of the information data to be stored in the memory in the unit of the sample of the information data smaller than the unit of the address recorded on the signal recording medium is performed. In particular, since the comparison between the sample data and the information data newly obtained by rereading is started when the search means is close to the target, the management of the information data stored in the memory is controlled by the information data. Reduces the possibility of mistakenly re-writing the information data to the memory when performing the operation in sample units. It can be.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a main part of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pickup 4 Signal processing circuit 5 Error detection and correction means 6 Interpolation means 8 System control circuit 9 Q code detection means 10 Track jump control means 12 Second RAM 14 Write control circuit 15 WOK signal generation means 16 Data match determination circuit 22 Shift register 23 Latch Circuit 24 Comparison circuit

Claims (1)

(57) [Claims] 1. A digital signal recorded on a signal recording medium includes position index data indicating a reproduction position, and the reproduction position of the signal recording medium can be detected using the position index data. Information data that is configured so that error correction of the information data obtained by demodulating the digital signal read by the pickup can be performed, and cannot be reproduced by detecting that the error correction of the information data was not possible. Information data demodulated by a signal processing circuit that performs signal processing on a digital signal read from a signal recording medium in a digital signal recording medium reproducing device configured to return a reading position by a pickup to reread a digital signal including And a write control circuit that controls writing of information data to the memory. Comparing the sample data corresponding to the information data written in the memory before the writing to the memory is stopped by the writing control means with the information data newly obtained by re-reading,
A data match determining circuit determines that the data match, a detecting means for optionally detecting the position index data included in the digital signal with the signal processing of the digital signal by the signal processing circuit, the memory and a search means for searching for a digital signal read by the pickup position indication data detected by said detecting means when the writing of the information data is abandoned to the goal, and the sample data by the data match determining circuit Reading
That the information data newly obtained by the reconciliation matches
Writing information data to the memory when determined
And a comparison of data by the data match determination circuit is started when the position index data near the target in the search means is detected by the detection means. Recording medium playback device.