JP2567763B2 - Variable playback speed circuit for disc playback device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention writes a digital signal read from a disc on which information data is recorded by a digital signal into a memory circuit and reads the signal written in the memory circuit to perform a reproducing operation. The present invention relates to a disc reproducing apparatus configured as described above.

[0002]

2. Description of the Related Art There is known a disc reproducing apparatus which performs a reproducing operation by reading a signal from a disc on which information data such as music is recorded by a digital signal with a pickup. Such a disc reproducing device is generally configured to reproduce the information data at a constant speed by once writing the digital signal read from the disc into the memory circuit and then reading it by the read clock. A CD player is known as a typical example of such a disc reproducing apparatus.

By the way, as is well known, in the CD type disc, in addition to the main data signal such as music information, sub-data called sub-coding signal in which one block is completed in a cycle of 1/75 second accompanying reproduction. The signal is stored.
Such a sub-coding signal is a P. It is composed of eight channels Q to W, of which the P channel contains position index information indicating the position of the beginning of the song, and the Q channel has the absolute elapsed time from the start point of the signal track, The position index information indicating the elapsed time and the song number is included. Therefore, the CD player can perform a search operation by using the position index information, and can perform a reproduction operation of a designated music piece and a repeat reproduction operation of a designated section.

In addition, a CIRC disc has a CIRC.
Since a digital signal to which an error correction code referred to as is added is recorded and an error detection code referred to as CRC is added to the Q channel of the sub-coding signal, such a signal is used in a CD player. The error correction operation and the error detection operation of the reproduced information data can be performed.

In such a CD player, for example, when the signal recorded on the disc is reproduced faster than the normal speed, the rotational speed of the disc is made higher than the normal speed.

[0006]

In the system in which the reproduction speed of the signal reproduced from the disk is changed by changing the rotation speed of the disk, not only the response characteristic at the time of changing the speed is bad but also the variable range of the reproduction speed is There is a problem of being narrow. The present invention is intended to provide a reproduction speed variable circuit in which such a point is improved.

[0007]

SUMMARY OF THE INVENTION A reproducing speed variable circuit of the present invention is a digital signal from a disk which is faster than the reading speed of a signal stored in a memory circuit in which a digital signal read from a disk is written. Reading means, a memory control circuit for controlling a signal writing operation to the memory circuit and a reading operation from the memory circuit, and a digital signal read from the memory circuit is written and the reading speed is variable. A buffer memory circuit and a system control circuit for controlling the operation of the reading means according to the capacity of the digital signal in the memory circuit detected by the memory control circuit and controlling the reading speed from the buffer memory circuit. It is composed of

[0008]

According to the present invention, when the memory control circuit detects that the capacity of the digital signal in the memory circuit has reached the predetermined amount, the reading position on the disk by the reading means is returned to the rear and the reading to the memory circuit is performed. The writing operation of the digital signal is temporarily stopped, and the reading operation of the digital signal written in the buffer memory circuit from the memory circuit is performed so that the capacity of the signal stored in the buffer memory circuit becomes a predetermined amount or more. It is something that is done.

[0009]

1 is a block circuit diagram showing an embodiment of the present invention. In the figure, 1 is a pickup having a photodetector for projecting a light beam onto a CD type disc (not shown) and receiving the light beam reflected by the signal surface of the disc, 2 is a photodetector for the pickup 1. An RF amplifier circuit 3 for amplifying an RF signal obtained from the device and for shaping the waveform, and a focusing control 3 for focusing the light beam of the pickup 1 on the signal surface of the disc based on the signal obtained through the RF amplifier circuit 2. And a servo signal processing circuit 4 for performing tracking control for causing the light beam to follow a signal track on the signal surface and controlling the feeding operation of the entire pickup 1, 4 is the RF amplification circuit 2
The digital signal processing circuit 5 performs digital signal processing of the output signal (serial digital signal) output from the digital signal processing circuit 5 and demodulates various signals. Data 5 is used when the digital signal processing circuit 4 demodulates various signals. A first memory circuit for temporarily storing data for sorting
Reference numeral 6 is a system control for displaying a reproduction time and the like on a display 7 by using a sub-coding signal which is position index information demodulated by the digital signal processing circuit 4 and controls various operations according to an operation of an operation switch 8. Circuit.
Reference numeral 9 denotes a second memory circuit in which a digital (parallel) signal output from the digital signal processing circuit 4 is written, 1
Reference numeral 0 denotes a memory control circuit for controlling a signal writing operation to the second memory circuit 9 and a signal reading operation stored in the second memory circuit 9, and 11 denotes a memory control circuit stored in the second memory circuit 9. The digital signal is compared with the digital signal output from the digital signal processing circuit 4, and the comparison output is compared with the memory control circuit 10.
A comparator circuit 12 for supplying an error to the Q channel data of the sub-coding signal demodulated by the digital signal processing circuit 4 and an error detection circuit for supplying the detected output to the system control circuit 6; 2 A buffer memory circuit in which the digital signal read from the memory circuit 9 is written and the reading speed is variable, and 14 is the buffer memory circuit 13
A parallel-serial conversion circuit that converts the parallel digital signal read out to a serial digital signal,
Reference numeral 15 denotes a D / A converter to which the serial digital signal output from the parallel / serial conversion circuit 14 is input and which converts the signal into an analog signal. Reference numeral 16 is a reproduction speed changing operation means that is operated when the reproduction speed is changed, and is configured to change the read speed from the buffer memory circuit 13 by the operation of the system control circuit 6.

In the CD player configured as described above, the speed at which the disc is traced by the pickup 1 is higher than the standard tracing speed of the disc in a normal CD player (for example, twice) (higher than the rated linear velocity). The disk is rotated in step 1.), and the speed of writing and reading signals to and from the first memory circuit 5 is increased in accordance with the trace speed of the disk. Further, the writing speed of the signal to the second memory circuit 9 is set to be high in accordance with the reading speed of the first memory circuit 5, but the reading speed is slower than the writing speed and the buffer memory circuit 13 It is configured to change in accordance with the change in the signal reading speed.

Here, when the capacity of the digital signal (audio data) stored in the second memory circuit 9 reaches the first predetermined amount near the overflow, the memory control circuit 10 sends a signal to that effect to the system. It is adapted to be supplied to the control circuit 6. When the system control circuit 6 receives such a signal, the system control circuit 6 outputs a signal for controlling the operation of the servo signal processing circuit 3 so that the pickup 1 repeatedly traces the same signal track of the disk. It is configured. Also,
When such an operation is performed, the operation of the memory control circuit 10 interrupts the writing operation of the digital signal to the second memory circuit 9, and only the reading operation from the second memory circuit 9 is performed. Then, the signal stored in the second memory circuit 9 decreases with the reading operation, and when the capacity of the digital signal stored in the second memory circuit 9 becomes less than or equal to a second predetermined amount, memory control is performed. A signal to that effect is supplied from the circuit 10 to the system control circuit 6. When the system control circuit 6 receives such a signal, the system control circuit 6 picks up the pickup 1
The signal for controlling the operation of the servo signal processing circuit 3 is output so as to advance the trace position of the disk by the above.

Further, the system control circuit 6 controls the servo signal processing circuit 3 in accordance with the detection output from the error detection circuit 12, and the error detection circuit 12 causes an error in the Q channel data of the sub-coding signal to occur several times in succession. When it is detected, the audio data of the digital signal portion including the Q channel data having an error due to the operation of the memory control circuit 10 is prevented from being written in the second memory circuit 9 and the disc by the pickup 1 is used. Is configured to retract the trace position of.

The error in the Q channel data of the sub-coding signal can be detected by the CRC error detection code included in the Q channel data. If there is an error in the Q channel data, there is a possibility that an error has occurred in the audio data in the digital signal read in 1/75 seconds until one block of the Q channel data is completed. It can be judged to be large. Therefore, if the data of the Q channel is erroneous several times in succession, it is very likely that the audio data in the digital signal during that time is erroneous. Incidentally, CD
Since the error correction processing called CIRC is applied to the audio data of the system, some errors of the audio data can be corrected, but significant errors of the audio data cannot be corrected.

Further, the error detection circuit 12 supplies a signal to that effect to the system control circuit 6 even when the Q channel data itself generated when the signal cannot be read by the pickup 1 is not detected. It is configured so that audio data is not written in the second memory circuit 9 and the trace position of the disc of the pickup 1 is retracted by the action of the servo signal processing circuit 3.

When the servo signal processing circuit 3 moves the trace position of the disk back by the pickup 1 and the digital signal can be read again, the audio data output from the digital signal processing circuit 4 by the comparison circuit 11 and the second memory circuit. The comparison with the audio data stored in 9 is made. In this case, the audio data from the digital signal processing circuit 4 is sequentially compared with each of the plurality of audio data stored in the second memory circuit 9 in the written order. Then, when the same audio data is detected several times in succession, the control operation of the memory control circuit 10 causes the memory addresses of the same audio data portion to overlap so that the audio data output from the digital signal processing circuit 4 is changed. The write operation to the second memory circuit 9 is restarted. Therefore, when the signal track of the digital signal portion including the erroneous Q channel data is traced again and the correctly read audio data is output from the digital signal processing circuit 4, the audio data is converted into the Q channel data. It is written in a predetermined address of the second memory circuit 9 so as to be correctly continuous with the audio data of the digital signal portion before the error is detected. Here, the second memory circuit 9
Is a device having a storage capacity such that audio data read from the second memory circuit 9 is not lost while the digital signal read by mistake is read again, and the digital signal is processed and written in the second memory circuit 9. used. Therefore, the audio data read from the second memory circuit 9 is not interrupted even if the digital signal read by mistake is read again.

The read operation of the digital signal stored in the buffer memory circuit 13 is performed based on the read clock signal output from the system control circuit 6, and the read speed is the reproducing speed changing operation means. It is configured to be variable by 16 operations. Then, the read speed of the digital signal stored in the second memory circuit 9 is also changed in response to the change in the read speed of the signal from the buffer memory circuit 13, and the control operation of such read operation is performed by the buffer. It is performed so that the capacity of the digital signal stored in the memory circuit 13 becomes equal to or larger than a predetermined amount.

The present invention is configured as described above, and the operation will be described below. When the track of the disc is traced by the light beam projected from the pickup 1, the signal recorded on the disc is read by the pickup 1 and is supplied to the RF amplification circuit 2 as an RF signal (high frequency signal). The RF signal is amplified by the RF amplification circuit 2 and waveform-shaped and applied to the digital signal processing circuit 4 as a digital signal. The digital signal processing circuit 4 demodulates the digital signal output from the RF amplification circuit 2 and extracts various data signals contained in the digital signal. The audio data is extracted by the signal processing operation of the digital signal processing circuit 4, and the audio data is subjected to error correction processing based on the error correction data included in the digital signal. The error correction processing operation is performed by the data rearrangement operation using the first memory circuit 5.

The audio data output from the digital signal processing circuit 4 is written in the second memory circuit 9 by the operation of the memory control circuit 10 and the second data is written in the second memory circuit 9.
It is read from the memory circuit 9. The digital signal read from the second memory circuit 9 is written in the buffer memory circuit 13, and the reading operation is performed so that the capacity of the digital signal stored in the buffer memory circuit 13 becomes constant.

The read operation of the digital signal stored in the buffer memory circuit 13 is performed based on the read clock signal output from the system control circuit 6. Parallel audio data is read from the buffer memory circuit 13, and the audio data is input to the parallel / serial conversion circuit 14 and converted into serial audio data. The serial audio data output from the parallel / serial conversion circuit 14 is applied to the D / A converter 15 to be converted into an analog signal and separated into left and right channel signals and output. Therefore, if the analog signals of the left and right channels output by the D / A converter 15 are supplied to an audio circuit (not shown) and amplified, the signals such as music recorded on the disc can be reproduced and heard. .

The digital signal processing circuit 4 also extracts a sub-coding signal from the digital signal output from the RF amplifier circuit 2 and supplies the sub-coding signal to the system control circuit 6. As a result, the system control circuit 6 operates according to the reproduction control data (emphasis on / off, etc.) contained in the sub-coding signal and reproduces based on the position index information contained in the sub-coding signal. The time and the like are displayed on the display 7.

On the other hand, the Q channel data of the sub-coding signal extracted by the digital signal processing circuit 4 is
It is supplied to the error detection circuit 12. The error detection circuit 12 checks the CRC included in the Q channel data each time the Q channel data is supplied, detects whether the Q channel data has an error, and detects the error within a certain period. It is detected whether the Q channel data itself can be detected. The error detection circuit 12 detects the error in the Q channel data by a predetermined number of times set in advance or Q
It is determined that the digital signal read from the disc has an error by detecting the absence of the channel data.

When it is determined that the digital signal read by the error detection circuit 12 has no error, the system control circuit 6 for monitoring the memory control circuit 10 makes the second signal.
It is detected whether the audio data stored in the memory circuit 9 is equal to or more than a first predetermined amount. The audio data stored in the second memory circuit 9 is the first
If the audio data is newly written in the second memory circuit 9, the trace position by the pickup 1 is advanced as it is, and new audio data is continuously written in the second memory circuit 9. Get caught.

The audio data stored in the second memory circuit 9 has a first predetermined amount or more,
When the audio data cannot be newly written in the second memory circuit 9, the trace position by the pickup 1 becomes a state in which the same signal track is repeatedly traced and the audio data is written in the second memory circuit 9. Is interrupted. In such a state, when the read operation of the audio data stored in the second memory circuit 9 is performed and the amount becomes smaller than the first predetermined amount, the write operation can be performed.

By the way, when the error detection circuit 12 detects that the read digital signal has an error, the audio data stored in the second memory circuit 9 by the system control circuit 6 is next detected by the second predetermined amount. It is determined whether or not the following. When it is determined that the audio data stored in the second memory circuit 9 is equal to or less than the second predetermined amount, even if there is an error in the read digital signal, the trace position by the pickup 1 is advanced as it is, The audio data is continuously written in the second memory circuit 9. Therefore, the audio data read from the second memory circuit 9 is not interrupted.

On the other hand, when it is determined that the read digital signal has an error, it is determined that the audio data stored in the second memory circuit 9 is larger than the second predetermined amount, the Q channel data having an error. The writing of the audio data in the digital signal including the signal to the second memory circuit 9 is stopped, and the control operation of the servo signal processing circuit 3 by the system control circuit 6 is performed to return the trace position by the pickup 1 to the rear. Therefore,
The portion of the digital signal containing the erroneous Q channel data will be reread.

As described above, the second memory circuit 9 of this embodiment
The operation of writing and reading signals to and from
Next, the operation in a specific situation will be described.

When the pickup 1 correctly reads the signal recorded on the disc and the error detection circuit 12 determines that the read digital signal has no error, the correct audio data is the second audio data. It is written in the memory circuit 9. Since the signal writing speed to the second memory circuit 9 is set to be higher than the reading speed of the stored signal, the audio data stored in the second memory circuit 9 gradually increases. . However, when the audio data stored in the second memory circuit 9 becomes equal to or more than the first predetermined amount, the trace position of the pickup 1 is retracted and the trace of the same portion on the disk is repeatedly performed, and the signal of that portion is repeated. Since the writing operation of the audio data corresponding to the second memory circuit 9 is not performed,
The memory circuit 9 never overflows. Even when the same portion on the disc is repeatedly traced by the pickup 1, the audio data is continuously read from the second memory circuit 9, so that the audio data is not interrupted. However, the signal reproducing operation is continuously performed.

On the other hand, when the pickup 1 does not correctly read the signal on the disc due to an impact or swing received from the outside, and the error detection circuit 12 determines that the read digital signal has an error, the second memory circuit If the audio data stored in 9 is larger than the second predetermined amount, the trace position on the disc of the pickup 1 is retracted and the digital signal determined to be erroneous is read again. Then, the audio data in the reread digital signal is written so as to be correctly continuous with the audio data stored in the second memory circuit 9.
In such a case, the digital signal determined to be erroneous is read again, and while the audio data in the digital signal is written in the second memory circuit 9, the audio data read from the second memory circuit 9 may exist. The second
The storage capacity of audio data in the memory circuit 9 is controlled. Therefore, the audio data stored in the second memory circuit 9 is read again after the audio data stored in the second memory circuit 9 is read, so that the audio data is not interrupted and the signal reproduction operation is continuously performed. .

As described above, the writing operation and the reading operation of the digital signal to the second memory circuit 9 are performed,
Next, the operation of writing and reading the signal to and from the buffer memory circuit 13 is corrected. When the reproduction speed varying operation means 16 is not operated, the speed at which the audio data is read from the buffer memory circuit 13 is set to be standard according to the sampling frequency of the signal recorded on the disc. Then, the signal read operation from the second memory circuit 9 is performed so that the amount of the signal stored in the buffer memory circuit 13 becomes equal to or more than a predetermined amount. The buffer memory circuit 13
The audio data, which is a parallel digital signal read from, is input to the parallel / serial conversion circuit 14 and converted into serial audio data. The serial audio data output from the parallel / serial conversion circuit 14 is applied to the D / A converter 15 to be converted into an analog signal and separated into left and right channel signals and output. Therefore, a signal such as music recorded on the disc can be reproduced and heard at a standard speed.

The reproduction / listening operation is performed at the standard speed as described above. Next, the operation when the reproduction speed is varied will be described. When the user operates the reproduction speed varying operation means 16 in the reproduction operation state described above, the cycle of the read clock pulse supplied from the system control circuit 6 to the buffer memory circuit 13 is changed according to the reproduction speed. . Therefore, the speed of the reproduction signal converted into the serial signal by the parallel / serial conversion circuit 14 and then converted into the analog signal by the D / A converter 15 can be increased or decreased with respect to the standard speed. When the reproduction operation is performed, the second
The control operation of the read speed of the signal stored in the memory circuit 9 is performed so that the capacity of the audio data stored in the buffer memory circuit 13 becomes equal to or more than a predetermined amount. The signal reproducing operation can be continuously performed. The variable range of the reproduction speed by the reproduction speed changing operation means 16 is such that the signal can be read from the disc, that is, in the case of the present embodiment, the reproduction speed can be changed up to twice the standard speed and the reproduction speed can be changed. The operation can be performed continuously.

In this embodiment, the error of the digital signal read from the disc is detected by the Q channel data of the sub-coding signal. However, the digital signal processing circuit 4 corrects the audio data or the corrected audio data. It is also possible to detect an error in the read digital signal by using this detection output, since it is detected whether it is the audio data obtained by interpolation.

[0032]

According to the reproducing speed varying circuit of the present invention, the reproducing speed changing operation is performed by changing the reading speed from the buffer memory circuit for storing the audio data without changing the rotating speed of the disk. Therefore, not only the response characteristic at the time of changing the speed is excellent, but also the variable range of the reproduction speed can be widened.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of a reproduction speed variable circuit of the present invention.

[Explanation of symbols]

 1 pickup 3 servo signal processing circuit 4 digital signal processing circuit 5 first memory circuit 6 system control circuit 9 second memory circuit 10 memory control circuit 11 comparison circuit 12 error detection circuit 13 buffer memory circuit 14 parallel / serial conversion circuit 15 D / A converter 16 Reproduction speed changing operation means

Claims (1)

(57) [Claims] 1. A disc configured to write a digital signal read from a disc in which information data is stored by a digital signal into a memory circuit and to read the signal written in the memory circuit to perform a reproducing operation. In the reproducing device, a reading unit that reads a digital signal from the disk at a speed higher than a reading speed of the digital signal stored in the memory circuit, a signal writing operation to the memory circuit, and a reading operation from the memory circuit are performed. A memory control circuit for controlling, a buffer memory circuit in which a digital signal read from the memory circuit is written and the reading speed is variable, and a capacity of the digital signal in the memory circuit detected by the memory control circuit Operation of the reading means according to And a system control circuit for controlling the reading speed from the buffer memory circuit, and when the memory control circuit detects that the capacity of the digital signal in the memory circuit has reached a predetermined amount, The reading position on the disk by the reading means is returned to the rear, the writing operation of the digital signal to the memory circuit is temporarily stopped, and the reading operation of the digital signal written in the buffer memory circuit from the memory circuit is performed. A reproducing speed varying circuit of a disk reproducing device, wherein the capacity of a signal stored in the buffer memory circuit is set to be a predetermined amount or more.