JP3981054B2 - Image signal and audio signal recording method and image signal and audio signal recording / reproducing apparatus - Google Patents

Description

  The present invention relates to an image signal and audio signal recording method for recording a video signal, an audio signal, and an auxiliary signal accompanying the video signal and the audio signal, and an image signal and audio signal recording / reproducing apparatus for recording and reproducing the signal.

  VCR which encodes a video signal and an audio signal, records and reproduces is implemented. Examples of this include a component type D1 and a composite type D2 in a business VCR. In addition, an image compression method has been researched and developed as a consumer digital VCR.

In the case of recording digital data, it has been proposed to record data such as subcodes as a pack having a predetermined data amount. In that case, a header indicating the contents of the pack data is added.

A code having a predetermined bit length is used as the header, but only a type corresponding to the bit length can be identified by the header. Therefore, there is a problem that the types of packs cannot be increased.

  Accordingly, an object of the present invention is to provide an image signal and audio signal recording method and an image signal and audio signal recording / reproducing apparatus capable of increasing the types of packs.

In order to solve the above-described problems, the present invention is provided with an auxiliary data area in which auxiliary data associated with an image and sound is recorded, in addition to an area in which an image signal is recorded and an area in which an audio signal is recorded. In the auxiliary data area, the auxiliary data is packed and recorded in a fixed-length pack in an image signal and audio signal recording method,
The pack has a structure in which a header having a predetermined bit length is added to the auxiliary data,
The header is divided into a first header having an n-bit length and a second header having an m-bit length, and the first header defines upper types of up to 2 ⁿ packs,
It kind of up to 2 ^m pieces of the upper by a second header for each type of higher-level
Each sub- type is defined, and the first and second headers define up to 2 ⁿ × 2 ^m pack types ,
The area after the recording of a specific type of pack defined by the first and second headers is reserved as a manufacturer's optional area. For the specific type of pack, the manufacturer identification code and the specific type of pack The video signal and audio signal recording method is characterized in that a code indicating the total number of auxiliary data packs whose data contents are defined for each manufacturer is recorded .

Further, according to the present invention, in addition to the area where the image signal is recorded and the area where the audio signal is recorded, an auxiliary data area where auxiliary data associated with the image and sound is recorded is provided. In an image signal and audio signal recording / reproducing apparatus adapted to record the auxiliary data in a long pack,
The pack has a structure in which a header having a predetermined bit length is added to the auxiliary data,
The header is divided into a first header having an n-bit length and a second header having an m-bit length, and the first header defines upper types of up to 2 ⁿ packs,
It kind of up to 2 ^m pieces of the upper by a second header for each type of higher-level
Each sub- type is defined, and the first and second headers define up to 2 ⁿ × 2 ^m pack types ,
The area after the recording of a specific type of pack defined by the first and second headers is reserved as a manufacturer's optional area. For the specific type of pack, the manufacturer identification code and the specific type of pack An image signal and audio signal recording / reproducing apparatus in which a code indicating the total number of packs of auxiliary data whose data content is defined for each manufacturer is recorded .

A pack structure is used to record the auxiliary data, and the pack header PC0 is divided into upper bits and lower bits. A pack type is defined by a combination of upper bits and a combination of lower bits, and a number of pack types can be defined. A manufacturer code pack is defined as one type of pack, and a manufacturer identification code is recorded as the PC1. From PC2 of the manufacturer code pack in up to two low-order bit of the PC3, it records the TDP that shows the total number of pack, you open up to PC4 from the lower third bit of the PC3.

  According to the present invention, the number of types of packs can be increased by hierarchizing, so packs suitable for each application can be freely defined.

Hereinafter, a preferred embodiment of the present invention will be described with reference to the drawings. For the sake of clarity, (A) an outline of a digital VCR to which the present invention is applied (B) a track format, application ID and pack structure (C) a hierarchical structure of option packs (D) a digital VCR The recording / reproducing circuit will be described in this order.

(A) Outline of digital VCR to which the present invention is applied In a digital VCR that compresses and records / reproduces a digital video signal, the composite digital color video signal is separated into a luminance signal Y and color difference signals RY and BY. Then, it is compressed by a high-efficiency compression method using DCT conversion, variable-length coding, and high-efficiency coding, and recorded on a magnetic tape by a rotary head. As the recording method, the SD method (525 lines / 60 Hz, 625 lines / 50 Hz) and the HD method (1125 lines / 60 Hz, 1250 lines / 50 Hz) can be set. In the case of the SD method, the number of tracks per frame Is 10 tracks (in the case of 525 lines / 60 Hz) or 12 tracks (in the case of 525 lines / 60 Hz), in the case of the HD system, the number of tracks per frame is double that of the SD system, that is, 20 tracks (1125 lines / 60 Hz) or 24 tracks (1250 lines / 50 Hz).

(B) Track format, application ID and pack structure In such a digital VCR, the applicant of the present application is a system for making data management easy and making the digital VCR usable as a versatile recording / reproducing apparatus. The system which becomes application ID previously is proposed. With this system, it is easy to manage cassettes with memory, including video spare data VAUX (Video Auxiliary data), audio spare data AAUX (Audio Auxiliary data) and subcodes, and memory called MIC (Memory In Cassette) It becomes. In the present invention, audio data after-recording, video data insertion, and data superimposed on the V blanking period (broadcast station operation signal, medical signal, etc.) are recorded using the pack.

  First, the application ID system will be described. In a digital VCR tape to which the present invention is applied, diagonal tracks are formed on the tape as shown in FIG. 1A. The number of tracks per frame is 10 and 12 tracks for the SD system, and 20 and 24 tracks for the HD system.

  FIG. 1B shows one track of a tape used in a digital VCR. On the track entrance side, there is a timing block for reliably performing post-recording called ITI (Insert and Track Information). This is provided in order to accurately position the area when the data written in the subsequent area is rewritten after dubbing.

  In any digital signal recording / playback application apparatus, since rewriting of data in a specific area is indispensable, the ITI area on the track entrance side always exists. That is, many sync blocks having a short sync length are written in the ITI area, and the sync numbers are assigned in order from the track entrance side. If any sync block in this ITI area can be detected when trying to post-record, the current position on the track can be accurately determined from the number written there. Based on that, the after-recording area is determined. Generally, the track entrance side is unstable because it is difficult to hit the head due to mechanical accuracy and the like. Therefore, the detection probability is increased by shortening the sync length and writing a large number of sync blocks.

  As shown in FIG. 2, the ITI area is composed of four parts: a preamble, an SSA, a TIA, and a postamble. The 1400-bit preamble functions as a PLL run-in for digital signal reproduction. SSA (Start Sync block Area) is used for this function, and is composed of 30 bits per block and 61 blocks. Behind that is a TIA (Track Information Area). This consists of three blocks of 90 bits. The TIA is an area for storing information relating to the entire track. In this area, the original application ID of APT (Application ID of a Track) is 3 bits, the SP / LP is 1 bit indicating the track pitch, and the reserve is 1 bit. In addition, a total of 6 bits of PF (Pilot Frame) 1 bit indicating the reference frame of the servo system are stored. Finally, there are 280 bits of postamble for earning a margin.

  In the above-described apparatus, the applicant of the present invention first mounts a circuit board provided with a memory IC on a cassette in which a recording medium is stored, and when the cassette is mounted on the apparatus, the data written in the memory IC is stored. Has been proposed to assist recording and reproduction (Japanese Patent Application No. 4-165444, Japanese Patent Application No. 4-287875). In the present application, this is called MIC.

  The MIC can store TOC (Table Of Contents) information, index information, character information, reproduction control information, timer recording information, etc., as well as information on the tape itself such as tape length, tape thickness, and tape type. . When a cassette tape having an MIC is connected to a digital VCR, for example, data stored in the MIC is read out, skipped to a predetermined program, set the playback order of the program, and designates a scene of the predetermined program. It is possible to play back a still image (photo) or record it with a timer reservation.

The application ID is stored in the upper 3 bits of address 0 as an APM (Application ID of MIC) in this MIC as well as the above-described AIA in the TIA area. The definition of application ID is
The application ID prescribes the data structure.
In short, the application ID is not an ID that determines the application example, but merely determines the data structure of the area. Therefore, the following meaning is given.
APT ... Determines the data structure on the track.
APM: Determines the data structure of the MIC.
The data structure on the track is defined by the value of APT.

That is, the track after the ITI area is divided into several areas as shown in FIG. 3, and the data structure such as the position on these tracks, the sync block configuration, and the ECC configuration for protecting data from errors is uniquely defined. Determined. Further, each area has an application ID that determines the data structure of the area. The meaning is as follows.
Application ID of area n... Determines the data structure of area n.

  The application ID has a hierarchical structure as shown in FIG. That is, the area on the track is defined by APT which is the original application ID, and AP1 to APn are further defined in each area. The number of areas is defined by APT. Although FIG. 4 shows two levels, a level may be further formed as needed. The APM which is the application ID in the MIC is only one layer. The same value as the APT of the device is written by the digital VCR.

  By the way, with this application ID system, a digital VCR for home use can be diverted as it is with its cassette, mechanism, servo system, ITI area generation detection circuit, etc., to completely different product groups such as data streamers and multi-track digitals. It is also possible to make something like an audio tape recorder. In addition, even if one area is determined, the contents can be further defined by the application ID of the area. Therefore, when an application ID is a value, it is video data, and when it is another value, video / audio data, or computer data. Thus, it becomes possible to perform a very wide range of data settings.

Next, FIG. 5A shows a state when APT = 000. As shown in this figure, area 1, area 2, and area 3 are defined on the track. The position on the track, the sync block configuration, the ECC configuration for protecting data from errors, the gap for guaranteeing each area, and the overwrite margin for guaranteeing overwriting are determined. Further, each area has an application ID that determines the data structure of the area. The meaning is as follows.
AP1... The data structure of area 1 is determined.
AP2... The data structure of area 2 is determined.
AP3... The data structure of area 3 is determined.

When the application ID of each area is 000, it is defined as follows.
AP1 = 000 ··· CVCR audio, AAUX data structure AP2 = 000 · · · CVCR video, VAUX data structure AP3 = 000 · · · CVCR subcode, ID data structure where CVCR: Home digital image signal and audio signal recording / reproducing apparatus AAUX: audio preliminary data VAUX: video preliminary data. That is, when realizing a home digital VCR, as shown in FIG.
APT, AP1, AP2, AP3 = 000
It becomes. Naturally, APM also takes a value of 000.

  When APT = 000, the AAUX, VAUX, subcode, and MIC areas are all described in a common pack structure. As shown in FIG. 6, one pack is composed of 5 bytes, the first 1 byte is a header, and the remaining 4 bytes are data. A pack is a minimum unit of a data group, and related data is collected to form one pack.

  The header 8 bits are divided into upper 4 bits and lower 4 bits to form a hierarchical structure. As shown in FIG. 7, the upper 4 bits are the upper header, the lower 4 bits are the lower header, and the hierarchy is further divided into two layers by data bit assignment. This hierarchization makes it clear that the pack contents are organized and can be easily expanded. The 256 spaces by the upper header and the lower header are prepared together with the contents of each pack as a pack header table (see FIG. 8). Using this, each area described above is described. The pack structure is based on a fixed length of 5 bytes, but the variable length pack structure is used only when character data is described in the MIC as an exception. This is to make effective use of a limited buffer memory.

  Each area of audio and video is called an audio sector and a video sector, respectively. FIG. 9 shows the structure of the audio sector. Note that the audio sector includes a preamble, a data portion, and a postamble. The preamble is composed of 500 bits, and includes a run-up 400 bits and two presync blocks. Run-up is used as a run-up pattern for PLL pull-in, and pre-sync is used as pre-detection of an audio sync block. The data part consists of 10500 bits. The rear postamble is composed of 550 bits, and consists of one postsync block and a guard area of 500 bits. The post sync is for confirming the end of the audio sector by the sync number of the ID, and the guard area is for guarding the audio sector so as not to bite into the video sector behind it after the dubbing.

Each block of presync and postsync is composed of 6 bytes as shown in FIGS. 10A and 10B. In the sixth byte of the presync, there is an SP / LP discrimination byte. FFh represents SP and 00h represents LP. The sixth byte of the post sync stores FFh as dummy data. The SP / LP identification byte also exists in the TIA area as an SP / LP flag, but this is for protection. If the value of the TIA area can be read, that value is adopted. If the value cannot be read, the value of this area is adopted. Each 6 bytes of pre-sync and post-sync are recorded after being subjected to 24-25 conversion (modulation method in which 24-bit data is converted into 25 bits and recorded), so the total bit length is
Presync 6 × 2 × 8 × 25 ÷ 24 = 100 bits Postsync 6 × 1 × 8 × 25 ÷ 24 = 50 bits.

As shown in FIG. 11, the audio sync block is composed of 90 bytes as one sync block. The first 5 bytes have the same configuration as presync and postsync. The data portion is 77 bytes and is protected by horizontal parity C1 (8 bytes) and vertical parity C2 (5 sync blocks). The audio sync block consists of 14 sync blocks per track, and is recorded after being subjected to 24-25 conversion, so the total bit length is
90 × 14 × 8 × 25 ÷ 24 = 10500 bits. The first 5 bytes of the data part are for AAUX, which constitutes 1 pack, and 9 packs are prepared per track. The numbers from 0 to 8 in FIG. 11 represent the pack numbers in the track.

  FIG. 12 is a diagram in which 9 packs are extracted and described in the track direction. One video frame is composed of 10 tracks in the case of a 525 line / 60 Hz system and 12 tracks in the case of a 625 line / 50 Hz system. Audio and subcode are also recorded and reproduced according to this one video frame. In FIG. 12, numerals 50 to 55 indicate pack header values (hexadecimal). As can be seen from FIG. 12, the same pack is written 10 times on 10 tracks. This portion is called a main area. Here, essential items such as a sampling frequency and a quantization bit number necessary for reproducing an audio signal are mainly stored. It is written many times for data protection. As a result, the data in the main area can be reproduced even when a horizontal flaw or a single channel clog or the like, which tends to occur in the tape transport, occurs.

  All other remaining packs are connected in order and used as an optional area. In FIG. 12, as shown by a, b, c, d, e, f, g, h,... In one video frame, 30 packs (525 lines / 60 Hz) or 36 packs (625 lines / 50 Hz) are prepared as an optional area. Since this area is literally an option, a pack may be freely selected and described for each digital VCR from the pack header table of FIG.

  The optional area includes a common common option (for example, character data) and a manufacturer's option with no commonality that allows each manufacturer to determine its contents independently. Because it is optional, only one or both may or may not be present. When there is no information, it is described using a pack without information (NO INFO pack). The application ID and both areas are delimited by the appearance of the manufacturer code pack. After this pack is the manufacturer's optional area. If a manufacturer code pack is recorded, it is secured as a manufacturer's optional area until the end of one video frame thereafter. The mechanisms of the main area, optional area, common optional area, and manufacturer's optional area are all common to AAUX, VAUX, subcode, and MIC. Furthermore, the content written in the optional area is arbitrary, but the error correction capability is low with respect to the subcode, so the number of times the same pack is written is defined.

FIG. 13 shows the configuration of the video sector. The structure of the preamble and the postamble is the same as that of the audio sector shown in FIG. However, the number of bits in the guard area of the postamble is larger than that in the audio sector. As shown in FIG. 14, the video sync block is composed of the same 90 bytes as audio and one sync block. The first 5 bytes have the same configuration as pre-sync, post-sync, and audio sync. The data portion is 77 bytes and is protected by horizontal parity C1 (8 bytes) and vertical parity C2 (11 sync blocks) as shown in FIG. The upper two sync blocks in FIG. 15 and the one sync block immediately before the C2 parity are dedicated to VAUX, and 77-byte data is used as VAUX data. Except for the VAUX dedicated sync and the C2 sync, video data of a video signal compressed using DCT (discrete cosine transform) is stored. The video sync block consists of 149 sync blocks per track, and is recorded after being subjected to 24-25 conversion, so the total bit length is
90 × 149 × 8 × 25 ÷ 24 = 111750 bits.

  FIG. 16 shows the state of the VAUX dedicated sink. The upper two syncs in FIG. 16 correspond to the upper two syncs in FIG. 15, and the lowermost sink in FIG. 16 corresponds to the one sync immediately before C1 in FIG. If 77 bytes are engraved in a pack unit of 5 bytes, 2 bytes remain, but this is not particularly used as a reserve. If numbers are assigned in the same way as audio, 45 packs are secured from 0 to 44 per track.

  FIG. 17 shows the 45 packs extracted and described in the track direction. In FIG. 17, numerals from 60 to 65 indicate pack header values (hexadecimal). This is the main area. Like audio, I write the same pack 10 times on 10 tracks. Here, essential items such as a television system and a screen aspect ratio necessary for reproducing a video signal are mainly stored. As a result, the data in the main area can be reproduced even in the case of lateral scratches, single channel clogs, and the like that tend to occur in the tape transport. All other remaining packs are connected in order and used as an optional area. As in the case of audio in FIG. 17, the main area packs are pulled out and connected in the direction of the arrows as a, b, c,. In one video frame, an optional area of 390 packs (525 lines / 60 Hz) or 468 packs (625 lines / 50 Hz) is prepared. The handling of the optional area is the same as that of audio.

  In FIG. 15, the middle 135 sync block is a video signal storage area. In the figure, BUF0 to BUF26 each indicate one buffering block. One buffering block is composed of 5 sync blocks, and there are 27 blocks per track. One video frame and 10 tracks have 270 buffering blocks. In other words, an area effective as an image is extracted from one frame of image data, and digital data obtained by sampling the area is shuffled from various parts of the actual image to form 270 groups. One group is one buffering unit. For each unit, data compression is attempted using a compression technique such as a DCT method, and processing is performed while evaluating whether or not it is within the target compression value as a whole. Thereafter, the compressed data of one buffering unit is packed into one buffering block and five syncs.

  Next, the ID part will be described. IDP is used in the same manner in audio, video, and subcode sectors, and is used as a parity for protecting ID0 and ID1. FIG. 18 shows the contents of the ID part. IDP is omitted.

  In FIG. 18A, ID1 is a place for storing the in-track sync number. In this case, numbers from 0 to 168 are consecutively written in binary notation from the pre-sync of the audio sector to the post-sync of the video sector. In the lower 4 bits of ID0, the track number in one video frame is entered. Number one in two tracks. The distinction between the two can be determined by the azimuth angle of the head. The contents of the upper 4 bits of ID0 vary depending on the location of the sync. In the AAUX + audio sync and the video data sync shown in FIG. 18B, a sequence number of 4 bits is input. In this method, 12 numbers from 0000 to 1011 are assigned to each video frame. Thereby, it is possible to distinguish whether the data obtained at the time of variable speed reproduction is in the same frame.

  In the pre-sync, post-sync, and C2 parity sync shown in FIGS. 9, 11, 13 and 15, the application IDs AP1 and AP2 are stored in the upper 3 bits of ID0. Therefore, AP1 is written 8 times and AP2 is written 14 times. In this way, the application ID is reliable and protected by writing many times and distributing the locations.

  FIG. 19 is a configuration diagram of a subcode sector. Unlike the audio sector and video sector, the subcode sector preamble and postamble have no presync and postsync. The length is longer than other sectors. This is because the subcode sector is used for frequently rewriting such as index driving, and because the subcode sector is at the end of the track, the deviation in the first half of the track is added and the wrinkles are reduced. The subcode sync block has no more than 12 bytes as shown in FIG. The first 5 bytes have the same configuration as pre-sync, post-sync, audio sync, and video sync. The subsequent 5 bytes are a data part, and a pack is formed only by this.

The horizontal parity C1 has only 2 bytes, and this protects the data part. Further, a so-called product code configuration using C1 and C2 is not used as in audio and video. This is because the subcode is mainly for high-speed search, and neither C2 parity can be picked up within the limited envelope. Also, the sync length is shortened to 12 bytes for high-speed search up to about 200 times. The subcode sync block has 12 sync blocks per track, and is subjected to 24-25 conversion before recording, so the total bit length is
12 × 12 × 8 × 25 ÷ 24 = 1200 bits.

  21A and 21B show the ID part of the subcode. In the subcode sector, the contents of the data portion are different between the first half 5 tracks (525 lines / 60 Hz), 6 tracks (625 lines / 50 Hz), and the latter half. There is an F / R flag in the MSB of ID0 for distinguishing between the first half and the second half during variable speed reproduction and high speed search. The lower 3 bits contain the application ID and AP3 in sync numbers 0 and 6. In addition to sync numbers 0 and 6, an index ID, a skip ID, and a PP ID (photo ID, picture ID) are stored in order from the top. The index ID is used for a conventional index search, and the skip ID is an ID for cutting an unnecessary scene such as a commercial cut. The PP ID is for still image search. It is the absolute track number that straddles ID0 and ID1. In this method, absolute numbers are entered in order from the beginning of the tape, and the MIC performs a TOC search and the like based on this. The lower 4 bits of ID1 are an in-track sync number.

  FIG. 22 shows the data portion of the subcode. The uppercase alphabet represents the main area, and the lowercase alphabet represents the optional area. Since there is one pack in one sync block of the subcode, there are a total of 12 packs from 0 to 11 in one track. The same characters indicate the same pack contents. You can see that the contents are different between the first half and the second half.

  The main area stores information necessary for high-speed search such as time code and recording date. Since it is possible to search in pack units, it is called pack search. The optional area cannot be used by connecting it all like AAUX and VAUX. This is because, as described above, since the protection of parity is weak, the contents are moved up and down for each track, and the same data is written many times in the first and second half tracks for protection. Accordingly, the first half and the second half can be used as an optional area for 6 packs. This is the same for both the 525 line / 60 Hz system and the 625 line / 50 Hz system.

  FIG. 23 shows the data structure of the MIC. The MIC is also divided into a main area and an optional area, and everything is described in a pack structure except for the first byte and the unused area (FFh). As described above, only character data is stored in a variable-length pack structure, and other data is stored in a pack structure with a fixed length of 5 bytes, which is the same as VAUX, AAUX, and subcode.

  At the top address 0 of the MIC main area, there are an MIC application ID, APM 3 bits, and BCID (Basic Cassette ID) 4 bits. BCID is a basic cassette ID and has the same contents as an ID board for ID recognition (tape thickness, tape type, tape grade) in a cassette without MIC. The ID board allows the MIC reading terminal to perform the same function as a conventional 8 mm VCR recognition hole, thereby eliminating the need to make a hole in the cassette half as in the prior art. From address 1 onward, three packs of cassette ID, tape length, and title end are inserted in order. The cassette ID pack has more specific values of tape thickness and memory information about the MIC.

  The tape length pack is a tape manufacturer that stores the tape length of the cassette in the number of tracks. From this and the next title end pack (recorded with the final recording position information and absolute track number), the remaining amount of tape can be read at once. Can be calculated. Further, this recording final position information provides a convenient usability when the camcorder is played back halfway and stopped, and then when returning to the original final recording position or timer reservation.

  The optional area is composed of optional events. The main area is a 16-byte fixed area from addresses 0 to 15, whereas the optional area is a variable-length area after address 16. The length of the area changes depending on the contents, and when the event is erased, the remaining events are packed in the direction of address 16 and stored. All data that becomes unnecessary after the stuffing operation is written as FFh in the unused area. The optional area is literally an option, and mainly stores tag information indicating points on the TOC and tape, and character information such as a title related to a program. When the MIC is read, the next pack header appears for every 5 bytes or variable length bytes (character data) depending on the contents of the pack header. When the FFh in the unused area is read as a header, this is a NO INFO pack. The control microcomputer can detect that there is no information after that.

(C) Hierarchical structure of option packs FIG. 24 is an extract of the pack header table shown in FIG. 8, and is a pack header related to the present invention. FIG. 24 shows a pack group of upper bits = “1111”. When “11110000” is specified, the manufacturer code pack is specified, when “11110001” to “11111110” is specified, the option pack is specified, and when “11111111” is specified, the NO INFO pack is specified.

  FIG. 25 is a diagram showing a manufacturer code pack. When the header is “11110000”, it is defined as a manufacturer code pack. PC1 records a manufacturer code as a manufacturer identification code, and uses the 8 bits of PC2 and the lower 2 bits of PC3 to record the total number of packs (TDP) that follows. Also, it is opened from the lower third bit of PC3 to PC4. This open area is used as a manufacturer's option. That is, in this area, data contents can be defined for each manufacturer.

  The manufacturer's optional area in the VAUX area can record 39 packs per track when all the optional areas are used, and when recording high-definition television signals, it can record up to 24 tracks per frame, so 39 x 24 = 936 packs Can be recorded. Therefore, the total number of packs (TDP) requires 10 bits in binary. Up to this TDP is a common optional area.

  FIG. 26 is a flowchart of the reproduction process relating to the pack when the above-described TDP is used. In step 501, it is determined whether or not the read code is a manufacturer code pack. In the case of a manufacturer code pack, the TDP in the pack is read (step 502). Thereafter, a memory area having a capacity corresponding to the number of packs specified by TDP is secured, and all data in the memory area is set to FFh (step 503). After the option pack is read in step 504, if there is no error in the data to be written, it is written in the reserved memory area (step 505). In step 506, it is determined whether data writing for one pack has been completed. If not, the process returns to step 505. On the other hand, when the data writing for one pack is completed, it is determined in step 507 whether or not the data of all the manufacturer's option packs have been read. If not, the process returns to step 504. Note that the total number of packs TDP recorded in the manufacturer code pack is used for the determination in step 507. On the other hand, if all the manufacturer's option packs have been read, the process proceeds to step 508.

  In step 508, it is determined whether or not reading of data for one video frame is completed. If completed, the series of processing is terminated. On the other hand, if it is not determined that the reading of data for one video frame is completed, the process proceeds to step 509.

  In step 509, the next pack is read. In step 510, it is determined whether pack header = FFh (NO INFO pack) or an error. If pack header is not equal to FFh or an error, the process returns to step 505. Thereby, data is written many times. On the other hand, if the pack header = FFh or an error, the storage area pointer is advanced by 5 bytes (1 pack) (step 511), and the processing from step 508 is repeated. Thus, since the number of required option packs can be specified by TDP, the read data can be recorded effectively.

  FIG. 27 is a diagram of a maker code pack when the option pack has a hierarchical structure. The same data as the manufacturer code pack shown in FIG. 26 is stored from the MSB of PC1 and PC2 to the lower 2 bits of PC3. A first category code is written in the remaining bits of PC3, and a second category code is written in PC4. The first category code is defined as a layer one level lower than the manufacturer code, and the second category code is defined as a level one level lower than the first category code.

  FIG. 28 is a diagram illustrating the hierarchical structure described in FIG. As can be seen from FIG. 28, option packs with headers F1h to FEh are arranged below the category code.

  FIG. 29 is a diagram illustrating an example of the hierarchical structure of FIG. In this case, the company name (A Co., Ltd.) is shown as the manufacturer code, the application name (consumer video, computer use, business use) is shown as the first category code, and the first category code is shown as the second category code. Subdivision of categories (consumer video-digital VCR, TV video integrated type, computer-data streamer, commercial-aircraft VCR) is defined, and this hierarchical structure improves usability. .

  The optional area is composed of optional events. By setting the main area to have such a hierarchical structure, it is possible to define in accordance with each application example in a spatially finite option pack. For this reason, the manufacturer's option pack can be increased, and the application can be freely expanded.

(D) Digital VCR Recording / Reproducing Circuit FIGS. 30 to 35 are block diagrams of a digital VCR recording system to which the present invention is applied. In this digital VCR, a composite color video signal is separated into a digital luminance signal Y and color difference signals RY and BY, and is compressed and recorded by a high-efficiency encoding method using DCT conversion and a variable length code. The data for the V blanking period is recorded using the MIC described above.

  In FIG. 30, a television signal is received by the antenna 1. A signal received by the antenna 1 is supplied to the tuner 2. The tuner 2 demodulates a composite color video signal and an audio signal of the NTSC system or PAL system from the television signal. The composite video signal from the tuner 2 is supplied to the switch 3a, and the audio signal is supplied to the switch 3b.

  Further, an analog composite video color video signal is supplied to the external video input terminal 4. The composite video signal from the external video input terminal 4 is supplied to the switch 3a. An analog audio signal is supplied to the external audio input terminal 5. This analog audio signal is supplied to the switch 3b.

  The composite video signal from the tuner unit 2 and the composite video signal from the external video input terminal 4 are selected by the switch 3a. The output of the switch 3a is supplied to the Y / C separation circuit 6 and also to the synchronization separation circuit 11. The Y / C separation circuit 6 separates the luminance signal (Y) and the color difference signals (RY, BY) from the composite video signal.

  The luminance signal (Y) and the color difference signals (R−Y, B−Y) from the Y / C separation circuit 6 are supplied to the A / D converters 8a, 8b, and 8c via the low-pass filters 7a, 7b, and 7c. The The low-pass filters 7a, 7b and 7c limit the band of the input signal in order to remove aliasing distortion. The cutoff frequencies of the low-pass filters 7a, 7b, and 7c are, for example, 5.75 MHz for a luminance signal (Y, sampling frequency 13.5 MHz (4 rate)), and for a color difference signal (RY, BY). Are set to 2.75 MHz at a sampling frequency of 6.75 MHz (2 rate) and 1.45 MHz at a sampling frequency of 3.375 MHz (1 rate).

  The sync separation circuit 11 extracts a vertical sync signal (V sync) and a horizontal sync signal (H sync). The vertical synchronization signal (V sync) and the horizontal synchronization signal (H sync) from the synchronization separation circuit 11 are supplied to a PLL (Phase Locked Loop) circuit 12. This PLL circuit 12 forms a clock with a basic sampling frequency of 13.5 MHz locked to the input video signal. This 13.5 MHz sampling frequency is referred to as a rate of 4 as described above. The clock having the basic sampling frequency of 13.5 MHz is supplied to the A / D converter 8a. The clock having the basic sampling frequency of 13.5 MHz is supplied to the frequency divider 13, and the frequency divider 13 forms a clock having a frequency that is ¼ of the basic sampling frequency. A clock having a frequency of 1/4 of this basic sampling frequency (rate of 1) is supplied to the A / D converters 8b and 8c.

  The digital component video signals Y, RY, BY from the A / D converters 8a, 8b, 8c are supplied to the blocking circuit 9. The blocking circuit 9 processes the data on the real screen so as to be a block of 8 samples × 8 lines. The output of the blocking circuit 9 is supplied to the shuffling circuit 10 and shuffled. The shuffling is performed in order to avoid intensive loss of data recorded on the tape due to head clogging or tape scratches. At the same time, the shuffling circuit 10 performs rearrangement so that the luminance signal and the color difference signal can be easily processed later.

  The output of the shuffling circuit 10 is supplied to the data compression encoding unit 14. The data compression / encoding unit 14 includes a compression circuit using a DCT method or variable length coding, an estimator for estimating whether or not the result can be compressed to a predetermined amount of data, and a quantum that is finally quantized based on the determination result. It consists of a generator. The compressed video data is packed in a predetermined sync block according to a predetermined rule by the framing circuit 15. The output of the framing circuit 15 is supplied to the synthesis circuit 16.

  On the other hand, an audio signal from the tuner 2 and an audio signal from the external audio signal input terminal 5 are selected by the switch 3b. The output of the switch 3b is supplied to the A / D converter 21. The analog audio signal is digitized by the A / D converter 21. The digital audio signal obtained in this way is supplied to the shuffling circuit 22. The digital audio data is shuffled by the shuffling circuit 22. The output of the shuffling circuit 22 is supplied to the framing circuit 23. The audio data is packed into the audio sync block by the framing circuit 23. The output of the framing circuit 23 is supplied to the synthesis circuit 24.

  The mode processing microcomputer 34 is a microcomputer having a man-machine interface, and operates in synchronization with a field frequency 60 Hz or 50 Hz of a television image. Since the signal processing microcomputer 20 is operated on the side closer to the machine, for example, the signal processing microcomputer 20 operates in synchronization with the drum rotation speeds of 9000 rpm and 150 Hz.

  The mode processing microcomputer 34 generates pack data of video preliminary data VAUX, audio preliminary data AAUX, and subcode, and the absolute track number included in the “title end” pack or the like is generated by the signal processing microcomputer 20. The TTC (time title code) stored in the subcode is also generated by the signal processing microcomputer 20.

  The preliminary video data VAUX generated by the signal processing microcomputer 20 is supplied to the synthesis circuit 16 via the VAUX circuit 17. In the synthesis circuit 16, the video preliminary data VAUX is synthesized with the output of the framing circuit 15. The audio preliminary data AAUX generated by the signal processing microcomputer 20 is supplied to the synthesis circuit 24 via the AAUX circuit 19. The audio preliminary data AAUX is synthesized with the output of the framing circuit 23 by the synthesis circuit 24. VDATA (video data) that is the output of the synthesis circuit 16 and ADATA (audio data) that is the output of 24 are supplied to the switch 26.

  Based on the output of the signal processing microcomputer 20, the subcode circuit 18 generates data SID and AP3 of the ID part and subcode pack data SDATA, and these are supplied to the switch 26. Also, the sync generation circuit 25 generates AV (audio / video) ID sections, presync and postsync, and supplies them to the switch 26. Further, AP1 and AP2 are generated by the circuit 25, and these are fitted into a predetermined ID portion. The switch 26 switches the output of the circuit 25 and ADATA, VDATA, SID, and SDATA at a predetermined timing.

  The output of the switch circuit 26 is supplied to the error correction code generation circuit 27. The error correction code generation circuit 27 adds a predetermined parity. The output of the error correction code generation circuit 27 is supplied to the random number conversion circuit 29. The random number circuit 29 randomizes the recorded data so that there is no bias. The output of the random number circuit 29 is supplied to the 24/25 conversion circuit 30, and 24-bit data is converted into 25 bits. As a result, the direct current component, which is a problem during magnetic recording and reproduction, is removed. Here, although not shown, PRIV (partial response, class 4) coding processing (1 / 1-D2) suitable for digital recording is also performed.

  The output of the 24/25 conversion circuit 30 is supplied to the synthesis circuit 31. The synthesizing circuit 31 synthesizes an audio / video sync pattern and a subcode sync pattern with the output of the 24/25 conversion circuit 30. The output of the synthesis circuit 31 is supplied to the switch 32.

  The APT, SP / LP, and PF data are output from the mode processing microcomputer 34 that manages the mode of the entire VCR, and these data are supplied to the ITI circuit 33. From the ITI circuit 33, ITI sector data is generated. The switch 32 outputs the data and the amble pattern by switching the timing.

  The data switched by the switch 32 is further switched by the switch 35 in accordance with the head switching timing. The output of the switch 35 is amplified by the head amplifiers 36a and 36b and supplied to the heads 37a and 37b.

  The switch 40 is an external switch of the VCR main body, and is a switch group that instructs recording, reproduction, and the like. Among them, there is a switch for setting the SP / LP recording mode, and the result is instructed to the mechanical control microcomputer 28 and the signal processing microcomputer 20. An MIC microcomputer 38 is connected to the mode processing microcomputer 34. The MIC microcomputer 38 generates APM and pack data in the MIC. This data is supplied to the cassette 41 with MIC via the MIC contact 39.

  As described above, in the digital VCR to which the present invention is applied, the digital luminance signal (Y) and the color difference signals (RY, BY) are compressed and recorded in the video sector, and the digital audio signal is recorded in the audio sector. Is done. In addition, VAUX and AAUX are recorded. VAUX data and AAUX data are recorded in a pack structure.

  FIG. 31 is a detailed block diagram of the recording side circuit regarding VAUX data. In the pack data generation unit 51 of the mode processing microcomputer 34, pack data to be stored in the VAUX area is generated and converted into serial data by the P / S conversion circuit 52. This data is supplied to the S / P conversion circuit 53 of the signal processing microcomputer 20 in accordance with the communication protocol between the microcomputers. After being converted into parallel data by the S / P conversion circuit 53, it is stored in the buffer 55 via the switch 54. Each pack header is detected by the pack header 56 from the pack data output from the S / P conversion circuit 53. Further, it is determined whether the pack is a pack that requires an absolute track number. If necessary, the switch 54 is switched so that the 23-bit data is output from the absolute track number generation circuit 57 every 8 bits and stored in the buffer 55. The storage areas are all fixed positions of PC1, PC2, and PC3. The S / P conversion circuit 53 is a serial I / O in the microcomputer, the pack header detection circuit 56, the absolute track number generation circuit 57 and the switch 54 are microcomputer programs, and the buffer 55 is a RAM in the microcomputer. The Since the processing of the pack structure is in time for the processing time of the microcomputer, a microcomputer that is advantageous in terms of cost is used in this way.

  The data stored in the buffer 55 is sequentially read by the timing signal of the write side timing controller 58 of the VAUX circuit 17. At this time, the first six packs are supplied to the FIFO 60 as main area data, and the subsequent 390 packs are supplied to the FIFO 61 as optional area data. Note that data is supplied to the FIFO 60 and the FIFO 61 by switching the switch 59.

  Incidentally, the VAUX data is stored in the in-track sync numbers 19, 20 and 156 as shown in FIG. 32A. When the track number in the frame is 0, 2, 4, 6, and 8, -azimuth is the main area in the second half of the sync number 156, and when the track number is 1, 3, 5, 7, and 9, + azimuth is the sync number 19 There is a main area in the first half. This is shown in one video frame in FIG. 32B. As can be seen from FIG. 32B, this area is the main area when nMAIN = “L”. Such a signal is generated by the read side timing controller 62 and supplied to the switch 63. As a result, the data of the FIFO 60 or the FIFO 61 is supplied to the synthesis circuit 16 via the switch 63.

  Here, when nNAIN = “L”, the data in the main area FIFO 60 is repeatedly read 10 times (525 lines / 60 Hz) or 12 times (625 lines / 50 Hz). When nMAIN = “H”, the data in the optional area FIFO 61 is read once every video frame.

  FIG. 33 is a block diagram of a VAUX pack data generation circuit in the mode processing microcomputer 34. The VAUX pack data generation circuit is divided into a main area and an optional area. The main area data collection and generation circuit 71 receives a signal such as a closed caption. Based on these data, the main area data collection and generation circuit 71 generates a data group such as a television channel, a source code, a tuner category, a copy source, and a copy generation. This data group is assembled into a bit byte structure of the main pack, and a pack header is added by the switch 72. Thereafter, the data is converted into serial data by the P / S conversion circuit 74 via the switch 73 and supplied to the signal processing microcomputer 20.

  On the other hand, teletext data, program titles, and the like are input from the tuner to the optional area data collection and generation circuit 75. The VCR set determines which pack is recorded in the optional area. The pack header is set by the pack header setting circuit 76, and the pack header is added to the data when the switch 77 is switched. Thereafter, the data is converted into serial data by the P / S conversion circuit 74 via the switch 73 and then supplied to the signal processing microcomputer 20. The P / S conversion circuit 74 is a serial I / O in the microcomputer, and the other circuits are microcomputer programs.

  FIG. 34 is a block diagram of an AAUX pack data generation circuit in the mode processing microcomputer 34. The operation of each circuit is almost the same as that of the VAUX pack data generation circuit shown in FIG. In this case, however, the program title input from the tuner may be a title of a music program such as a digital audio PCM broadcast in addition to the title of the television program. Some tuners have a predetermined sampling frequency, quantization bit number, etc., as in so-called A-mode and B-mode digital audio. Further, when an AAUX closed caption pack (55h) is configured, the closed caption signal in the vertical blanking is obtained from the tuner, and the audio information is extracted from the decoder audio information extraction circuit 81. This is packed in the AAUX source pack (50h) and source control pack (51h), respectively.

  FIG. 35 is a detailed circuit block diagram of the MIC processing microcomputer 38. The serial data supplied from the mode processing microcomputer 34 is converted into parallel data by the S / P conversion circuit 91. By the way, in the main area shown in FIG. 23, the VCR side rewrites the APM at address 0, the ME flag in the cassette ID pack, and the title end pack. Among these, the RE (Recording proofed events Exist) flag and the ME (MIC Error) flag are generated in the MIC microcomputer 38, and others are supplied from the mode processing microcomputer 34. Among the outputs of the S / P conversion circuit 91, the absolute track number, APM, SL flag, and BF flag are supplied to the main area data collection and generation circuit 92, and a predetermined data group is generated. This data group is supplied to one end of the fixed terminal of the switch 97 via the switch 94. The switch 94 supplies the pack header 1Fh, and is turned on only at the time of title end writing.

  On the other hand, among the output data of the S / P conversion circuit 91, data such as recording date, recording time / minute / second, and program title are supplied to the optional area data collection / generation circuit 93. The above-described data is for a timer recording reservation event, for example. In the pack header setting circuit 95, a data pack header used in the optional area data collection and generation circuit 93 is set. The pack header and data are supplied to the other end of the fixed terminal of the switch 97 via the switch 96. The data selected by the switch 97 is converted into a predetermined format by the IIC bus interface circuit 98 and supplied to the MIC contact 39. The switching timing of each switch is adjusted by a timing adjustment circuit 99.

  By the way, in the case of MIC, it can be considered to be used in a simple MIC writing device or the like. In this case, the S / P conversion circuit 91 is removed from the circuit shown in FIG.

  Next, the configuration of the reproduction side of the digital VCR to which the present invention is applied will be described with reference to FIGS. In FIG. 36, signals obtained from the heads 101 a and 101 b are amplified by the head amplifiers 102 a and 102 b and switched by the switch 103. The output of the switch 103 is supplied to the equalizer circuit 104. In order to improve the electromagnetic conversion characteristics between the tape and the magnetic head during recording, so-called emphasis processing (for example, partial response, class 4) is performed, but the equalizer circuit 104 performs the reverse processing.

  The output of the equalizer circuit 104 is supplied to the A / D converter 106 and also supplied to the clock extraction circuit 105. The clock component is extracted by the clock extraction circuit 105. With this extracted clock, the output of the equalizer circuit 104 is digitized using the A / D converter 106. The 1-bit data thus obtained is written into the FIFO 107.

  The output of the FIFO 107 is supplied to the sync pattern detection circuit 108. A sync pattern for each area is supplied to the sync pattern detection circuit 108 via the switch 109. The switch 109 is switched by the output of the timing circuit 113. The sync pattern detection circuit 108 has a so-called flywheel configuration, and once a sync pattern is detected, it is checked whether the same sync pattern comes again after a predetermined sync block length. For example, if it is correct three times or more, it is regarded as true so as to prevent erroneous detection.

  When the sync pattern is detected in this way, the shift amount is determined which part is extracted from the output of each stage of the FIFO 107 and one sync block can be extracted. Therefore, based on this, necessary bits are taken into the sync block determination latch 111 by the switch 110. Thus, the fetched sync number is taken out by the extraction circuit 112 and inputted to the timing circuit 113. Since the read sync number indicates where the head is on the track, the switch 109 and the switch 114 are switched accordingly.

  The switch 114 is switched to the lower side in the ITI sector, and the ITI sync pattern is separated by the separation circuit 115 and supplied to the ITI decoder 116. Since the ITI area is coded and recorded, APT, SP / LP, and PF data can be extracted by decoding the ITI area. This is given to the mode processing microcomputer 117 which determines the operation mode and the like of the entire set connected to the operation key 118 outside the set.

  The mode processing microcomputer 117 is connected to an MIC microcomputer 119 that manages APM and the like. Information from the cassette 121 with the MIC is given to the microcomputer 119 with the MIC via the MIC contact 120, and processes the MIC while sharing the role with the mode processing microcomputer 117. Depending on the set, the MIC microcomputer may be omitted, and the mode processing microcomputer 117 may perform MIC processing. The mode processing microcomputer 117 performs system control of the entire set in cooperation with the mechanical control microcomputer 128 and the signal processing microcomputer 151.

  In the case of the A / V sector or the subcode sector, the switch 114 is switched to the upper side. After the sync pattern of each sector is extracted by the separation circuit 122, it is further supplied to the reverse random number conversion circuit 124 through the 24/25 reverse conversion circuit 123, and returned to the original data string. The data thus extracted is supplied to the error correction circuit 125.

  The error correction circuit 125 detects and corrects error data. Uncorrectable data is output with an error flag. Each data is switched by the switch 126.

  The circuit 127 is in charge of the ID section of the A / V sector and the syncs of the presync and postsync. Here, the SP / LP stored in the sync number, track number and presync and postsync syncs. Each signal is extracted. These are given to the timing circuit 113 to create various timings.

  Further, AP1 and AP2 are extracted by the circuit 127, supplied to the mode processing microcomputer 117, and the format is checked. When AP1 and AP2 = 000, area 2 is defined as an image data area and is normally operated. In other cases, a warning operation such as warning processing is performed.

  As for SP / LP, the mode processing microcomputer 117 performs a comparative study with that obtained from ITI. In the ITI area, SP / LP information is written three times in the TIA area in the ITI area, and the reliability is improved by the majority decision process or the like. There are two pre-syncs for audio and video, and a total of four SP / LP information is written. Here, too, a majority vote is taken and reliability is improved. In the event that the two do not eventually match, the ITI area is preferentially adopted.

  Playback data from the video sector is divided into video data and VAUX data by the switch 129 in FIG. The video data is supplied to the deframing circuit 130 together with an error flag. In the deframing circuit 130, framing inverse conversion is performed.

  The image data is supplied to a data inverse compression encoding unit including an inverse quantization circuit 131 and an inverse compression circuit 132, and is returned to data before compression. Next, the data is returned to the original image space arrangement by the deshuffling circuit 133 and the deblocking circuit 134.

  After the deshuffling, the process is performed by dividing into three systems of luminance signal (Y) and color difference signal (RY, BY). Then, it is returned to an analog signal by the D / A converters 135a, 135b and 135c. At this time, the output divided by the oscillation circuit 139 and the frequency divider 140 is used. That is, the luminance signal (Y) is 13.5 MHz and the color difference signals RY and BY are 6.75 MHz or 3.375 MHz.

  The signal thus obtained is synthesized by the Y / C synthesis circuit 136 and further synthesized by the synthesis signal output from the synchronization signal generation circuit 141 and the synthesis circuit 137.

  Playback data from the audio sector is divided into audio data and AAUX data by the switch 143. The audio data is returned to the original time axis by the next deshuffling circuit 145. At this time, if necessary, audio data interpolation processing is performed based on the error flag. This signal is supplied to the D / A converter 146, converted back to an analog audio signal, and then output from the analog audio output terminal 152 through the switch 147 while taking timing such as video data and lip sync.

  The VAUX and AAUX data separated by the switches 129 and 143 are supplied to the VAUX circuit 148 and the AAUX circuit 150, and preprocessing such as majority processing at the time of multiple writing is performed while referring to an error flag. The ID part and data part of the subcode sector are supplied to the subcode circuit 149. Again, preprocessing such as majority processing is performed with reference to the error flag. Thereafter, it is supplied to the signal processing microcomputer 151 and a final reading operation is performed. At this time, errors that could not be removed are given to the signal processing microcomputer 151 as VAUXER, SUBER, and AAUXER, respectively. Here, AP3 is extracted by the subcode circuit 149. AP3 is supplied to the mode processing microcomputer 117 via the signal processing microcomputer 151. The mode processing microcomputer 117 checks the format. When AP3 = 000, area 3 is defined as a subcode area and normal processing is performed. On the other hand, when AP3 ≠ 000, a warning process such as a warning process is performed.

  To supplement the error processing here, the signal processing microcomputer 151 further performs propagation error processing, data repair processing, and the like by analogy with the context of each data pack. The data result thus determined is supplied to the mode processing microcomputer 117. This data result is used as a factor in determining the movement of the entire set.

  FIG. 38 is a detailed circuit block diagram of the VAUX circuit 148. Note that the pre-processing is not a majority decision process, and will be described by a method in which data is not written to the memory when an error occurs. The VAUX data input via the switch 129 is divided into main area data and optional area data by the switch 161 by a write timing pulse (see FIG. 32) output from the write-side controller 162. The pack header detection circuit 163 detects the pack header of the pack data in the main area. The output of the pack header detection circuit 163 is applied to the switch 164. Thereby, the switch 164 is switched. Only when there is no error, data is written into the main area memory 165. The memory 165 has a 9-bit configuration, and a halftone dot is used as an error flag storage bit.

  As an initial setting of the main area memory, the contents are all set to 1 (no information) for each video frame. And no processing is performed in case of an error. On the other hand, when there is no error, the data is written and 0 is written in the error flag. Since the same pack is written 10 times or 12 times in the main area, the place where the error flag is set to 1 at the end of one video frame is finally recognized as an error.

  By the way, since the optional area is basically written only once, the error flag is written in the FIFO 166 for the optional area together with the data. The FIFO 166 has a capacity for a manufacturer's option. If no error flag is supplied to the FIFO 166, data is written. By switching the switches 168 and 169 with the read side timing controller 167, the data stored in the memory 165 and the data stored in the FIFO 166 are supplied to the signal processing microcomputer 151. Although the VAUX circuit for VAUX data has been described here, the AAUX circuit including the FIFO for AAUX data has the same configuration and operation.

  FIG. 39 is a detailed circuit block diagram of the signal processing microcomputer 151. The signal processing microcomputer 151 performs analysis based on the pack data and the error flag supplied from the VAUX circuit 148. That is, the pack data VAUXDT output from the VAUX circuit 148 is supplied to the pack header identification circuit 171, and the pack data is distributed and supplied to the switch 172. On the other hand, the error data VAUXER is supplied to the read / write circuit 177. The switch 172 is controlled by the output control signal of the read / write circuit 177. The pack data passed through the switch 172 is written into the memory 173. Here, there is no distinction between main area data and optional area data.

  When the data is pack data in the main area, like the VAUX circuit 148, no writing process is performed during VAUXER. As a result, the repair can be performed with a value at least one video frame before. Since the content of the main area is considered to have a very strong correlation with the value one video frame before, there is no problem even if this processing is performed. On the other hand, in the case of pack data in the optional area, since it is considered that there is no correlation with the value one video frame before, error propagation processing is performed for each pack.

  This method is basically performed by changing to “no information pack” in which all data is FFh if there is an error in the pack data having a fixed length of 5 bytes, but it is also necessary to deal with each pack individually. For example, in the case of a teletext pack, since the pack continues many times, even if there is an error in the pack header in the meantime, the teletext pack header can be easily replaced. Even if there is an error in the data part, the pack is not changed to “pack without information”. This is because the restoration of the teletext data is left to the parity check of the teletext decoder. Therefore, even if an error is determined, the data is left as it is.

  It is assumed that there is no error flag in the data processed as described above. The pack data stored in the memory 173 is read to the P / S conversion circuit 174 and converted into serial data. Thereafter, the signal is supplied to the S / P conversion circuit 175 of the mode processing microcomputer 117 according to the communication protocol between the microcomputers. The parallel data output from the S / P conversion circuit 175 is supplied to the pack data decomposition analysis circuit 176 and analyzed. Note that the processing in the pack data decomposition analysis circuit 176 is performed in the reverse order to the VAUX pack data generation processing shown in FIG.

The P / S conversion circuit 174 and the S / P conversion circuit 175 are serial I / Os in the microcomputer, the pack header identification circuit 171, the switch 172 and the read / write circuit 177 are microcomputer software, and the memory 173 is a memory inside the microcomputer. Each is composed. Further, the processing on the reproduction side of the MIC microcomputer 119 is performed in the reverse order to the MIC data generation processing shown in FIG.
As described above, in one embodiment of the present invention, the total number of packs (TDP) following is recorded in the manufacturer code pack. The effect of recording the total number of packs (TDP) will be described with reference to FIGS. As described above, in the VAUX, AAUX, subcode, and MIC optional areas, when the manufacturer code pack (F0h) is read, the subsequent areas are defined as the manufacturers optional area. The manufacturer's optional area is an area where each manufacturer freely defines the data content of the pack and records the pack. As shown in FIG. 40, the contents of the manufacturer code pack are prepared as F0h as a pack header in PC0 and 8 bits as a manufacturer identification code in PC1, and the rest are opened.
When data is recorded on a recording medium (for example, a cassette tape), there is a risk that the data may not be restored due to a horizontal flaw, a clog, etc. during tape reproduction. For this reason, a process of writing and protecting the same data many times is usually performed. However, in the configuration as shown in FIG. 40, it is impossible to determine unless the actual recorded manufacturer's option data continues until it is read. Also, as shown in FIG. 41, when the data is written many times, if there is an error in the maker code pack in the middle, it will not be possible to know how far it is, and eventually the effect of the many times writing will fade. End up.
That is, in FIG. 41A, when 18 packs are recorded, if an error occurs in F2, it becomes impossible to determine whether the total number is 17 packs or 18 packs. Further, as shown in FIG. 41B, when the same data is written twice, if the first pack F0 of the second data becomes an error, the length of the first data can be determined. Even if all the second data can be read correctly, all the read data must be invalidated.
In one embodiment of the present invention, since the total number of packs (TDP) following the manufacturer code pack is recorded, it is possible to avoid the occurrence of such a problem.

It is a figure which shows the track format of a tape. It is a figure which shows the track format of a tape. It is a figure which shows the track format of a tape. It is a figure which shows the hierarchical structure of application ID. It is a figure which shows the track format of a tape. It is a figure which shows the structure of a pack. It is a figure which shows the hierarchical structure of a header. It is a figure which shows a pack header table | surface. It is a figure which shows the track format of a tape. It is a figure which shows the structure of a presync and a postsync. It is a figure which shows the track format of a tape. It is a figure which shows the track format of a tape. It is a figure which shows the track format of a tape. It is a figure which shows the track format of a tape. It is a figure which shows the track format of a tape. It is a figure which shows the track format of a tape. It is a figure which shows the track format of a tape. It is a figure which shows the detail of ID part. It is a figure which shows the track format of a tape. It is a figure which shows the track format of a tape. It is a figure which shows the detail of ID part. It is a figure which shows the track format of a tape. It is a figure which shows the data structure of MIC. It is the figure which extracted the pack header table | surface. It is a figure which shows a manufacturer code pack. It is a flowchart of the reproduction | regeneration processing regarding the pack at the time of using TDP. It is a figure of a maker code pack in case an optional pack is made into a hierarchical structure. It is a figure which shows a hierarchical structure. It is a figure which shows an example of a hierarchical structure. It is a block diagram of a recording system of a digital VCR. It is a block diagram of the recording system regarding VAUX data. It is a figure which shows the relationship between a main area, an optional area, and a sync number. It is a block diagram of a VAUX pack data generation circuit. It is a block diagram of an AAUX pack data generation circuit. It is a block diagram of a MIC processing microcomputer. It is a block diagram of the reproduction system of a digital VCR. It is a block diagram of the reproduction system of a digital VCR. It is a block diagram of a VAUX circuit. It is a block diagram of a signal processing microcomputer. It is a figure which shows a manufacturer code pack. It is a figure which shows the example of a recording of a manufacturer code pack.

Explanation of symbols

148 VAUX circuit 163 Pack header detection circuit 165 Memory 166 FIFO

Claims (2)

In addition to the area where the image signal is recorded and the area where the audio signal is recorded, an auxiliary data area where auxiliary data associated with the image and sound is recorded is provided. In the auxiliary data area, the auxiliary data area is provided in a fixed-length pack. In an image signal and audio signal recording method in which data is packed and recorded,
The pack has a configuration in which a header having a predetermined bit length is added to the auxiliary data.
The header is divided into a first header having an n-bit length and a second header having an m-bit length, and the first header defines the upper types of a maximum of 2 ⁿ packs,
Maximum 2 ^m pieces of the upper with respect to each type of upper Symbol higher by the second header
Sub-types of each type are defined, and the first and second headers define up to 2 ⁿ × 2 ^m types of packs ,
The area after the recording of the specific type of pack defined by the first and second headers is secured as a manufacturer's optional area, and the manufacturer identification code and the specific type for the specific type of pack are recorded. And a code indicating the total number of packs of auxiliary data whose data content is defined for each manufacturer, following the pack of the video signal and the audio signal recording method. In addition to the area where the image signal is recorded and the area where the audio signal is recorded, an auxiliary data area where auxiliary data associated with the image and sound is recorded is provided. In the auxiliary data area, the auxiliary data area is provided in a fixed-length pack. In an image signal and audio signal recording / playback apparatus in which data is packed and recorded,
The pack has a configuration in which a header having a predetermined bit length is added to the auxiliary data.
The header is divided into a first header having an n-bit length and a second header having an m-bit length, and the first header defines the upper types of a maximum of 2 ⁿ packs,
Up to 2 ^m of the above higher ranks by the second header for each of the higher rank types
Sub-types of each type are defined, and the first and second headers define up to 2 ⁿ × 2 ^m types of packs ,
The area after the recording of the specific type of pack defined by the first and second headers is secured as a manufacturer's optional area, and the manufacturer identification code and the specific type for the specific type of pack are recorded. An image signal and audio signal recording / reproducing apparatus in which a code indicating the total number of auxiliary data packs whose data contents are defined for each manufacturer is recorded after the pack .

Images