JP3520539B2 - Digital signal recording / reproducing method and apparatus - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal recording / reproducing method for recording / reproducing by encoding a digital signal or an analog signal.

[0002]

2. Description of the Related Art Various apparatuses for encoding and recording image signals and audio signals for recording and reproducing have been implemented. In such a device, a servo system or system controller required when recording and reproducing image signals and audio signals by encoding,
There is provided a device for recording / reproducing computer data other than image signals and audio signals by sharing the mechanism. An example of such a device is a DAT format audio signal recording / reproducing device.

That is, in this DAT device, 2 bits × 2 for each synchronization period in the main data area.
An ID area of area (4 bits) is provided. Then, among these IDs, a 2-bit format ID indicating which format is used for recording is provided. As a result, the DAT device distinguishes between the DAT audio format and the DDS (data streamer using DAT).

By the way, in such a DAT device,
So-called sub-code areas are provided at both ends of each track. The data associated with the signal is also recorded / reproduced in these sub-code areas. However, the above-mentioned format ID is not recorded in these subcode areas.

That is, in this DAT device, with the format ID in the ID area of the main data area,
It is decided whether the data to be recorded is voice or computer data. At this time, the sub-data area is simply associated with the main data area and cannot be independent of the main area.

On the other hand, for the coming digital world, the necessity of a digital platform that can be commonly used for various digital data is being discussed. DAT, DDS
Is part of that. However, in the format of the format ID of the conventional DAT device as described above, the type of data that can be recorded is limited to one type.

Also, the format ID itself has only 2 bits, and since two of them are already used, there are only two remaining. This limits the development potential for the future. This application is made in view of such a point.

[0008]

A problem to be solved is how to effectively record and reproduce various miscellaneous data in a recordable area on a recording medium.

[0009]

According to a first aspect of the present invention, there is provided a track on a recording medium in which a predetermined amount of a signal obtained by encoding one or more digital signals or analog signals is recorded.
One or a plurality of signal a digital signal recording and reproducing method for recording and reproducing a recording area, et al provided a track of
A first identification signal for selecting the number of signal recording areas to be recorded,
Data length and sync block length for each signal recording area
Set the second identification signal to be selected and set it in the signal recording area.
Tracking one of the signal recording areas when recording a signal
A synchronization area for determining the reference position of the recording signal
Provisions Te, and adding a first identification signal in synchronization area Then DOO
The second identification signal is added to each signal recording area, and the first
And a digital signal recording and reproducing method characterized by the structure of the track and the signal recording area Te on the second identification code has to be defined.

The second means according to the present invention is the first means.
In the digital signal recording / reproducing method described in
A memory means to which it belongs is provided and the identification within this memory means
The third identification code is added to the place of
The digital signal recording / reproducing method is characterized in that a structure of a signal provided in the memory means is defined.

The third means according to the present invention is one or more.
A signal that encodes a number of digital or analog signals
One or more of the tracks on the recording medium for each predetermined amount
Digital signal recording for recording and playback as the signal recording area
The signal recording provided on the track in the reproducing apparatus
Means for generating a first identification signal for selecting the number of areas
And the data length and synchronization block for each signal recording area
Means for generating a second identification signal for selecting the length,
When recording a signal in the signal recording area
One to determine the reference position of the recording signal in the track
It is defined as the synchronization area of the
Signal and add a second identification signal for each signal recording area.
No. is added, and the track and
A digital feature characterized by defining the structure of the signal recording area.
It is a digital signal recording / reproducing device. The fourth aspect of the present invention
Means, the third means digital signal recording and reproducing apparatus <br/> Oite according, memory hand stage is provided that comes into record medium, a third identification code to a particular location in the memory means Addition
And a digital signal recording and reproducing apparatus characterized by the structure of the signal <br/> provided in the memory means has to be defined Te to the third identification code.

[0012]

According to this, with the identification code added to the area for determining the reference position of the recording signal in the track,
The data structure of the entire recorded / reproduced track is defined. The individual identification code added to each signal area defines the data structure of each signal area. This allows products that record and reproduce completely different data over the entire track to coexist with the same mechanism and the same servo system. Furthermore, it is possible to record and reproduce completely different data for each signal area. Therefore, a digital platform machine in the true sense can be realized, and various miscellaneous data can be collected and processed in one machine.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A recording side circuit of a concrete VTR in which the present invention is implemented is shown in FIG. 1, and a reproducing side circuit is shown in FIGS. This example is a so-called baseband recording / reproducing VTR, and in addition to the current 4: 3 aspect ratio television system of NTSC and PAL, a similar block is used in a 16: 9 aspect ratio television system such as high-definition television broadcasting. Illustrated in the figure.

First, the recording side circuit of FIG. 1 will be described. The TV radio signal input from the antenna 1 is received by the tuner 2 and is restored to a composite video signal and audio signal. This composite video signal is selected by the signal from the external input 4 and the switch 3a and added to the Y / C separation circuit 6. In this circuit, it is decomposed into a luminance signal (Y) and a color difference signal (RY, BY). On the other hand, the signal from the switch 3a is also given to the sync separation circuit 11. Here, the V sync signal and the H sync signal are extracted.

Both of these are the following PLL (Phase L
It is used as a reference signal of an ocked loop circuit, and here, the original basic sampling frequency of 13.5 MHz locked to the input signal is generated.
This frequency is called a rate of 4, but since the color signal does not usually require the amount of information to be sampled by this, a frequency divider of 13 makes half or a quarter of this frequency, Sampling with this is sufficient. In this embodiment, 525 lines / 60 Hz NTSC is 4: 1: 1, and 625 lines / 50 Hz PAL is 4: 2 :.
Sample at a rate of 0.

Before converting the analog output of the Y / C separation circuit 6 into a digital signal, LPFs (Low Pass) 7a, 7b and 7c are provided to remove aliasing distortion.
Filter) to limit the bandwidth. The cutoff frequency of the filter is, for example, 5.75 MHz for Y, RY,
For BY, 2.75 MHz at a rate of 2 and 1.45 MHz at a rate of 1 are selected. The signal thus preprocessed is converted into a digital signal by the A / D converters 8a, 8b and 8c.

Next, these digital signals are converted to DCT (De
In order to perform the block compression encoding using the screen cosine transform, the data on the real screen is processed into blocks of 8 samples × 8 lines by a blocking circuit of 9. Then, the shuffling circuit of 10 effectively disperses the data. This is a measure for avoiding intensive loss of data recorded on the tape due to head clogs or lateral scratches on the tape. At the same time, in 10, rearrangement is performed so that the luminance signal and the color difference signal can be easily processed in the subsequent stage.

The data compression coding unit 14 uses a compression circuit using the DCT method or variable length coding, an estimator for estimating whether the result can be compressed up to a predetermined data amount, and finally a quantum based on the judgment result. It consists of a quantizer for The video data thus compressed is packed in a predetermined SYNC block according to the rule of 15 framing circuits.

The pack data of VAUX, AAUX, and Subcode and the track number to be stored in Subcode are generated by the signal processing microcomputer 20. The result is given to the interface ICs 17, 18, and 19 which are provided between the microcomputer and the hardware. VAUX
The IC 17 in charge of is also generating AP2, and synthesizes it with the framing output in the synthesizer 16 at a proper timing. Similarly, the IC 18 in charge of the subcode generates the data SID of the ID part, the AP 3, and the pack data SDATA of the subcode.

On the other hand, the audio signal is converted into a digital signal by the A / D converter 21 after selecting the output signal from the tuner 2 or the signal from the external input 5 by the switch 3b. At this time, as with the video, an LPF (not shown) corresponding to the sampling frequency is required in the preceding stage. The audio data thus obtained is separated by a shuffling circuit 22 into a form advantageous for recording on the tape. The framing circuit 23 at the next stage packs it into the audio SYNC block. At this time AAU
The X charge IC 19 generates the pack data of AP1 and AAUX, measures the timing, and packs them in a predetermined place in the SYNC block of the audio by the synthesizing circuit 24.

In the circuit 25, the AV (Audio / Vid)
Each ID part of eo) and each SYNC of Pre and Post are generated. This, ADATA, VDATA, SID,
The SDATA is switched by observing the timing by the switch 26, and a predetermined parity is added by the error correction code generation circuit 27.

In the next-stage channel coder, first, a random number is generated at 29 so that the recorded data is not distorted, and the 24/25 converter 30 converts the 24-bit data into 25-bit data based on a certain promise. To do. As a result, the direct current component which becomes a problem during magnetic recording / reproduction is removed.
Although not shown here, a PRI suitable for digital recording
V (partial response, class 4) coding processing (1 / 1-D ² ) is also performed.

The signal thus obtained is added to the Audio / V
The synthesizer 31 synthesizes the SYNC patterns of video and subcode. The IC 33 is an ITI sector generation IC. Here, from 33 mode processing microcomputers that manage the mode of the entire VTR, APT, SP / L
Each data of P and PF is given, and it is fitted into a predetermined position and added to the switch 32. The switch 32 switches these data and amble patterns by observing the timing.

The switch 40 is a switch group for instructing recording, reproduction, etc. by an external switch of the VTR main body. There is also an SP / LP recording mode setting switch, and the result is the mechanical control microcomputer 2 via the microcomputer communication network.
8 or the signal processing microcomputer 20. An MIC microcomputer 38 is connected to the mode processing microcomputer 34. Here, pack data in the APM or MIC is generated and given to the MIC cassette 40 via the MIC contact 39.

The data switched by the switch 32 is further switched by the switch 35 in accordance with the head switching timing. And head amplifier 3
Amplified by 6a and 36b, and recorded on the tape by heads 37a and 37b. The series of operations described above are performed mainly by the mode processing microcomputer 34 in cooperation with the mechanical control microcomputer 28 or the signal processing microcomputer 20 and the ICs in charge of each part.

Next, the reproducing side circuit shown in FIGS. 2 and 3 will be described. The weak signals input from the heads 1a and 1b are amplified by the head amplifiers 2a and 2b, and the switch 3
Is added to the equalizer circuit 4 while being timed and switched. The equalizer circuit performs so-called emphasis processing (for example, partial response class IV) in order to improve the electromagnetic conversion characteristics between the tape and the magnetic head during recording, but performs the reverse processing. A clock extraction circuit 5 extracts a clock component from the output of the equalizer circuit 4. Using this, the output of the equalizer circuit 4 is digitized using an A / D converter of 6. The 1-bit data thus obtained is written in the FIFO 7 by using the extraction clock CK.

This clock CK is a temporally fluffy and unstable signal containing a jitter component of the rotary head drum. However, since the data itself before A / D conversion is fluffy, there is no problem in sampling itself. However, when extracting image data or the like from this point, the data cannot be extracted unless the data is stable in terms of time, so the time axis is adjusted using the FIFO. That is, writing is performed with an unstable clock, but reading is performed with a stable clock SCK from a self-excited oscillator 39 using a crystal oscillator 38 or the like. The FIFO depth should be large enough so that it will not be read faster than the input speed of the input data.

The output of each stage of the FIFO is 8 SYNCs.
It is added to the pattern detection circuit. Switch 9 here
The SYNC pattern of each area is changed to the timing circuit 1
It is switched by 3 and given. The SYNC pattern detection circuit has a so-called flywheel configuration. Once a SYNC pattern is detected, a predetermined SYNC pattern is detected.
See if the same SYNC pattern comes again after the NC block length. For example, if it is correct three times or more, it is regarded as true to prevent erroneous detection. FIFO
The depth of this should be a few minutes.

When the SYNC pattern is detected in this way, the shift amount is determined which part of the output of each stage of the FIFO should be extracted to extract one SYNC block. The bit is taken into the 11 SYNC block confirmation latch. As a result, the fetched SYNC number is fetched by the extraction circuit 12 and input to the timing circuit 13. The position of the head on the track can be known from the read SYNC number, and the switch 9 or the switch 14 is switched accordingly.

The switch 14 is switched to the lower side at the time of the ITI sector, and the ITISYNC pattern is removed by 15 and added to the ITI decoder of 16.
Since the ITI area is coded and recorded,
By decoding it, APT, SP / LP,
Each data of PF can be taken out. This is given to the mode processing microcomputer 17 which is connected to the operation key 18 outside the set and determines the operation mode of the entire set.

The mode processing microcomputer 17 is connected to the MIC microcomputer 19 that manages the APM and the like. MIC
Information from the attached cassette 21 is the MIC contact switch 2
It is given to the MIC microcomputer 19 via 0, and performs the processing of the MIC while sharing the role with the mode processing microcomputer 17. Depending on the set, the MIC microcomputer may be omitted and the mode processing microcomputer 17 may perform the MIC processing. The mode processing microcomputer 17 is the mechanical control microcomputer 2
8 and the signal processing microcomputer 51 in cooperation with each other to perform system control of the entire set.

In the A / V sector or the Subcode sector, the switch 14 is switched to the upper side. Two
After the SYNC pattern of each sector is extracted by 2, it is passed through the 24/25 inverse conversion circuit 23, further added to the inverse random number conversion circuit 24, and returned to the original data string. The data thus fetched is added to the error correction circuit 25.

In the error correction circuit, various strategies are used to detect and correct error data, but data that cannot be completely removed is output with an ERROR flag. Each data is switched by the switch 26. The circuit 27 includes an ID section of the A / V sector and Pr.
It is in charge of each SYNC of e and Post, where S
The YNC number, the track number, and the SP / LP signals stored in Pre-SYNC are extracted. These generate various timings given to the timing circuit 13.

Regarding SP / LP, the mode microcomputer 17 carries out a comparative examination with that obtained from ITI. I
In the TI area, SP / L 3 times in the TIA area
The P information is written, and only there is taken a majority vote to improve reliability. Pre-SYNC has 2 SYNC for audio and 2 SYNC for video respectively, total 4 SP / LP
Information is written. Here too, there is a majority vote to improve reliability. Finally, if they do not match, the ITI area is preferentially adopted.

VDATA is set to Vid by the switch 29.
It is divided into eo data and VAUX data. Vid
The eo data is given to the deframing circuit 30 together with the ERROR flag. The deframing circuit performs the inverse conversion of the framing, and grasps the property of the data packed in it. Therefore, when there is an error that can not be caught in one data, I understand how it affects other data, so I will handle the propagation error here. As a result, the ERROR flag becomes a VERROR flag that newly includes a propagation error. Of course, if the error data is not important for image reproduction,
The deframing circuit also performs processing for making a certain modification to the image data and deleting the error flag.

The image data is added to the data decompression encoder. That is, the data before compression is restored through the inverse quantization circuit 31 and the inverse compression circuit 32. Next, the data is returned to the original image space arrangement by the deshuffling 33 and the deblocking 34. Only after returning the data to the real image space, the image concealment becomes possible based on the VERROR flag. That is, for example, the image data of one frame before is always stored in the memory, and the image block in error is substituted with the previous image data. This uses the correlation with the previous image, and of course, when there is no correlation like a scene change, the deception does not work. However, this method is often used as a last resort.

Now, after the deshuffling 33, the data is divided into three systems of a luminance signal and a color difference signal and handled. And 3
The D / A converter 5 returns the analog components of Y, RY, and BY. For the clock at this time, an oscillation circuit 39 and an output obtained by dividing the oscillation circuit by a frequency divider 40 are used. That is, Y is 13.5 MHz and RY and BY are 6.7.
It is 5 MHz or 3.375 MHz. The three signal components thus obtained are combined by the Y / C combining circuit 36, and further combined by 37 with the composite synchronizing signal of the synchronizing signal generating circuit 41, and output from 42 as a composite video signal.

ADATA is added to AUD by the switch 43.
It is divided into io data and AAUX data. Aud
The io data is given to the deframing circuit 44 together with the ERROR flag. The deframing circuit performs the inverse conversion of the framing, and grasps the property of the data packed in it. Therefore, when there is an error that can not be caught in one data, I understand how it affects other data, so I will handle the propagation error here. For example, at the time of 16-bit sampling, since one data is in 8-bit units, one ERR
The OR flag will span two data. As a result, the ERROR flag becomes an AERROR flag that newly includes a propagation error.

The audio data is returned to the original time axis by the next deshuffling circuit 45. At this time, the audio data repair work is performed based on the AERROR flag. That is, since an error in the audio immediately becomes a "buzz" sound, a process such as a previous value hold in which the sound immediately before the error is substituted is performed. If the error period is too long and the deception does not work, processing such as muting is performed to stop the sound itself. After such processing, it is returned to an analog value by the D / A converter 46, and output to 47 while timing of image data and lip sync, etc. is taken.

The respective data of VAUX and AAUX separated by the switches 29 and 43 are subjected to preprocessing such as majority processing with reference to an error flag by a dedicated IC such as 48 or 50. Subcode sector ID
The section SID and the data section SDATA are given to the dedicated IC 49, and here also preprocessing such as majority processing is performed with reference to the error flag. Then, it is given to the signal processing microcomputer 51, and a final reading operation is performed. The errors that could not be removed at this time were VAUXER and
Signal processing microcomputer 51 as SUBER and AAUXER
Given to. The respective ICs 48, 49 and 50 also perform the generation processing of AP2, AP3 and AP1, respectively.

Supplementing the error processing here,
Each area has a main area and an optional area. And in the case of 525 / 60Hz system,
The same data is written 10 times in the main area.
Therefore, even if some of them have an error, they can be supplemented and reproduced with other data, and the ERROR flag there is no longer an error. However, since the data is written once for the optional areas other than Subcode, the error remains VAUXER, SUBER, AA.
It will remain as a UXER. Signal processing microcomputer 51
Further performs analogy from the context of the pack of each data, and performs propagation error processing and data repair processing. The result of this determination is given to the mode processing microcomputer 17 and used as a material for determining the behavior of the entire set.

In the present invention, the above-mentioned application data (identification code = APT, APn (n = n =
1, 2, 3) and APM) are defined as shown in FIG. That is, this application data has a hierarchical structure as shown. The structure of the area on the track is defined by the original application data APT. Furthermore, application data A in each area
Pn is provided for these application data AP
The structure of data inside each area is defined by n. In addition, the application data APM allows MIC
The structure of the above data is specified.

In this way, the structure of each recorded / reproduced data is defined. The number of areas in the second layer is defined by the application data APT. Further, in the example of FIG. 4, the hierarchical structure of the application data on the track is two layers, but a lower layer may be provided if necessary. On the other hand, the application data on the MIC has only one layer, and the same value as the application data APT of the device is written by the digital signal recording / reproducing device.

In the above apparatus, when the application data APT is set to "000", the apparatus is set to a digital VCR, and the entire track format is determined as shown in A of FIG. That is, in the figure, an area 0, an area 1 with a gap G1, an area 2 with a gap G2, and an area 3 with a gap G3 are provided from the top (left) side, and a margin is provided at the end. To be

Further, in this figure, area 0 is the above-mentioned ITI sector, and as shown by B in the figure, first, an amble part for 1400 bits and an SSA (Start-Sync block Area) for 1830 bits.
An a) section, a TIA section for 90 bits, and an amble section for 280 bits are provided. After this, a gap G1 for 625 bits is provided.

Here, 1830 bits are 6 in the SSA section.
It is divided into one block, and a numerical value of 0 to 60 is sequentially provided in each 30-bit block. As a result, the position of the head on the track is detected by reproducing even one of these blocks, and the timing at the time of insertion is formed.

Further, in the TIA portion, as shown in C of the figure, first, a 10-bit synchronizing portion, an 8-bit first data portion, a 2-bit dummy data portion, and an 8-bit second data portion. A total of 30 bits of TIA data consisting of a 2-bit dummy data section is repeatedly provided three times. The first
Application data APT is 2 in the data part of
It is set up once. Further, in the second data portion, the data SP / LP defining the track width and the pilot frame PF are provided twice each.

Area 1 is a recording area for audio data when the above-mentioned application data AP1 is "000". That is, 5 at the beginning of area 1
An amble portion (run-up) for 00 bits is provided. This is followed by 14 sync blocks consisting of a sync signal of 2 bytes, an ID signal of 3 bytes, a data signal of 77 bytes, and an inner parity of 8 bytes, for a total of 90 bytes. After this, an amble part (guard area) for 550 bits is provided. Further, after this, a gap G2 for 700 bits is provided.

Here, the 14 synchronization blocks are arranged as shown in A of FIG. Of the 77 bytes of the data signal, the first 5 bytes of the first 9 sync blocks are the AAUX signal and the rest are audio data. In addition, 77 bytes of the data signal of the last 5 sync blocks are used as the outer parity. The data of 14 sync blocks, each of which has a total of 90 bytes, is converted into a total of 10500 bits by 24/25 conversion.

Before and after these 14 synchronization blocks, as shown in the figure, the front side (the end of the run-up).
2 blocks of pre-synchronization signals and 1 block of post-synchronization signals are provided on the rear side (the head of the guard area). These pre-synchronization and post-synchronization signals are composed of a sync signal of 2 bytes, an ID signal of 3 bytes, and a data signal of 1 byte. The data signal of the pre-synchronization signal has data SP
/ LP is provided. The data signal of the post-synchronization signal is dummy data.

Further, the structure of the ID signal is as shown in B of FIG. That is, the application data AP1 is provided in 3 bits on the MSB side of the first byte (ID0) of each ID signal of the pre-sync and post-sync signals. Also, the application data AP1 is provided in the 3 bits on the MSB side of the first byte of each ID signal of the above-mentioned five outer parity synchronization blocks. In addition, sequence number data SEQ is provided in 4 bits on the MSB side of the first byte of each ID signal of each of the 9 synchronization blocks of the AAUX signal and audio data. The 4th bit on the MSB side of the 1st byte of each of the ID signals of the front and rear synchronization signals and the outer parity has the LS of the sequence number.
B is provided.

Also, the LSB of the first byte of each ID signal of the 17 sync blocks including the pre-sync and post-sync signals.
4 bits on the side have data T of the track number in the frame
RK is provided. Each I of the 17 further sync blocks
The second byte (ID1) of the D signal is provided with the data SNC of the sync block number in the track. Note that the synchronization block number is # 0 including the signals of the front synchronization and the rear synchronization.
Numerical values of # 1 to # 16 (# 0 to # 168 are continuously provided in the recording area of video data described later) are also provided. The third byte (IDP) of each ID signal is the inner parity of the first and second bytes.

Further, the area 2 is a recording area of video data when the above-mentioned application data AP2 is "000". That is, 50 is at the beginning of area 2.
An amble part (run-up) for 0 bits is provided.
This is followed by a sync signal of 2 bytes, an ID signal of 3 bytes, a data signal of 77 bytes, and an inner parity of 8 bytes, for a total of 9 bytes.
There are 149 synchronization blocks of 0 bytes.
After this, the amble part for 975 bits (guard area)
Is provided. After this, a gap G3 for 1550 bits is provided.

Here, the 149 sync blocks are arranged as shown in A of FIG. The 77 bytes of the data signal are the first and second synchronization blocks (# 19, # 2
0) and the 138th synchronization block (# 156) in the middle are VAUX signals, and 135 synchronization blocks (# 21 to # 155) in between are video data. In addition, 11 synchronization blocks (# 157-
77 bytes of the data signal of # 167) is used as the outer parity. It should be noted that the data of 149 synchronization blocks consisting of a total of 90 bytes described above is made into a total of 111750 bits by 24/25 conversion.

Further, before and after these 149 synchronization blocks, signals for pre-synchronization and post-synchronization similar to the above-mentioned audio data recording area are provided. Further, data SP / LP and dummy data are provided in these pre-synchronization and post-synchronization signals and 149 synchronization blocks, respectively.
Furthermore, the first and second bytes of the ID signal (ID0,
7B, application data AP2, sequence number data SEQ, track number data TRK in the frame, and sync block number data SNC in the track are provided in ID1). The sync block number is 17 to 16 in the video data recording area.
A number of 8 is provided.

Further, area 3 is a subcode recording area when the above-mentioned application data AP3 is set to "000". In other words, at the beginning of area 3, 120
An amble part (run-up) for 0 bits is provided.
This is followed by a sync signal of 2 bytes, an ID signal of 3 bytes, a data signal of 5 bytes, and an inner parity of 2 bytes, for a total of 12 bytes.
Twelve synchronization blocks made up of bytes are provided. After this, an amble part (guard area) for 1200 bits is provided.

Here, 12 synchronization blocks (S # 0 to S #
# 11) is arranged as shown in FIG. The 12 bytes of the internal data signal are a data main area alternately defined for every three sync blocks and an optional data area arbitrarily defined by the user. Data such as a time code and recording date and time are recorded in the main area. Further, as shown in the figure, the main area and the optional area of the data are arranged so that the two fields constituting one frame of the video data have opposite arrangements.

The structure of the ID signal is as shown in FIG. That is, in FIG. 9, the first byte (ID0)
From the MSB side of the above, one bit is used as an identification signal for discriminating the two fields forming one frame. The next 3 bits are used as the area of the application data AP3 in the first and seventh synchronization blocks, and are used as the area of the application data APT in the 12th synchronization block. In the remaining sync blocks, 3 bits are used as an area for TAG data such as an index I, a skip S, and a picture photo P for reproducing a still image.

Further, an absolute track number from the recording start end of the tape is provided in a total of 8 bits of 4 bits on the LSB side of the first byte and 4 bits on the MSB side of the second byte (ID1). This absolute track number has a total of 24 bits of 23 when the three sync blocks are grouped together.
It is composed of a binary value of bits and a blank flag BF of 1 bit. This absolute track number is repeatedly provided for one track four times with the same data.

The data SNC of the synchronous block number (0 to 11) in the track is provided in the 4 bits on the LSB side of the second byte. The third byte (IDP) of the ID signal is the inner parity of the first and second bytes. It should be noted that the data of 12 synchronization blocks, each of which has a total of 12 bytes, is 1200 bits in total by the 24/25 conversion.

The MI provided on the cassette half 39
When the above-mentioned application data APM is set to “000”, a data structure as shown in FIG. 10 is defined in C41. That is, in FIG. 10, the address "0
The application data APM is provided in 3 bits on the MSB side of 1 byte of "000", and the basic cassette identification signal (BCID) is provided in the 5 bits on the LSB side. The identification signal (BCID) is, for example, 8 mmV, such as tape thickness, tape type, tape grade, etc.
The same content as the CR recognition hole is provided.

Further, each storage area after the address "0001" has a pack structure of 5 bytes, which will be described later. For example, a pack of each data of cassette ID, tape length and title end is sequentially provided. An additional pack is provided after these basic packs. The cassette ID pack is provided with a specific tape thickness value rather than the identification signal (BCID) tape thickness and memory information of the MIC 41. In addition, the tape length pack,
The tape manufacturer provides a value that represents the tape length of the cassette by the number of tracks. Further, in the pack at the title end, the information on the final recording position is stored as an absolute track number. This allows the remaining tape amount to be calculated immediately by simply inserting the cassette into the device.
Further, it is possible to provide good usability when returning to the final recording position after mid-playback with a camera-integrated VCR or when making a timer reservation.

Thus, according to the above-mentioned digital signal recording / reproducing method, the structure of the data of the entire recorded / reproduced track is defined by the identification code added to the area for discriminating the reference position of the recorded signal in the track. To be done. The individual identification code added to each signal area defines the data structure of each signal area. This allows products that record and reproduce completely different data over the entire track to coexist with the same mechanism and the same servo system.
Furthermore, it is possible to record and reproduce completely different data for each signal area. Therefore, a digital platform machine in the true sense can be realized, and various miscellaneous data can be collected and processed in one machine.

Further, according to the above digital signal recording / reproducing method, when the application data APT is "000", the AAUX signal for assisting the audio data, the VAUX signal for assisting the video data, the data signal of the subcode, Each storage area after the address “0001” of the MIC 41 is described by a common pack structure described below.

That is, one pack is composed of 5 bytes as shown in FIG. 11, the first 1 byte is a header, and the remaining 4 bytes are data. A pack means a minimum unit of a data group, and each pack is formed by collecting related data. Further, 1 byte (= 8 bits) of the header is divided into 4 bits on the MSB side and 4 bits on the LSB side, and each has a hierarchical structure of two layers as an upper header and a lower header as shown in FIG. Note that it is possible to extend further down the hierarchy by bit assignment of data.

By this layering, the contents of the pack are clearly organized and the expansion thereof becomes easy. The space of 256 by the upper header and the lower header is shown in FIG.
It is prepared with the contents of each pack as the only pack header table as shown in. That is, according to this pack header table, each AAUX signal, VAUX signal, subcode data signal, MIC 41 address "0001"
Each subsequent storage area is controlled. The pack structure is basically a fixed length of 5 bytes as described above, with the only exception when character data is described in the MIC41.
A variable-length pack structure, which is separately defined to effectively use the limited memory, is used.

Therefore, AAU for assisting audio data
The X signal is provided with 5 bytes for each of the above-described sync blocks, and data is configured with these 5 bytes as one pack. Therefore, 9 packs per track (0-8)
Is configured, for example, 1 that constitutes one frame of NTSC
If only the 0-track pack is extracted and arranged,
As shown in. And in this FIG.
Packs numbered with 55 are basic packs, and basic data as shown in FIG. 15 is provided in each of these packs.

That is, the above-mentioned numbers 50 to 55 indicate the values (hexadecimal number) of the pack header. Therefore, the pack header value 50 is a pack indicating a signal source, and this pack is provided with data such as the sampling frequency, the number of quantization bits, the number of channels, and the stereo format. The pack header value 51 is a pack indicating signal source control, and data such as a recording mode is provided in this pack. When the value of the recording mode data is "00", all the data in the area are invalid data.

Further, the pack header value 52 is a pack indicating a recording date, and data such as a time zone of year, month, week, day and time difference is provided in this pack. The pack header value 53 is a pack indicating the recording time,
In this pack, data such as hour, minute, second and frame of recording time are provided by a two-digit numerical value. Further, the pack header value 54 is a pack indicating a binary group, and the pack is provided with binary numbers 1 to 8.
Furthermore, the pack header value 55 is an undefined pack.

In this way, the basic pack of the AAUX signal is provided. Note that these basic packs include items such as the sampling frequency and the number of quantization bits that are indispensable for audio data playback, and are extremely important data. Strengthening the protection of. Also, by changing the position of the basic pack for each track, it is possible to reliably reproduce the data of the basic pack even in the case of lateral scratches that are common in tape transport and accidents such as one-channel clogs. There is.

Further, the remaining packs other than the above-mentioned basic packs are removed as shown in a, b, c ... This additional pack is N
30 packs are provided for one frame of TSC and 36 packs are provided for one frame of PAL, and any one is selected from the above header table and provided. That is, for example, a number obtained by dividing the audio data into arbitrary chapters or parts, text data of the title, and the like are provided.

The additional pack is made up of common common options (for example, character data) and maker's options individually defined by each maker. These are additional (optional), so one or both may not be present. The common option and the maker's option, or the basic pack and the maker's option are separated by the appearance of the maker code pack, and thereafter, the maker's option is defined.

Further, the VAUX signal for assisting the video data is provided with 77 bytes for each of the above sync blocks. Therefore, as shown in FIG. 16, these bytes are divided into 5 bytes to form data as 1 pack. Therefore, 45 packs (0 to 44) are formed per track, and the remaining 2 bytes are undefined. When these 45 packs are extracted and arranged, for example, only the packs of 10 tracks constituting one frame of NTSC are arranged, as shown in FIG. And this Figure 17
In, the packs numbered 60 to 65 are basic packs, and these packs are respectively provided with basic data as shown in FIG.

That is, each of the above-mentioned numbers 60 to 65 indicates a value (hexadecimal number) of the pack header. Therefore, the pack header value 60 is a pack indicating a signal source, and data such as a television system, a screen aspect ratio, a broadcast channel (3 digits), a field frequency, etc. is provided in this pack. The pack header value 61 is a pack indicating signal source control, and data such as a recording mode is provided in this pack. When the value of the recording mode data is "00", all the data in the area are invalid data.

Further, the pack header value 62 is a pack indicating a recording date, and data such as a time zone of year, month, week, day and time difference is provided in this pack. The pack header value 63 is a pack indicating the recording time,
In this pack, data such as hour, minute, second and frame of recording time are provided by a two-digit numerical value. Further, the pack header value 64 is a pack indicating a binary group, and the pack is provided with binary numbers 1 to 8.
Further, the pack header value 65 is a pack of teletext (closed caption), and includes upper byte data and lower byte data of closed caption data provided in the 21st scan line of the first and second fields, respectively.

In this way, the basic pack of VAUX signal is provided. Note that these basic packs include items that are essential for playing video data, such as the television system and screen aspect ratio, and are extremely important data, so the same pack is repeatedly provided for each track.
Strengthening data protection. Also, by changing the position of the basic pack for each track, it is possible to reliably reproduce the data of the basic pack even in the case of lateral scratches that are common in tape transport and accidents such as one-channel clogs. There is.

Further, the remaining packs other than the above-mentioned basic packs are removed as shown in a, b, c, ... This additional pack is N
One frame of TSC is provided with 390 packs, and one frame of PAL is provided with 468 packs, and any one is selected from the above header table and provided. The method of handling this additional pack is the same as the case of the AAUX signal of the audio data described above.

The sub-code data signal is provided with 5 bytes for each of the above-mentioned sync blocks.
The data is composed of bytes as one pack. Therefore 1
12 packs (0 to 11) are formed per track. For example, when only packs of 10 tracks forming one frame of NTSC are extracted and arranged, it becomes as shown in FIG.

In FIG. 19, packs with capital letters A to E are basic packs, and basic data such as time code and recording date and time are provided in these packs. It should be noted that these basic packs are repeatedly provided as shown in the figure to protect data, and are also read out at the time of high-speed search so that the pack search using the above-mentioned basic data is performed. Also a
~ L lowercase packs are additional packs,
As for this additional pack, the pack of the same data (indicated by the same character) is repeatedly provided as shown in the figure to protect the data.

Further, the address "0001" of the MIC41
Each storage area thereafter has a pack structure of 5 bytes each as described above, and packs of the above-mentioned cassette ID, tape length, and title end data are sequentially provided. An additional pack is provided after these basic packs.
In addition to the fixed-length pack of 5 bytes as described above, the additional pack uses a variable-length pack structure that is separately specified to effectively use the limited memory when writing character data. To be The variable-length pack structure is defined by using a pack indicating a variable-length start end and a pack indicating an end.

The digital video signal as described above is converted to DC.
In a consumer-use digital VTR that is T-converted or variable-length coded and is recorded on a magnetic tape by a rotary head, the recording rate after compression of the video section is about 2 in the standard recording mode.
It is set to 5 Mbps. On the other hand, an all-digital HDTV that compresses an HDTV signal by a high-efficiency coding method that combines DCT conversion, variable-length coding, and motion compensation, and also compresses an audio signal, and transmits using terrestrial waves. Broadcast (hereafter ATV * Advanced T
V) is proposed. Various methods have been proposed for such an ATV signal, but it has been reported that the transmission rate thereof will be at most about 20 Mbps including video and audio.

Therefore, in order to record / reproduce such an ATV broadcast by the VTR in this embodiment, the application of Area2 allocated as the area of Video is applied.
The value of the application ID (AP2) may be newly set to something other than 000, and recording / reproduction may be performed. In this case, Aud
The areas of io and Subcode may be the same as before.

However, in the ATV signal system, there is a possibility that the transmission rate may exceed 25 Mbps. In this case, since it cannot fit in the Area2 allocated as the video area any more, the portion of the audio area Area1 is also used, for example. At this time, a new Ar
The value of the Application ID (AP1) of ea1 is set to something other than 000 and used. The advantage of this method is that the circuit of the standard recording mode is used as it is and only the input signal is switched.

However, according to this method, data having the same property is protected by two different product code configurations, and there are various problems in reliability of image reproduction, capture in variable speed reproduction, and the like. . When making a product with an unacceptable level, it is desirable to set the main APT to something other than 000 and change the track format itself. Data is protected by newly designing the product code structure corresponding to the recording rate. Also in this case, if the position of the Subcode sector in the standard recording mode is left as it is, the IC and microcomputer software related thereto can be used as it is.

The above story will be summarized and illustrated. Figure 20
Is that. First, when recording / reproducing in the track format of APT = 000. Standard recording mode AP1 = 000, AP2 = 000, AP3 = 000 ATV recording mode (25 Mbps or less) AP1 = 000, AP2 = 001, AP3 = 000 ATV recording mode (when exceeding 25 Mbps) AP1 = 002, AP2 = 002, AP3 = 000 Next, when recording / reproducing by changing the APT. ATV recording mode AP1 = 000, AP2 = 000

ATV broadcasting is transmitted by a so-called packet structure. FIG. 21 shows an example. A service type is provided at the beginning of the packet. This is an ID indicating the attribute of this packet. For example, 00h is a video packet, 01h is an audio packet, and 02h is an AUX packet. This service data is followed by each data, and parity for data protection is added. As shown in FIG. 22, this packet is modulated in a mixed form and enters a radio wave.

Next, a VTR for recording / reproducing this ATV broadcast
A specific circuit example of the above will be described. Here, the VTR of the baseband recording / reproducing system described in FIGS. 1, 2 and 3 is used.
The coexistence circuit with and will be described. In the case of a VTR having only the ATV, the part relating to the baseband recording / reproduction may be deleted. FIG. 23 shows the recording side circuit of the ATV VTR, and FIG. 24 shows the reproducing side circuit.

First, the recording side circuit. In this example, APT = 00
It is a coexistence circuit with a rate of 25 Mbps or less, which is recorded in Area 2 at 0. In FIG. 23, the ATV radio signal captured by the ATV antenna A1 is the ATV A2 signal.
A desired channel is selected by the receiving circuit. This is extracted in packet units as shown in FIG. 21 by the ATV demodulation unit A3. This is subjected to error detection and correction by an error correction circuit A4. Service data is extracted from the confirmed packet data, and the switch A6 is switched based on this information. The switches A13a, A13b, A13c are switched to the upper side during recording.

In the case of AUX packet, switch A6
Switches to the top, and for video / audio packets to the bottom. The AUX packet is decoded by the A8 AUX decoder. At this time, the error ATVER that cannot be completely removed by the error correction circuit A4 is reflected in this decoder. For video / audio packets,
Further, it is switched by the switch A7 and decoded by the video decoder A9 and the audio decoder A10. At this time also, error countermeasures are taken based on the ATV rules.
This decoded output is sent to the monitor TV and reproduced as a received audio image.

When recording on the VTR, it is efficient and excellent in image quality to record and reproduce without decoding both video and audio. Therefore, the packet structure is recorded and reproduced as it is. If so, it may be possible to record the video / audio packet without passing through an error correction circuit, but the error that occurred when it was transmitted as radio waves and the error caused by passing through the electromagnetic conversion system are multiplexed. A, because at least it is clear that it will be in the wrong direction.
It is a good idea to fix errors that can be corrected on the TV tuner side in advance.

The recording buffer circuit 11 is for adjusting the timing of filling the framing circuit 11.
ATVER is not input here. Video / audio packet data is recorded / reproduced with errors other than correctable errors. The processing is entrusted to the video / audio decoder which is finally input during reproduction.
The switch 12 is switched by the mode processing microcomputer 34 by switching the input to the adder circuit 16, and is set to the lower side in the standard mode and the upper side in the ATV recording.

The output of the AUX decoder A8 is applied to the signal processing microcomputer 20, and is edited and recorded in a pack structure in the VAUX area based on the rule of APT = 000. At this time, IC17 for VAUX is A of ATV
It works for storing UX, and the value of AP2 is set to 001 as in the example of FIG.

When the audio is recorded in the area 1 and the video is recorded in the area 2 in FIG. 20, the timing is adjusted through the buffer circuits from the latter stage of the switch A7 in FIG. 23, and then input to the audio / video framing circuit. If the rate exceeds 25 Mbps, a new dedicated error correction code circuit is required. The output is shown in Figure 2.
Switch to the 3rd channel coder with a switch and input.

Next, the reproducing side circuit of FIG. 24 will be described. The tape is reproduced, and the mode processing microcomputer 17 receives the APT information from the ITI channel decoder. By judging this, it is judged which type of recording in FIG. Here, a coexistence circuit whose rate is 25 Mbps or less, which is recorded in Area 2 with APT = 000, is shown. Playback mode, so switches A13a, A13b, A13c
Is switching to the bottom.

The data corrected by the error correction circuit 25 is switched by the switch 26, and the data in the area 2 is input to the switch 29 as VDATA. Here, it is divided into video data and VAUX data.
The VAUX IC 48 restores the AP2. AP2 is
Through the signal processing microcomputer 51, the mode processing microcomputer 1
7. Here, when AP2 = 001, since ATV data is contained in area 2, the circuit operation after the deframing 30 for the standard recording mode is stopped.

After that, the output of the reproduction buffer circuit A14, which has been storing the data in area 2, becomes active for a period of time until the detection and determination of AP2 is performed in advance. Data of a SYNC block dedicated to video data and an ERROR flag for the data are stored here. The data of the reproduction buffer circuit A14 is also added to the service type extraction circuit A5, and it is judged here whether it is an audio packet or a video packet. Thereby, the switch A7 is switched. Whether the service type extraction circuit A5 judges the packet from A4 or the packet from A14 depends on the instruction from the mode processing microcomputer 17.

To the video decoder A9 and the audio decoder A10, error data generated during reproduction is input in addition to the respective packet data. First, based on this, each decoder determines where and how the error affects, and performs propagation error processing. After that, an error that cannot be completely removed due to an error that occurred when it was transmitted as a radio wave during recording is detected using the parity of FIG.
The above error data is processed based on the ATV processing rule. In this way, each video / audio data is restored.

Here, there is no AUX packet that originally existed. This is because the contents are disassembled at the time of recording and are edited again as a pack structure in the VAUX area and then recorded on the tape. At the time of reproduction, since the contents are read and processed, there is no need to reassemble them into an AUX packet.

When the audio is recorded in the area 1 of FIG. 20 and the video is recorded in the area 2, the timing is adjusted through the reproduction buffer circuit and input after the switch A7 of FIG. If the rate exceeds 25 Mbps, a new error correction code circuit for it is required. The output is input to the reproduction buffer circuit A14.

[0100]

According to the digital signal recording / reproducing method of the present invention, the structure of the data of the entire track to be recorded / reproduced by the identification code added to the area for discriminating the reference position of the recording signal in the track. Is prescribed. The individual identification code added to each signal area defines the data structure of each signal area. This allows products that record and reproduce completely different data over the entire track to coexist with the same mechanism and the same servo system. Furthermore, it is possible to record and reproduce completely different data for each signal area. Therefore, a digital platform machine in the true sense can be realized, and various miscellaneous data can be aggregated and processed in one machine.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an example of a recording system of a digital VCR to which a digital signal recording / reproducing method according to the present invention is applied.

FIG. 2 is a configuration diagram of an example of a reproducing system of a digital VCR to which the digital signal recording / reproducing method according to the present invention is applied.

FIG. 3 is a block diagram of an example of a reproducing system of a digital VCR to which the digital signal recording / reproducing method according to the present invention is applied.

FIG. 4 is a schematic diagram for explaining a structure of application data according to the present invention.

FIG. 5 is a schematic diagram showing an example of a structure of an area on a track for the purpose of explanation.

FIG. 6 is a schematic diagram showing an example of an audio data recording area for the purpose of explanation.

FIG. 7 is a schematic diagram showing an example of a recording area of video data for the purpose of explanation.

FIG. 8 is a schematic diagram showing an example of a subcode recording area for the purpose of explanation.

FIG. 9 is a schematic diagram illustrating an example of a subcode recording area for the purpose of explanation.

FIG. 10 is a schematic diagram showing an example of stored data in a memory for the purpose of explanation.

FIG. 11 is a schematic diagram for explaining the structure of the pack.

FIG. 12 is a schematic diagram for explaining a hierarchical structure of a pack header.

FIG. 13 is a schematic diagram for explaining a pack header table.

FIG. 14 is a schematic diagram for explaining a pack of an AAUX signal.

FIG. 15 is a schematic diagram showing an example of pack data for the explanation.

FIG. 16 is a schematic diagram for explaining a pack of one track of VAUX signal.

FIG. 17 is a schematic diagram for explaining a pack of one frame of VAUX signal.

FIG. 18 is a schematic diagram showing an example of pack data for the explanation.

FIG. 19 is a schematic diagram for explaining a pack of subcode data signals.

FIG. 20 is a diagram for explaining ATV recording.

FIG. 21 is a diagram for explaining ATV recording.

FIG. 22 is a diagram for explaining ATV recording.

FIG. 23 is a diagram for explaining ATV recording.

FIG. 24 is a diagram for describing ATV recording.

[Explanation of symbols]

1 Antenna 2 Tuner 3a, 3b Switch 4 External analog video input 5 External analog audio input 6 Y / C separation circuits 7a, 7b, 7c LPF (Low Pass Fil)
ter) 8a, 8b, 8c A / D conversion circuit 9 Blocking circuit 10 Shuffling circuit 11 Sync separation circuit 12 PLL (Phase Locked Loop)
Circuit 13 Frequency divider 14 Data compression coding unit 15 Framing circuit 16 Combiner 17, 18, 19 IC circuit 20 Microcomputer 21 for signal processing A / D conversion circuit 22 Shuffling circuit 23 Framing circuit 24 Combiner 25 Signal generation circuit 26 Switch 27 Error Correction Code Generation Circuit 28 Mechanism Control Microcomputer 29 Randomization Circuit 30 24/25 Conversion Circuit 31 Combiner 32 Switch 33 ITI Sector Generation IC 34 Mode Processing Microcomputer 35 Switches 36a, 36b Head Amplifier 37a, 37b Head 38 Microcomputer for MIC processing 39 MIC contact 40 Switch 41 MIC (Memory In Casset)
e)

Continuation of the front page (56) Reference JP-A-5-234263 (JP, A) JP-A-5-210917 (JP, A) JP-A-5-144189 (JP, A) JP-A-5-101618 (JP , A) JP 4-315398 (JP, A) JP 3-296974 (JP, A) JP 3-119574 (JP, A) JP 3-80470 (JP, A) JP 1-8554 (JP, A) JP-A-1-8555 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11B 27/10-27/34

Claims (4)

(57) [Claims] 1. A one or more digital signal recording and reproducing method for recording and reproducing digital signal or analog signal as one or more signal recording area of the track on the recording medium the encoded signal for each predetermined amount, Select the number of signal recording areas provided on the tracks.
First identification signal to be determined, and the data length and synchronization block for each signal recording area
When recording a signal in the signal recording area by setting a second identification signal for selecting the length
One area defined as a synchronization area for determining the reference position of the recording signal in the track, adds Then together the first identification signal on the synchronization area
Add the second identification signal to each signal recording area
And said track and said at the first and second identification code
A digital signal recording / reproducing method characterized in that the structure of a signal recording area is defined. 2. The digital signal recording / reproducing method according to claim 1, further comprising memory means attached to the recording medium, wherein a third identification code is added to a specific location in the memory means.
And, provided in said memory means in said third identification code
A digital signal recording / reproducing method characterized in that a signal structure is defined. 3. One or more digital signals or audio signals.
A signal that encodes the analog signal is recorded on the recording medium in specified amounts.
As one or more signal recording areas on each track
In a digital signal recording / reproducing device for recording / reproducing, select the number of the signal recording areas provided on the track
Means for generating a first identification signal that determines the data length and synchronization block for each signal recording area
Means for generating a second identification signal for selecting a length, and the signal recording when recording a signal in the signal recording area
Set one of the areas to the reference position of the recording signal in the above track.
It is defined as a synchronization area for discrimination, and the first identification signal is added to the synchronization area.
Add the second identification signal to each signal recording area
And said track and said at the first and second identification code
A digital feature characterized by defining the structure of the signal recording area.
Tal signal recording / reproducing device. 4. A digital signal recording / reproducing apparatus according to claim 3.
In the Memory means attached to the recording medium is provided, Add a third identification code to a specific place in this memory means
Then Provided in the memory means with the third identification code
Digital signal record characterized by defining the structure of the signal
Recording / playback device.