JPH117720A - Variable data delay device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow data to be accurately delayed by an arbitrary time. SOLUTION: Under control of a CPU 15 and a sequencer circuit 23, a write address generating section 19 and a read address generating section 20 respectively generate a write address WA and a read address RA so that a difference between the write address WA and the read address PA has a predetermined value and data is read out in the order with which the data has been written. The write address WA and the read address RA are selectively supplied to a memory block 18. The memory block 18 alternately performs writing of input data DIN and readout of the data in accordance with the selected address, whereby the input data DIN is delayed by an arbitrary time to be output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a digital data recording / reproducing system such as a digital VTR (Video Tape Recorder) or a digital data recording / reproducing apparatus, for example. Related to the device.

[0002]

2. Description of the Related Art In recent years, digital data recording / reproducing systems such as digital VTRs and digital data recording / reproducing apparatuses have become widespread. When the host computer records and reproduces data using these digital data recording and reproducing systems, the operation of recording and reproducing is also checked. That is, the host computer performs data recording by the digital data recording / reproducing system, and then reproduces the data to confirm whether the recording has been correctly performed. At this time, if the time from recording to confirmation differs depending on the model of the digital data recording / reproducing system, the host computer must take this into account and create a program. Since the digital data recording / reproducing system is merely a storage device from the viewpoint of the host computer, it is very inconvenient to consider the above.

[0003]

SUMMARY OF THE INVENTION
In a digital data recording / reproducing system, in order to keep the time from recording to confirmation even if the model is different,
A means for delaying digital data by a desired time is desired. One of such means is FIFO (Firs
t In First Out) It is conceivable to use a memory, but the FIFO memory has a problem in that when a large amount of data is transferred at a high speed, a data error called data corruption occurs.

[0004] The present invention has been made in view of such a problem, and an object of the present invention is to provide a variable data delay device capable of accurately delaying data by an arbitrary time.

[0005]

According to a first aspect of the present invention, there is provided a variable data delay device, wherein a write and read position is specified by an address, a storage device for recording data, and a write device for generating a write address in the storage device. Address generating means, read address generating means for generating a read address in the storage means, a difference between the write address and the read address has a predetermined value, so that data is read in the order of writing,
By causing the write address generation means and the read address generation means to generate a write address and a read address, selectively supplying these addresses to the storage means, and causing the storage means to write input data and read data, A write / read control unit for delaying the input data by an arbitrary time and outputting the data.

According to a second aspect of the present invention, there is provided a variable data delay device comprising: first storage means for specifying a write / read position by an address; first write address generation means for generating a write address in the first storage means. A first read address generating means for generating a read address in the first storage means, a second storage means for specifying a write and read position by the address, and a second read address for generating a write address in the second storage means. A second write address generating means, a second read address generating means for generating a read address in the second storage means, and a difference between the write address and the read address having a predetermined value, and the data is read in the order of writing. The first write address generating means, the first read An address is generated by the address generating means, the second write address generating means and the second read address generating means, and these addresses are selectively supplied to the first storage means and the second storage means. Writing input data in the first storage means, reading data in the second storage means,
And a writing / reading control means for delaying the input data by a predetermined time and outputting the data by alternately performing reading of data in the storage means and writing of input data in the second storage means. .

In the variable data delay device according to the first aspect,
Under the control of the write / read control unit, the write address and the read address are generated by the write address generation unit and the read address generation unit so that the difference between the write address and the read address has a predetermined value and the data is read in the order of writing. An address is generated and selectively provided to the storage means. The storage means writes and reads the input data according to the selected address, whereby the input data is output after being delayed by an arbitrary time.

In the variable data delay device according to the present invention,
Under the control of the write / read control unit, the first write address generation unit and the first read address generation unit, and the second write address generation unit and the second read address generation unit set the write address and the read address. Has a predetermined value,
A write address and a read address are generated so that data is read in the order written, and the write address and the read address generated by the first write address generating means and the first read address generating means are selectively applied to the first address. The write address and the read address generated by the second write address generation means and the second read address generation means are supplied to the storage means, and are selectively supplied to the second storage means. The first storage unit and the second storage unit perform writing of input data and reading of data according to the supplied addresses. At this time, writing of input data in the first storage means and reading of data in the second storage means, and reading of data in the first storage means and writing of input data in the second storage means are alternately performed. As a result, the input data is output after being delayed by a predetermined time.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 3 is a block diagram showing a configuration of a digital data recording / reproducing system including the variable data delay device according to the first embodiment of the present invention. In FIG. 3, the arrow pointing rightward indicates the flow of the recording data 10a, and the arrow pointing leftward indicates the flow of the reproduction data 10b.

This digital data recording / reproducing system 1
0 indicates input of the recording data 10a or reproduction data 10a.
b, and a connector 11 for outputting
, A recording / reproducing processing unit 13 connected to the variable data delay unit 12, a head unit 14 connected to the recording / reproducing processing unit 13, a variable data delay unit 12, A CPU (central processing unit) 15 connected to the reproduction processing unit 13; The variable data delay device according to the present embodiment includes a variable data delay unit 12 and a CPU 15.

The variable data delay section 12 delays data from the connector 11 by an arbitrary time and outputs the data to the recording / reproducing processing section 13, and also delays data from the recording / reproducing processing section 13 by an arbitrary time to connect to the connector. 11 is output. Note that the variable data delay unit 12 may delay only one of the data from the connector 11 and the data from the recording / reproducing processing unit 13. At the time of recording, the recording / reproducing processing unit 13 divides the data from the variable data delay unit 12 into blocks of a certain size, adds an error detection / correction code to them, and performs channel coding to obtain a form suitable for recording. After the conversion, a block synchronization signal (hereinafter, simply referred to as a synchronization signal) is given to each block.
Is output to the head unit 14.
In addition, the recording / reproducing processing unit 13 controls the head unit 1 during reproduction.
4 recovers a raw data string from the data read from the recording medium and, if necessary, a clock corresponding to the data, reproduces a synchronization signal accordingly, performs channel decoding on the data, Error detection and error correction are performed using the detection / correction code, and output to the variable data delay unit 12.

The head unit 14 stores data from the recording / reproducing processing unit 13 in a recording medium (not shown) such as a video tape.
A recording head for recording data on a recording medium, a reproduction head for reproducing data from a recording medium, and outputting the data to the recording / reproduction processing unit 13;
And an erasing head for erasing data on the recording medium. In addition, the CPU 15 controls the variable data delay unit 12
It controls the operation of the recording / reproducing processing unit 13.

FIG. 1 is a block diagram showing a configuration of a variable data delay device 1 according to the first embodiment. The variable data delay device 1 includes a memory block 18 connected to an address bus 16 and a data bus 17, a write address generator 19 for generating a write address WA which is a write address in the memory block 18, Read address generator 20 for generating read address RA as a read address
An address selector 21 for selectively outputting to the address bus 16 a write address WA generated by the write address generator 19 and a read address RA generated by the read address generator 20; A data selector section 22 for switching data output from the data bus 17; The memory block 18, the write address generator 19, and the read address generator 20 correspond to a storage unit, a write address generation unit, and a read address generation unit of the present invention, respectively.

The variable data delay device 1 further includes a sequencer circuit 23 for controlling operations of the memory block 18, the address selector 21 and the data selector 22, and a write address generator 19 and a read address generator 20, respectively. Address setting signal 15
and a CPU 15 for outputting a reference signal 15c to the sequencer circuit 23 as an operation reference. The sequencer circuit 23 and the CPU
Reference numeral 15 corresponds to a write / read control unit in the present invention.

The memory block 18 has a write address W
A, a write position and a read position are specified by the read address RA, and a storage device capable of writing and reading is provided. The storage device may be, for example, an SRAM (static random access memory).
Memory) or DRAM (Dynamic Random Access Memory).

The write address generation section 19 and the read address generation section 20 respectively provide an address setting signal 15
The write address WA and the read address RA are generated so that the write address WA and the read address RA have a predetermined difference value on the basis of the settings by a and 15b, and are read in the order in which the input data is written. Has become.

The sequencer circuit 23 has an H (High) level and a L level at a predetermined cycle based on the reference signal 15c.
(Low) Selector control signal 23a whose level switches
Is generated and supplied to the address selector 21 and the data selector 22. Further, the sequencer circuit 23 generates a memory control signal 23b for controlling the writing and reading operations in the memory block 18 with reference to the reference signal 15c, and supplies the memory control signal 23b to the memory block 18. When writing data in the memory block 18, the sequencer circuit 23 outputs an L level selector control signal 23.
a, and an H-level selector control signal 23a is generated when data is read from the memory block 18.

The address selector 21 has two input terminals 21a and 21b, one output terminal 21c, and a control terminal. The input terminal 21a is a write address generator 19
, And the input terminal 21 b is connected to the output terminal of the read address generator 20. The output terminal 21
c is connected to the address bus 16, and the control end is connected to the sequencer circuit 23. A selector control signal 23a is applied to this control terminal from the sequencer circuit 23. When an L-level selector control signal 23a is applied to this control terminal, the output terminal 21c becomes the input terminal 21a.
The address selector 21 supplies the write address WA from the write address generator 19 to the address bus 16. When the H-level selector control signal 23a is applied to the control terminal, the output terminal 21c is switched to the input terminal 21b side, and the address selector unit 21 transfers the read address RA from the read address generation unit 20 to the address bus 16. To be supplied. That is, the address selector 21 alternately supplies the write address WA and the read address RA to the memory block 18 via the address bus 16. Thus, the data write position and the data read position in the memory block 18 are alternately designated.

The data selector section 22 has a gate 22a and a gate 2 for permitting and prohibiting data transmission, respectively.
2b. The input terminal of the gate 22a is connected to the data input section of the variable data delay device 1. Gate 2
The output terminal of 2a is connected to the data bus 17, and the control terminal is connected to the sequencer circuit 23. Also, the gate 22
The input terminal of b is connected to the data bus 17, the output terminal is connected to the data output unit of the variable data delay device 1, and the control terminal is connected to the sequencer circuit 23. A selector control signal 23a is applied from the sequencer circuit 23 to the control terminals of the gates 22a and 22b.

When the L-level selector control signal 23a is applied to the data selector 22, the gate 22a is in the output state and the gate 22b is in the high impedance state, and is input from the data input section of the variable data delay device 1. The data D _IN is transmitted to the data bus 17 as write data for writing. As a result, the write data is stored in the memory block 18 at the position specified by the write address WA in the memory control signal 23b.
Is written in accordance with. Further, the data selector unit 22 outputs an H level selector control signal 2
When 3a is applied, the gate 22a is in a high impedance state and the gate 22b is in an output state, and the read data read from the position specified by the read address RA in the memory block 18 is output to the data output of the variable data delay device 1. To the department. As described above, the variable data delay device 1 includes the memory block 18
, The input data D _IN is sequentially written to the memory block 18, and the memory block 1 is written in the written order.
The data is read out from the memory 8 and output.

Next, the operation of the digital data recording / reproducing system 10 shown in FIG. 3 will be described.

When recording data for recording on a recording medium,
In the digital data recording / reproducing system 10, for example, recording data 10a is input from a host computer (not shown). The recording data 10a input to the digital data recording / reproducing system 10 is input to the variable data delay unit 12 via the connector 11. The recording data 10a input to the variable data delay unit 12 is input to the recording / reproducing processing unit 13 after being delayed by a predetermined time. The data input to the recording / reproduction processing unit 13 is input to the head unit 14 after signal processing such as error detection and addition of a correction code, and is recorded on a recording medium via the head unit 14.
In the digital data recording / reproducing system 10,
The recorded data is reproduced to confirm by the host computer whether the recording data has been correctly recorded on the recording medium. In this case, the data already recorded is read from the recording medium by the head unit 14 and input to the recording / reproducing processing unit 13. The data input to the recording / reproducing processing unit 13 is subjected to signal processing such as error detection / correction and the like, and is input to the variable data delay unit 12 in a manner opposite to the recording.
The data input to the variable data delay unit 12 is delayed by a predetermined time and input to the host computer via the connector 11 as reproduction data 10b. The reproduction data 10b input to the host computer is compared with the recording data 10a. Thus, it is confirmed whether the recording data 10a has been correctly recorded on the recording medium. The operations of the variable data delay unit 12 and the recording / reproducing processing unit 13 are controlled by the CPU 15. Also,
By adjusting the amount of delay in the variable data delay unit 12, the time from data recording to confirmation by the host computer is unified regardless of the model.

Next, the operation of the variable data delay device 1 according to the present embodiment will be described. Since the variable data delay device 1 performs the same operation during recording and reproduction of the digital data recording / reproducing system 10, the data input to the variable data delay device 1 is hereinafter simply referred to as input data D _IN. The data output from the variable data delay device 1 will be described as output data D _OUT .

In the variable data delay device 1, the CPU 1
5 supplies the reference signal 15c to the sequencer circuit 23 and the address setting signals 15a and 15b to the write address generator 19 and the read address generator 20.
The sequencer circuit 23 generates a selector control signal 23a that switches between an H level and an L level in a predetermined cycle based on the reference signal 15c, and supplies the selector control signal 23a to the address selector 21 and the data selector 22. Further, the sequencer circuit 23
Generates a memory control signal 23b for controlling the write and read operations in the memory block 18 based on the reference signal 15c,
Give to.

The write address generator 19 and the read address generator 20 provide address setting signals 15a, 15b
Are given, the write address WA and the read address RA have a predetermined difference value, and the write address WA is read so that the input data is read out in the order of writing.
And a read address RA. These write address WA and read address RA are output to the address selector unit 21, respectively.

When writing input data to the memory block 18, the sequencer circuit 23 supplies an L-level selector control signal 23 a to the address selector 21 and the data selector 22. In the address selector unit 21 to which the L-level selector control signal 23a is given, the output terminal 21c is switched to the input terminal 21a side to selectively output the write address WA to the address bus 16. As a result, the write address WA is supplied to the memory block 18, and the write position in the memory block 18 is specified. On the other hand, in the data selector unit 22 to which the selector control signal 23a at the L level is applied, the gate 22a is set to the output state, and the gate 22b is set to the high impedance state.
Then, the input data D _IN input from the data input unit of the variable data delay device 1 is transmitted to the data bus 17 as write data. The write data transmitted to the data bus 17 is written in the memory block 18 at the position specified by the write address WA in accordance with the memory control signal 23b.

At the time of reading data from the memory block 18, the sequencer circuit 23 supplies an H-level selector control signal 23 a to the address selector 21 and the data selector 22. H level selector control signal 2
3a, the output terminal 21c is switched to the input terminal 21b to change the read address R
A is selectively output to the address bus 16. As a result, the read address RA is supplied to the memory block 18 and the read position in the memory block 18 is specified. On the other hand, in the data selector unit 22 to which the selector control signal 23a at the H level is applied, the gate 22a is set to a high impedance state, and the gate 22b is set to an output state.
Then, in the memory block 18, read data is read from the position specified by the read address RA in accordance with the memory control signal 23b, and the read data is transferred to the variable data delay device 1 via the data bus 17 and the gate 22b. The data is transmitted to the data output unit and output as output data D _OUT .

Next, an example of a specific operation of the variable data delay device 1 according to the present embodiment will be described with reference to the timing chart of FIG.

FIG. 2A shows the reference signal 15c.
(B) shows the selector control signal 23a. Also,
FIG. 2C shows an address signal on the address bus 16, and FIG. 2D shows a data signal on the data bus 17.

As shown in FIGS. 2A to 2D, in this example, the selector control signal 23a is a signal that switches between H level and L level every one cycle of the reference signal 15c. While the selector control signal 23a is at the L level, the address bus 16
1, the write address WA is selectively output, and the write address WA is supplied to the memory block 18. In this example, the write address WA increases in the order of n, n + 1, n + 2,. As a result, the data write position in the memory block 18 is specified. On the other hand, input data D _IN from the data input unit of the variable data delay device 1 is output to the data bus 17 as write data WD.
In this example, the write data WD is W0, W1, W2,
... In the memory block 18, the write data W0 is written to the address n in accordance with the memory control signal 23b, and the write data W1 is sequentially written to the position specified by the write address WA, such that the write data W1 is written to the address n + 1. I will go.

During the period when the selector control signal 23 a is at the H level, the read address RA is selectively output to the address bus 16 by the address selector 21, and the read address RA is supplied to the memory block 18. In this example, the read address RA increases in the order of k, k + 1, k + 2,... With the initial value being k. As a result, the data reading position in the memory block 18 is specified. On the other hand, data is output to the data bus 17 as read data RD from a position specified by the read address RA in the memory block 18. In this example, it is assumed that the read data RD changes as R0, R1, R2,. In the memory block 18, the memory control signal 23b
, The read data RD is sequentially read from the position specified by the read address RA, such that the read data R0 is read from the address k and the read data R1 is read from the address k + 1.

As described above, in the variable data delay device 1, the selector control signal 2 output from the sequencer circuit 23 is output.
According to 3a, the write operation and the read operation of the memory block 18 are performed alternately. Further, in the variable data delay device 1, the time from writing to reading of the same data can be arbitrarily set by setting the initial value n of the write address WA and the initial value k of the read address RA. For example, the initial values of the write address WA and the read address RA are n = 2 and k, respectively.
= 0, and the input data D0, D1, D1 and D2 are input from the data input section of the variable data delay device 1 as shown in FIG.
When D2,... Are input, the data output unit of the variable data delay device 1 delays by 2.5 periods of the selector control signal 23a as shown in FIG.
Data D0, D1, D2,... Are output as output data. That is, the difference (nk) between the initial value n of the write address WA and the initial value k of the read address RA is 2
When the address is set so as to be as follows, the read address RA in the memory block 18 becomes the write address WA.
The position is two positions before the position. Therefore, after the input data signal is written to the write address WA, it is read and output in the third read operation.

As described above, according to the variable data delay device 1 of the present embodiment, the write address WA and the read address RA are set by the CPU 15 so that the difference between the write address WA and the read address RA has a predetermined value. RA is generated in the write address section 19 and the read address generation section 20, respectively, and these addresses are selectively selected by the sequencer circuit 23 in the memory block 18.
Further, the write operation and the read operation of the memory block 18 are alternately performed by the sequencer circuit 23, thereby reading the input data D _IN in the order of writing. By setting the address RA, the input data D
_IN can be output with an accurate delay for an arbitrary time.

It should be noted that the variable data delay device 1 can delay data at a high speed without a data error with a simple circuit configuration by increasing the frequency of the clock of the reference signal 15c.

In the variable data delay device 1 described above, the storage device used for the memory block 18 has a limit on the maximum frequency of the clock. Therefore, if the data transfer speed from the host computer etc. is very fast,
The variable data delay device 1 cannot respond to the transfer rate of the input data. The second embodiment is adapted to cope with high-speed data transfer.

FIG. 4 is a block diagram showing the configuration of the variable data delay device according to the second embodiment of the present invention. The variable data delay device 25 includes an address bus (1) 26
And a memory block (1) 28 connected to the data bus (1) 27; a write address generator (1) 29 for generating a write address WA which is a write address in the memory block (1) 28; A) read address generator (1) 30 for generating read address RA which is the read address in 28
And an address selector (1) for selectively outputting the write address WA generated by the write address generator (1) 29 and the read address RA generated by the read address generator (1) 30 to the address bus (1) 26. ) 31.

The variable data delay device 25 further includes a memory block (2) 34 connected to the address bus (2) 32 and the data bus (2) 33, and a write address as a write address in the memory block (2) 34. Write address generator (2) 35 for generating WA
And a read address generator (2) 36 for generating a read address RA which is a read address in the memory block (2) 34, and a write address generator (2) 35
And an address selector section (2) 37 for selectively outputting to the address bus (2) 32 a write address WA generated by the write address WA and a read address RA generated by the read address generation section (2) 36.

The variable data delay device 25 further includes a data input to the data bus (1) 27 and a data bus (2) 33.
A write data selector 38 for switching between data input to the data bus and a read data selector 39 for switching between data output from the data bus (1) 27 and data output from the data bus (2) 33.

The memory block (1) 28, the write address generator (1) 29 and the read address generator (1) 30 are the first storage means and the first address generator of the present invention, respectively.
Correspond to the write address generation means and the first read address generation means. Also, the memory block (2)
34, a write address generator (2) 35 and a read address generator (2) 36 correspond to a second storage unit, a second write address generation unit and a second read address generation unit, respectively, of the present invention.

The variable data delay unit 25 further includes a memory block (1) 28, a memory block (2) 34, an address selector (1) 31, and an address selector (2).
37, a sequencer circuit 40 for controlling operations of the write data selector 38 and the read data selector 39, and a write address generator (1) 29,
The address setting signals 15d, 15e, 15f and 15g are output to the read address generator (1) 30, the write address generator (2) 35 and the read address generator (2) 36, respectively. And a CPU 15 that outputs a reference signal 15h. The sequencer circuit 40 and the CPU 1
Reference numeral 5 corresponds to the write / read control means of the present invention.

The memory block (1) 28 and the memory block (2) 34 have write and read positions specified by the write address WA and the read address RA, and have a writable and readable storage device. In addition, as this storage device, for example, SRAM
And a DRAM.

The write address generator (1) 29 and the read address generator (1) 30 have a predetermined difference between the write address WA and the read address RA based on the setting by the address setting signals 15d and 15e, respectively. So that the input data is read out in the order in which it was written,
A write address WA and a read address RA are respectively generated. Similarly, the write address generator (2) 35 and the read address generator (2) 3
6 are a write address WA and a read address R based on the setting by the address setting signals 15f and 15g, respectively.
A has a predetermined difference value, and a write address WA and a read address RA are generated so that input data is read out in the order of writing.

The sequencer circuit 40 generates a selector control signal 40a that switches between H level and L level at a predetermined cycle based on the reference signal 15h, and uses this signal as an address selector (1) 31, an address selector ( 2) 3
7, the write data selector 38 and the read data selector 39. Further, the sequencer circuit 40 generates memory control signals 40b and 40c for controlling the write and read operations in the memory block (1) 28 and the memory block (2) 34 based on the reference signal 15h. Is given to the memory block (1) 28 and the memory block (2) 34, respectively. The sequencer circuit 40
Generates an L level selector control signal 40a at the time of writing data in the memory block (1) 28 and the memory block (2) 34, and at the time of reading data in the memory block (1) 28 and the memory block (2) 34. , H level selector control signal 4
0a is generated.

The address selector (1) 31 has two input terminals 31a and 31b, one output terminal 31c, and a control terminal. The input terminal 31a is connected to the output terminal of the write address generator (1) 29, and the input terminal 31b is connected to the output terminal of the read address generator (1) 30. The output terminal 31c is connected to the address bus (1) 26, and the control terminal is connected to the sequencer circuit 40. A selector control signal 40a is applied to this control terminal from the sequencer circuit 40. When an L-level selector control signal 40a is applied to this control terminal, the output terminal 31c switches to the input terminal 31a side, and the address selector unit (1) 31 outputs the write address from the write address generation unit (1) 29. WA is supplied to the address bus (1) 26. When the H-level selector control signal 40a is applied to the control terminal,
The output terminal 31c is switched to the input terminal 31b side, and the address selector unit (1) 31 is connected to the read address generation unit (1).
Read address RA from address 30 to address bus (1) 2
6. That is, the address selector (1) 31 alternately supplies the write address WA and the read address RA to the memory block (1) 28 via the address bus (1) 26. Thus, the data write position and the data read position in the memory block (1) 28 are alternately designated.

The address selector (2) 37 has two input terminals 37a and 37b, one output terminal 37c, and a control terminal. The input terminal 37a is connected to the output terminal of the write address generator (2) 35, and the input terminal 37b is connected to the output terminal of the read address generator (2) 36. The output terminal 37c is connected to the address bus (2) 32, and the control terminal is connected to the sequencer circuit 40. A selector control signal 40a is applied to this control terminal from the sequencer circuit 40. When an L-level selector control signal 40a is applied to this control terminal, the output terminal 37c switches to the input terminal 37b side, and the address selector section (2) 37 reads the read address from the read address generation section (2) 36. RA is supplied to the address bus (2) 32. When the H-level selector control signal 40a is applied to the control terminal,
The output terminal 37c is switched to the input terminal 37a side, and the address selector (2) 37 is connected to the write address generator (2).
The write address RA from the address 35 is transferred to the address bus (2) 3
2. That is, the address selector (2) 37 alternately supplies the write address WA and the read address RA to the memory block (2) 34 via the address bus (2) 32. Thus, the data write position and the data read position in the memory block (2) 34 are alternately designated.

The write data selector 38 has one input terminal 38a, two output terminals 38b and 38c, and a control terminal. The input end 38a is connected to the variable data delay device 2
5 data input units. The output terminal 38b is connected to the data bus (1) 27, the output terminal 38c is connected to the data bus (2) 33, and the control terminal is connected to the sequencer circuit 4.
Connected to 0. This control terminal has a sequencer circuit 4
From 0, the selector control signal 40a is applied. An L level selector control signal 40 is supplied to this control terminal.
When a is applied, the write data selector 38 switches the input end 38a to the output end 38b side, and the input data D input from the data input section of the variable data delay device 25.
Data bus (1) with _IN as write data for writing
27. As a result, write data is written in the memory block (1) 28 at the position specified by the write address WA. When an H-level selector control signal 40a is applied to the control end of the write data selector 38, the write data selector 38 switches the input end 38a to the output end 38c, and the data input of the variable data delay device 25 The input data D _IN input from the section is transmitted to the data bus (2) 33 as write data for writing. Thereby, the memory block (2)
At 34, write data is written to a position designated by the write address WA.

The read data selector 39 has two input terminals 39a and 39b, one output terminal 39c, and a control terminal. The input terminal 39a is connected to the data bus (1) 27
And the input terminal 39b is connected to the data bus (2) 33. The output terminal 39c of the read data selector unit 39 is connected to the data output unit of the variable data delay device 25, and the control terminal is connected to the sequencer circuit 40. A selector control signal 40a is applied to this control terminal from the sequencer circuit 40. When the L-level selector control signal 40a is applied to this control terminal, the read data selector unit 39 switches the output terminal 39c to the input terminal 39b side, and sets the position specified by the read address RA in the memory block (2) 34. Is transmitted to the data output section of the variable data delay device 25 via the data bus (2) 33. The read data selector 39
When the H-level selector control signal 40a is applied to the control end of the read data selector 39, the read data selector 39
Is switched to the input terminal 39a side, and the memory block (1) 2
8, the read data for reading is transferred from the position specified by the read address RA to the data bus (1) 27.
To the data output unit of the variable data delay device 25 via the.

As described above, the variable data delay device 25
Writing of input data in the memory block (1) 28 and reading of data in the memory block (2) 34 and reading of data in the memory block (1) 28 and writing of input data in the memory block (2) 34 alternately. By doing so, the input data is output after being delayed by a predetermined time.

Next, the operation of the variable data delay device 25 according to the present embodiment will be described.

In the variable data delay device 25, the CPU
15 supplies the reference signal 15h to the sequencer circuit 40, and applies the address setting signals 15d and 15e to the write address generator (1) 29 and the read address generator (1).
30 and the address setting signals 15f and 15g to the write address generator (2) 35 and the read address generator (2) 36. The sequencer circuit 40 generates a selector control signal 40a that switches between an H level and an L level at a predetermined cycle based on the reference signal 15h, and generates an address selector (1) 31, an address selector (2) 3
7, the write data selector 38 and the read data selector 39. Further, the sequencer circuit 40
Memory block (1) 28 based on reference signal 15h
And a memory control signal 40b for controlling write and read operations in the memory block (2) 34,
40c are generated and supplied to the memory block (1) 28 and the memory block (2) 34, respectively.

The write address generating section (1) 29 and the read address generating section (1) 30
When 5d and 15e are given, respectively, the write address WA and the read address RA have a predetermined difference value, and the write address WA and the read address RA are generated so that the input data is read in the order of writing. These write address WA and read address RA are output to the address selector (1) 31, respectively.

The write address generating section (2) 35 and the read address generating section (2) 36
When 5f and 15g are given, respectively, the write address WA and the read address RA have a predetermined difference value, and the write address WA and the read address RA are generated so that the input data is read in the order of writing. These write address WA and read address RA are output to the address selector (2) 37, respectively.

When writing input data to the memory block (1) 28 and reading data from the memory block (2) 34, the sequencer circuit 23 sends the L-level selector control signal 40a to the address selector (1) 3.
1, an address selector (2) 37, a write data selector 38 and a read data selector 39. In the address selector unit (1) 31 to which the L-level selector control signal 40a is applied, the output terminal 31c is switched to the input terminal 31a side to selectively output the write address WA to the address bus (1) 26. As a result, the write address WA is supplied to the memory block (1) 28, and the write position in the memory block (1) 28 is specified. On the other hand, the L-level selector control signal 40a
The address selector section (2) 37 to which is supplied the output terminal 37c is switched to the input terminal 37b side to selectively output the read address RA to the address bus (2) 32. As a result, the read address RA becomes the memory block (2)
The read position is specified in the memory block (2) 34. Further, the write data selector section 38 to which the L-level selector control signal 40a is given
Then, the input terminal 38a is switched to the output terminal 38b side, and the input data D _IN input from the data input section of the variable data delay device 25 is used as write data as the data bus (1) 27.
To communicate. The write data transmitted to the data bus (1) 27 is written in the memory block (1) 28 at a position specified by the write address WA in accordance with the memory control signal 40b. Further, in the read selector unit 39 to which the L-level selector control signal 40a is given, the output terminal 39c is switched to the input terminal 39b, and the read address RA in the memory block (2) 34 is changed.
The read data for reading is read from the position designated by the command according to the memory control signal 40c. This read data is transmitted to the data output unit of the variable data delay device 25 via the data bus (2) 33, and is output as output data D _OUT .

When reading data from the memory block (1) 28 and writing input data to the memory block (2) 34, the sequencer circuit 40 outputs the H-level selector control signal 40a to the address selector section (1) 3.
1, an address selector (2) 37, a write data selector 38 and a read data selector 39. The address selector section (1) 31 to which the H-level selector control signal 40a is supplied switches the output terminal 31c to the input terminal 31b side and selectively outputs the read address RA to the address bus (1) 26. As a result, the read address RA is supplied to the memory block (1) 28, and the read position in the memory block (1) 28 is specified. On the other hand, the H-level selector control signal 40a
Is supplied to the address selector (2) 37, the output terminal 37c is switched to the input terminal 37a side, and the write address WA is selectively output to the address bus (2) 32. As a result, the write address WA becomes the memory block (2)
The write position in the memory block (2) 34 is designated. Further, the write data selector unit 38 to which the selector control signal 40a at the H level is given.
Then, the input terminal 38a is switched to the output terminal 38c side, and the input data D _IN input from the data input section of the variable data delay device 25 is used as write data as the data bus (2) 33.
To communicate. The write data transmitted to the data bus (2) 33 is written in the memory block (2) 34 at the position specified by the write address WA in accordance with the memory control signal 40c. Further, the read selector unit 39 to which the selector control signal 40a at H level is given.
Then, the output terminal 39c is switched to the input terminal 39a side, and read data for reading is read from the position specified by the read address RA in the memory block (1) 28 in accordance with the memory control signal 40b. This read data is transmitted to the data output unit of the variable data delay device 25 via the data bus (1) 27, and is output as output data D _OUT .

Next, an example of a specific operation of the variable data delay device 25 according to the present embodiment will be described with reference to the timing chart of FIG.

FIG. 5A shows the reference signal 15h.
5B shows a selector control signal 40a, and FIG. 5C shows an address signal on the address bus (1) 26.
(D) shows an address signal on the address bus (2) 32. 5E shows a data signal on the data bus (1) 27, and FIG. 5F shows a data signal on the data bus (2) 3.
3 shows the data signal above.

As shown in FIGS. 5A to 5F, in this example, the selector control signal 23a is a signal that switches between the H level and the L level every cycle of the reference signal 15c. During the period when the selector control signal 40a is at the L level, the write address WA is selectively output to the address bus (1) 26 by the address selector unit 31, and the write address WA is stored in the memory block (1) 2
8 is supplied. In this example, the write address WA increases in the order of n, n + 1, n + 2,. Thus, the data write position in the memory block (1) 28 is specified. The input data D _IN from the data input unit of the variable data delay device 25 is output to the data bus (1) 27 as write data WD. In this example, it is assumed that the write data WD changes as W0, W1, W2,. However, since the write data WD is alternately output to the data bus (1) 27 and the data bus (2) 33 by the write data selector 38, the data bus (1)
27, the write data WD is W0, W2, W4,.
・ It changes. In the memory block (1) 28, the write data W0 is written into the address n according to the memory control signal 40b, and the write data W2 is written into the address n +
1 so that the write data WD
Is written to the position specified by the write address WA.

On the other hand, the read address RA is selectively output to the address bus (2) 32 by the address selector 37, and the read address RA is supplied to the memory block (2) 34. In this example, the read address RA is k-1, k, k + 1, with the initial value being k-1.
, And so on. This allows
The data reading position in the memory block (2) 34 is specified. Further, data is output to the data bus (2) 33 as read data RD from the position specified by the read address RA in the memory block (2) 34. In this example, the read data RD is R
0, R2, R4,... At this time, in the memory block (2) 34, the memory control signal 4
0c, the read data R0 is at the address k−1
The read data RD is sequentially read from the position specified by the read address RA, such that the read data R2 is read from the address k.

During the period in which the selector control signal 40a is at the H level, the read address RA is selectively output to the address bus (1) 26 by the address selector unit 31, and the read address RA is stored in the memory block (1). 1) Supplied to 28. In this example, the read address RA is k, k + 1, k + 2,.
・ Increase in order. As a result, the data read position in the memory block (1) 28 is specified. Data is output to the data bus (1) 27 as read data RD from the position specified by the read address RA in the memory block (1) 28. In this example, the read data RD is R1,
R3, R5,... At this time,
In the memory block (1) 28, the memory control signal 40b
, The read data R1 is read from the address k and the read data R3 is read from the address k + 1, so that the read data RD is sequentially read from the position specified by the read address RA.

On the other hand, the data bus (2) 33 has input data D _IN from the data input section of the variable data delay device 25.
Is output as the write data WD. In this example, the write data WD changes to W1, W3, W5,. In the memory block (2) 34, the memory control signal 4
According to 0c, the write data W1 is written to the address n and the write data W3 is written to the address n + 1, so that the write data WD is sequentially written to the position specified by the write address WA.

Thus, the variable data delay device 25
Then, according to the selector control signal 40a output from the sequencer circuit 40, the write operation of the memory block (1) 28 and the read operation of the memory block (2) 34, the read operation of the memory block (1) 28, and the memory block (2) ) 34 are alternately performed. The variable data delay device 25 can arbitrarily set the time from writing to reading of the same data by setting the initial value of the write address WA and the initial value of the read address RA. In this setting, the difference between the write address WA generated by the write address generator (1) 29 and the read address RA generated by the read address generator (1) 30 and the write address generator (2) 35, the write address WA and read address generator (2) 3
6 so that the value of the difference between the read addresses RA is the same.

In this setting, the initial values of the write address WA generated by the write address generator (1) 29 and the write address WA generated by the write address generator (2) 35 are set to the same value. Read address R generated by read address generator (1) 30
If the initial value of A and the read address RA generated by the read address generator (2) 36 are set to the same value, the variable data delay device 25 can compare with the first embodiment even at the same frequency of the reference signal 15h. Data can be delayed at twice the transfer rate. For example, the initial values of the write address WA generated by the write address generator (1) 29 and the read address RA generated by the read address generator (1) 30 are set to n = 2 and k = 0, respectively. The initial values of the write address WA generated by the write address generation section (2) 35 and the read address RA generated by the read address generation section (2) 36 are set to n = 2 and k = 0, respectively, and are variable. As shown in FIG. 5 (g), input data D0, D1, D2, D3,... Are input from the input section of the data delay device 25.
Then, as shown in FIG. 5H, the data D0, D0 are delayed at a timing delayed by 2.5 cycles of the selector control signal 40a.
D1, D2, D3,... Are continuously output as output data.

In the variable data delay device 25, FIG.
As can be seen by comparing (g) and (h) with FIGS. 2 (e) and (f), the reference signal 15c of the variable data delay device 1
Even with the reference signal 15h having the same frequency as the above, input data can be delayed and output at twice the transfer rate.

In the example shown in the figure, the initial values of the write address in the memory block (1) 28 and the write address in the memory block (2) 34 are set to the same value, and the read address and the memory in the memory block (1) 28 are set to the same value. Although the initial value of the read address in the block (2) 34 is set to the same value, this is not always necessary, and the difference between the write address and the read address in the memory block (1) 28 and the memory block (2) 3
It is sufficient that the difference between the write address and the read address in 4 is equal.

As described above, according to the present embodiment, C
The PU 15 generates the write address WA and the read address RA so that the write address WA and the read address RA have a predetermined difference and the data is read in the order in which the data was written. Write and memory block (2)
34, the reading of data in the memory block (1) 28 and the writing of input data in the memory block (2) 34 are alternately performed, and the writing of input data and the memory block in the memory block (1) 28 are performed. (2) The data reading in 34 is performed simultaneously, and the memory block (1)
Reading of data and memory block (2) at 28
Since the writing of the input data at 34 is performed at the same time, the input data can be accurately delayed for an arbitrary time, and the input data can be delayed and output at a higher transfer speed.

The present invention is not limited to the above embodiments. For example, the present invention is not limited to the digital data recording / reproducing system shown in FIG. 3, but requires an arbitrary data delay amount. It can be applied to various systems.

[0067]

As described above, according to the variable data delay device of the first aspect, the difference between the write address and the read address has a predetermined value, and the data is written so that the data is read out in the order of writing. By generating an address and a read address, selectively supplying these addresses to the storage means, and causing the storage means to write input data and read data,
Since the input data is output after being delayed by an arbitrary time, there is an effect that the data can be accurately delayed by an arbitrary time by setting the write address and the read address.

According to the variable data delay device of the present invention, the difference between the write address and the read address has a predetermined value, and the write address and the read address are generated so that the data is read in the order of writing. Then, writing of input data in the first storage means and reading of data in the second storage means, and reading of data in the first storage means and writing of input data in the second storage means are alternately performed. Thereby, the writing of the input data in the first storage means and the reading of the data in the second storage means are simultaneously performed, and the reading of the data in the first storage means and the writing of the input data in the second storage means are performed. Is performed at the same time, so that the input data can be It is possible to delay ku,
There is an effect that input data can be delayed and output at a higher transfer rate.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a variable data delay device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram illustrating an example of an operation of the variable data delay device according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a digital data recording / reproducing system using the variable data delay device according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a variable data delay device according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram illustrating an example of an operation of a variable data delay device according to a second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Variable data delay device, 12 ... Variable data delay part, 1
5 CPU, 16 address bus, 17 data bus,
18 memory block 19 write address generator
20: read address generator, 21: address selector, 22: data selector, 23: sequencer circuit.

Claims (2)

[Claims] 1. A memory for recording data by specifying a write and read position by an address, a write address generator for generating a write address in the memory, and a read for generating a read address in the memory. Address generating means, generating a write address and a read address in the write address generating means and the read address generating means so that the difference between the write address and the read address has a predetermined value, and the data is read in the order in which the data was written; A write / read control unit for selectively supplying these addresses to the storage unit and causing the storage unit to write input data and read data, thereby delaying input data by an arbitrary time and outputting the data; To A variable data delay device, comprising: 2. A first storage unit in which write and read positions are specified by an address; a first write address generation unit that generates a write address in the first storage unit; First read address generation means for generating a read address; second storage means for specifying a write / read position by an address; second write address generation means for generating a write address in the second storage means A second read address generating means for generating a read address in the second storage means; and a second read address generating means for generating a read address, wherein a difference between a write address and a read address has a predetermined value, and the data is read in the order of writing. 1 write address generation means, 1st read address generation Generating an address for each of the generating means, the second write address generating means and the second read address generating means, and selectively supplying these addresses to the first storage means and the second storage means; Writing input data in the first storage means and reading data in the second storage means;
Writing and reading control means for delaying the input data by a predetermined time and outputting the data by alternately performing the reading of data in the storage means and the writing of input data in the second storage means. Characteristic variable data delay device.