JPH0778416A - Digital audio interface circuit and recording and reproducing device - Google Patents

Abstract

PURPOSE:To obtain a simply structured DAI circuit and a simply structured recording and reproducing device equipped with such circuit by performing a jitter absorbing function and an SPMC function by means of a common RAM and RAM control device. CONSTITUTION:A DIR clock is reproduced from an inputted DA receiving signal by a DA receiving circuit 5A, and this clock and the DIR signal are supplied to a DAI circuit 1. A crystal clock is imparted to the circuit 1 from an MD signal processing circuit 3, and a jitter contained in the input data is absorbed in the circuit 1 and transmitted to the circuit 3. Based on this signal, a data recording is carried out on MD2 by the circuit 3. The circuit 3 is internally provided with a jitter absorbing circuit containing a small capacity RAM, and the reproducing signal and the crystal clock are imparted to the circuit 1 in the case of reproducing data from the MD. After a process to prevent sound skipping is performed in the circuit 1, the signal is imparted to a DA transmitting circuit 6A and a DA converter 6B. The reproducing signal is outputted from the converter 6B as analog data or from the circuit 6A as digital data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital audio interface circuit and a recording / reproducing apparatus, and more particularly to a jitter absorbing function for absorbing jitter generated in digital audio data and a skipping sound caused by a shock in a mini disk player or the like. The present invention relates to a digital audio interface circuit that also has a shock-proof memory control function to suppress it, and a recording / reproducing apparatus including the same.

[0002]

2. Description of the Related Art When transferring digital audio data, a format of a digital audio interface (hereinafter referred to as DAI) is adopted. Generally, in DAI, jitter occurs in digital data due to wiring or the like between the transmitting side and the receiving side. Since jitter affects the quality of digital audio data, DA
The I circuit employs a jitter absorption circuit that removes or absorbs this.

The DAI circuit is employed in a recording / reproducing apparatus such as a mini disk player for recording / reproducing digital audio data to / from a mini disk, and functions as a signal transmission circuit thereof.
In a mini disc (hereinafter referred to as MD) or the like, for example, when a player receives an impact, the pickup may be separated from its original position due to the impact. In such a case, skipping occurs in the reproduced data and good audio data cannot be obtained. Therefore, in the DAI circuit adopted in the MD player or the like, a shock proof memory control circuit (SPMC circuit) for suppressing skipping is provided. ) Is included in the circuit. The SPMC circuit employs a method in which data read from an MD or the like is temporarily stored in a large capacity RAM, and the stored data is sequentially read from the RAM and transmitted.

FIG. 4 shows the above jitter absorbing circuit and SPM.
An example of a mini disc player including a conventional DAI circuit including a C circuit is shown. Either an analog signal shown as an audio signal or a digital signal shown as a digital audio data (DAD) reception signal is input to the input section of the player, and an audio signal is input to the output section of the player. Either or both of the analog signal shown as and the digital signal shown as the DAD received signal are output.

DAD receiving circuit 41 for receiving the DAD signal
A PLL circuit (not shown) is included therein, and when recording digital audio data, a DAI clock for reading the received DAD signal is used as a PLL.
Playback is performed by the circuit to read digital audio data. DIR reproduced by the DAD receiving circuit 41
The signal and the DIR clock are input to the jitter absorbing circuit 42. RA for jitter absorption in the jitter absorption circuit 42
M43 is connected, and the output of the jitter absorbing circuit 42 is recorded in the MD2 via the MD signal processing circuit 3.

At the time of reproducing the data recorded in the MD, M
The signal read by the pickup from D2 and reproduced by the MD signal processing circuit 3 is sent to the SPMC circuit 45.
The SPMC circuit 45 once writes data in the attached SPMC RAM 46, and sequentially reads the data after a predetermined time. With this configuration, even when the pickup is separated from the disk due to a shock, the data is read from the MD again by using the time difference between the data writing and the data reading to the SPMC RAM 46 and the normal data is read as the SPMC RAM4.
Write to 6. In this way, skipping included in the read reproduction output, that is, the DAD transmission signal or the audio signal is suppressed.

FIG. 5 shows an example of the jitter absorbing circuit 42 of FIG. 4 together with the RAM 43. In FIG. 5, the jitter absorbing circuit includes a RAM interface 50 and a CPU.
It basically comprises an interface 51, a serial / parallel conversion circuit 52, a parallel / serial conversion circuit 53, a write address register 54, a read address register 55, adders 56 and 57, an address comparison circuit 58, and a timing generator 59. The input audio data is temporarily stored in the jitter absorbing RAM 43 under the control of the CPU.

The write address register 54 is the RAM 4
3, and the read address register 55 stores the read address for the RAM 43.
From these respective registers 54 and 55, write and read addresses are transferred to the RAM via the RAM interface 50.
43. Input data, which is a DIR signal, is sequentially written to the address of the RAM 43 designated by the write address register 54 via the serial / parallel conversion circuit 52, and from the address of the RAM 43 designated by the read address register 55, The written data is read. The read data is
It is given as an MD recording signal to the MD signal processing circuit via the parallel / serial conversion circuit 53.

Each register 54, 55 is initialized by a CPU signal via the CPU interface 51,
From the initial state in which addresses having a predetermined offset are stored between the two, the outputs of the adders 56 and 57 attached to the respective addresses are sequentially given, and the addresses are sequentially incremented. The operation timing of each of the registers 54 and 55 is controlled by a timing generator 59. When there is a difference in the cycle of the write and read operation timings, for example, when the write timing advances with respect to the read timing, the jitter is absorbed until the RAM overflows. On the contrary, when the write timing is delayed from the read timing, the jitter is absorbed until the addresses of both registers match.
The address comparison circuit monitors that both addresses keep a predetermined offset, and when they are out of the predetermined offset range, temporarily controls the operation speed of the write address register 54, or By specifying the address separately, both registers 54,
The address of 55 is controlled to operate within a predetermined offset range.

The timing generator 59 is a circuit for generating a timing signal necessary for the entire jitter absorption circuit.
An accurate clock with no variation is required for the read timing for reading data from the RAM, and the so-called crystal clock generated by the crystal oscillation circuit of the MD signal processing circuit is used for reading from the timing generator 59. The timing is supplied to the reading unit from the RAM 43 including the read address register 55.
Further, in the writing section to the RAM 43 including the write address register 54, the timing generator 59 is input.
The DIR clock reproduced by the PLL circuit of the DA receiving circuit is supplied.

FIG. 6 shows an example of the structure of the conventional SPMC circuit 45 shown in FIG. 4 together with the RAM 46. This SPMC circuit has the same configuration as the jitter absorption circuit except that it does not have an address comparison circuit.
Small-capacity RAM for signal processing circuit to absorb jitter
It is adopted when having. The MD signal processing circuit having the jitter absorbing RAM generates the crystal clock by the crystal oscillation circuit, and the crystal clock of the MD signal processing circuit is input to the timing generator 69 of the SPMC circuit as the write timing. It In this case, the MD reproduction signal read from the MD and input to the SPMC circuit is also synchronized with this crystal clock, and the write address register 64 and the read address register 65 operate in the same cycle. Therefore, a comparison circuit for comparing both addresses is unnecessary.

FIG. 7 shows another configuration example of the SPMC circuit. In this SPMC circuit, the MD signal processing circuit is MD
It is used when there is no small capacity RAM that absorbs the jitter in the read signal. M without jitter absorption function
The D signal processing circuit reproduces the PLL clock from the MD read data by the internal PLL circuit, and both the PLL clock and the crystal clock are input to the timing generator 79 of the SPMC circuit. Each clock is supplied from the timing generator 79 to the write address register 74 and the read address register 75, respectively. This SP
In the case of the MC circuit, the address comparison circuit 78 for comparing the addresses of the write address register 74 and the read address register 75 is required, as in the jitter absorption circuit shown in FIG.

[0013]

In the conventional DAI circuit used for recording / reproducing of MD and the like, two large-capacity RAMs are required for the jitter absorbing circuit and the SPMC circuit. Therefore, there are drawbacks such as an increase in the cost of the RAM, a complicated circuit for accessing the RAM, and a large space for realizing the DAI circuit.

In view of the above, the present invention overcomes the drawbacks of the conventional DAI circuit adopted in the recording / reproducing apparatus for recording / reproducing to / from the MD and the like, and has a simple structure.
It is an object of the present invention to provide an AI circuit and a recording / reproducing apparatus having a simple structure including the AI circuit.

[0015]

In order to achieve the above object, the digital audio interface circuit of the present invention stores a write address to a RAM, and the address is written at a first timing every write from a set initial value. A write unit including a write address register that advances, a write data transmission unit that sequentially transmits write data to the RAM, and a read address from the RAM are stored, and at a second timing for each read from the set initial value. A read unit including a read address register for advancing an address, a read data transfer unit for sequentially transferring read data from the RAM, an address comparison circuit for monitoring the address offset of the write address register and the read address register, Based on the output of the address comparison circuit, the writing In a digital audio interface circuit including a register control unit that controls an address offset of a read address register and a read address register within a predetermined range, a mode setting unit that sets an operation mode to a first mode or a second mode, and Based on the setting of the mode setting unit, an input switching unit that switches the input data to the write data transmitting unit to the first input or the second input, and in conjunction with the switching of the input switching unit, from the read data transmitting unit. An output switching unit that switches the output data to the first output or the second output is provided.

In the recording / reproducing apparatus of the present invention, the recording signal obtained based on the audio signal input to the first input is output from the first output to the recording medium, and the recording mode is set to the first recording medium. In a recording / reproducing apparatus operable in a reproduction mode in which an audio signal reproduced based on a signal input to two inputs is output from a second output, a RAM having a predetermined capacity and a write address to the RAM Is stored, and an input is connected to the first input and the second input, and a write address register in which the address advances at the first timing every writing from the set initial value, and either the first input or the second input An input selector for selecting and outputting the R, a data writing unit for writing the output of the input selector to the RAM based on the address of the write address register, and the R Stored in the read address from the M,
A read address register whose address advances from the set initial value at the second timing every read, a data read unit for reading data from the RAM based on the address of the read address register, and a read by the data read unit An output selector that selects and outputs the selected data to either the first output or the second output corresponding to the selection of the first input or the second input, and the write address register and the read address register. An address comparison circuit for monitoring the offset of the address value, and a register control unit for controlling the address offset of the write address register and the read address register within a predetermined range based on the output of the address comparison circuit. And

[0017]

In the digital audio interface circuit of the present invention, the jitter absorbing function and the SPMC function are
Since the common RAM and the write unit and the read unit that form the control unit thereof are used, the functions of both are only one set of RAM and R.
This is achieved by the AM control unit, and the configuration of the digital audio interface circuit is simplified.

Further, in the recording / reproducing apparatus of the present invention, by adopting the digital audio interface circuit having the above-mentioned operation, the jitter absorbing RAM and the SPMC RAM can be shared, and the digital audio interface circuit having a simple structure. Combined with the adoption of, the whole circuit configuration is simplified.

[0019]

The present invention will be further described with reference to the drawings. Figure 2
FIG. 3 shows the configuration of an MD recording / reproducing apparatus including a digital audio interface circuit according to an embodiment of the present invention. In the figure, this recording / reproducing apparatus comprises a DAI circuit 1 which constitutes an embodiment of the present invention, a first signal output section and a second signal input section, and is provided between the DAI circuit 1 and MD2. MD signal processing circuit 3 for exchanging signals, large-capacity RAM 4 for DAI circuit 1, DA receiving circuit 5A and A / D converter 5B forming first signal input section 5, and second signal output section DA transmission circuit 6A and D / A converter 6B which form 6
The digital audio data is recorded / reproduced to / from the MD2 by operating in the recording mode or the reproduction mode.

When recording audio data on the MD2, an input signal input for recording is constituted as either an analog audio signal or digital audio data. In the case of an analog audio signal, A
The signal is converted into a digital signal by the / D converter 5B, and M
It is given to the DAI circuit 1 as a recording signal for D. Further, in the case of digital audio data, it is received by the DA receiving circuit 5A, and is similarly converted into D signal as DIR signal.
It is given to the AI circuit 1.

The DA receiving circuit 5A internally includes a PLL circuit (not shown), reproduces a DIR clock from a DA receiving signal input as digital data, and supplies this clock and the DIR signal to the DAI circuit 1. DAI
The crystal clock is further supplied to the circuit 1 from the MD signal processing circuit 3, and the DAI circuit 1 absorbs the jitter included in the input data and transmits it to the MD signal processing circuit 3. Based on this signal, the MD signal processing circuit 3 outputs M
Data recording is performed on D2.

The MD signal processing circuit 3 is internally provided with a jitter absorbing circuit including a small capacity RAM for absorbing jitter, and when reproducing data recorded in MD, M
The reproduction signal read from D and obtained by absorbing the jitter and the crystal clock used to obtain the reproduction signal are applied to the DAI circuit 1. The DAI circuit 1 performs signal processing for preventing skipping that occurs in the reproduced signal, and then performs D
It is applied to the A transmission circuit 6A and the D / A converter 6B. The reproduced signal is output from the D / A converter 6B as an analog audio signal or is supplied from the DA transmission circuit 6A as digital audio data to another signal processing circuit.

FIG. 1 shows the configuration of the DAI circuit 1 shown in FIG. 2 together with the RAM 4. This DAI circuit includes a RAM interface 31, a CPU interface 32, and an R
An AM write unit 10, a RAM read unit 20, an address comparison circuit (address comparison and control circuit) 33 that monitors and controls the offset between the write address of the write unit 10 and the read address of the read unit 20. It is composed of a timing generator 34 and a timing selector 35. The writing unit 10 includes an input selector 11 that switches input data, and a serial / serial circuit that forms a write data transmitting unit.
The parallel / serial conversion circuit includes a parallel conversion circuit 12, a write address register 13, and a write unit adder 14, and the read unit 20 includes a read address register 21, a read unit adder 22, and a read data transfer unit. Two
3 and an output selector 24.

The address comparison circuit 33 is a circuit for monitoring that the address outputs of the write address register 13 and the read address register 21 have a predetermined offset, and also has a function of keeping the offset of both addresses within a predetermined range. Have. The timing generator 34 controls the write timing for controlling the writing unit 10 and the reading unit 20.
The read timing for controlling the
Alternatively, it is supplied to the reading unit 20.

When the data from the DA receiving circuit 5A (FIG. 2) is recorded on the MD, the writing section 10 is supplied with the DIR clock reproduced by the PLL circuit of the DA receiving circuit, and the reading section 20 is supplied with the MD. The crystal clock for MD signal processing generated by the signal processing circuit is supplied. When reproducing data from the MD, the writing unit 10
The crystal clock of the MD signal processing circuit is supplied to both the read section 20 and the read section 20. Switching of these timings is performed by a timing selector 35 attached to the timing generator 34.

An overflow signal is input to the timing generator 34 from the MD signal processing circuit. This signal is a signal that is output when a small capacity RAM for error correction and jitter absorption provided in the MD signal processing circuit overflows. When this signal is output, writing from the writing unit 10 to the RAM 4 is stopped until the pickup returns to the original position and normal data is input. Although FIG. 1 shows an example in which the overflow signal is independently input from the MD signal processing circuit to the timing generator 34, it may be input via the CPU interface 32.

When the DIR signal and the DIR clock are supplied to the DAI circuit from the DA receiving circuit for recording the digital audio signal, the timing generator 34
Write addresses to the RAM 4 are sequentially generated based on the timing of the DIR clock, and read addresses from the RAM are sequentially generated based on the crystal clock. The address comparison circuit 33 manages the overflow of the RAM 4 that occurs when the jitter of the DIR signal is large. For example, when the operation timing of the write address register 13 is delayed and the addresses of the write address register 13 and the read address register 21 match,
The address comparison circuit 33 transmits the coincidence signal to the MD signal processing circuit and also sends the write address register 13
Temporarily accelerate the operation timing of.

When the operation timing of the write address register 13 advances and the RAM 4 overflows, the address of the write address register is delayed and set. As a result, the offset value between the two registers 13 and 21 is maintained within the predetermined range. In this way, the DAI circuit absorbs the jitter and transfers the data to the M
The data is sent to the D signal processing circuit 3 and data is recorded in the MD 2 via the MD signal processing circuit 3. Instead of the configuration in which the address comparison circuit 33 directly controls the register, for example, the comparison circuit 33 supplies an address match signal to the CPU,
The address value of the register or the operation timing can be controlled by the CPU. In this case, the response speed is slightly lower than that of the above-described example.

When reproducing the data from the MD, both the write address register 13 and the read address register 21 operate at the same timing, so that the default offset is maintained as it is when there is no skip. In addition, when skipping occurs, the overflow signal is
It is supplied from the MD signal processing circuit to the timing generator 34. At this time, the DAI circuit temporarily stops writing to the RAM 4, and then resumes writing after normal data is input. The read address register 21 is irrelevant to the R
Continue reading from AM4. In this way, by utilizing the address offset between both registers, the skipping of the sound generated at the time of impact can be eliminated, and the reproduced data with good accurate timing can be obtained.

FIG. 3 shows a DAI circuit according to the second embodiment of the present invention. The DAI circuit of this embodiment corresponds to both the MD signal processing circuit of the type having the jitter absorbing function described above and the MD signal processing circuit of another type having no jitter absorbing function. In FIG. 3, when the MD signal processing circuit has a jitter absorbing function, the crystal clock of the MD signal processing circuit is selected by the timing selector 35 when reproducing data.

When the MD signal processing circuit does not have the jitter absorbing function, the PLL clock regenerated by the PLL circuit of the MD signal processing circuit is the timing selector 35.
Is selected in, and when playing data from MD, MD
RA data based on the PLL clock of the signal processing circuit
To write to M4 and read data from RAM4,
A crystal clock generated by an MD signal processing circuit or the like is used. As a result, jitter generated by MD rotation fluctuations during data reproduction is also absorbed in the DAI circuit. Further, no matter which clock is selected, it has the same SPMC function as the DAI circuit of FIG.

As described above, in the DAI circuit of the embodiment of the present invention and the DAI circuit of the recording / reproducing apparatus of the embodiment of the present invention, the jitter absorption processing function from the recorded data including the jitter and the reproduced data of MD and the like. The SPMC processing function for eliminating the sound skipping that occurs in the common RAM and RA
By using the hardware including the M control circuit, the configurations of the DAI circuit and the recording / playback apparatus can be simplified. Further, by adopting common hardware, it is possible to simplify the access to the RAM, reduce the number of times of access itself, and thus suppress unnecessary signal emission caused by the access to the RAM, and realize a circuit. The advantage of being able to reduce the space for

Although the present invention has been described based on its preferred embodiments, the present invention is not limited to the configurations of the above embodiments, and various modifications and changes can be made from the above embodiments. is there.

[0034]

As described above, according to the digital audio interface circuit and the recording / reproducing apparatus of the present invention, the common RAM and the RAM control section perform the jitter absorbing function and the SPMC function.
And the structure of the digital audio interface circuit is simplified, and the space for realizing the circuit can be reduced, which is a remarkable effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital audio interface circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a recording / playback apparatus according to an embodiment of the present invention.

FIG. 3 is a block diagram showing the configuration of a digital audio interface circuit according to another embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional recording / playback device.

FIG. 5 is a block diagram showing a configuration of a conventional jitter absorption circuit.

FIG. 6 is a block diagram showing an example of the configuration of a conventional SPMC circuit.

FIG. 7 is a block diagram showing another example of the configuration of a conventional SPMC circuit.

[Explanation of symbols]

 1 Digital Audio Interface Circuit 2 MD (Mini Disc) 3 MD Signal Processing Circuit 4 RAM 5 Input Section 5A DAD Reception Circuit 5B A-D Conversion Circuit 6 Output Section 6A DAD Transmission Circuit 6B D-A Conversion Circuit 10 Writing Section 11 Input Selector 12 Serial / parallel conversion circuit 13 Write address register 14 Adder 20 Read unit 21 Read address register 22 Adder 23 Parallel / serial conversion circuit 24 Output selector 31 RAM interface 32 CPU interface 33 Address comparison circuit 34 Timing generator 35 Timing selector

Claims (4)

[Claims] 1. A write address register which stores a write address to a RAM and which advances an address at a first timing for each write from a set initial value, and a write data transfer unit which sequentially transfers write data to the RAM. And a read address register for accumulating read addresses from the RAM and advancing the address at a second timing every read from a set initial value, and read data transmission for sequentially transmitting read data from the RAM A read unit including a unit, an address comparison circuit that monitors an address offset of the write address register and the read address register, and an address of the write address register and the read address register based on an output of the address comparison circuit. Controls the offset within a specified range. In a digital audio interface circuit including a transistor control unit, a mode setting unit that sets an operation mode to a first mode or a second mode, and input data to the write data transmission unit based on the setting of the mode setting unit. An input switching unit that switches to a first input or a second input, and an output switching unit that switches output data from the read data transmission unit to a first output or a second output in cooperation with switching of the input switching unit. A digital audio interface circuit characterized by the following. 2. The interface circuit for digital audio according to claim 1, further comprising a timing switching unit that switches at least one of the first timing and the second timing based on the setting of the mode setting unit. . 3. A recording mode in which a recording signal obtained based on an audio signal input to the first input is output from the first output to a recording medium, and a signal input to the second input from the recording medium. In a recording / reproducing apparatus operable in a reproduction mode in which an audio signal reproduced by the second output is output from a second output, a RAM having a predetermined capacity and a write address to the RAM are stored, and a preset initial value is set. A write address register whose address advances at a first timing for each writing; and an input selector which is connected to the first input and the second input and which selects and outputs either the first input or the second input. A data writing unit that writes the output of the input selector to the RAM based on the address of the write address register, and stores a read address from the RAM. A read address register whose address advances from the set initial value at every second timing at every read, a data read unit for reading data from the RAM based on the address of the read address register, and a read by the data read unit An output selector for selecting and outputting the output data to either the first output or the second output in response to the selection of the first input or the second input; the write address register and the read address register An address comparison circuit for monitoring the address offset of the write address register and a register control unit for controlling the address offset of the write address register and the read address register within a predetermined range based on the output of the address comparison circuit. Recording / playback device. 4. The recording / reproducing apparatus according to claim 3, further comprising a timing switching unit that switches at least one of the first timing and the second timing based on selection of each mode.