JP3156556B2 - Digital recording and playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital recording / reproducing apparatus for recording and reproducing digital data on a magnetic tape by helical scanning with a rotary head.

[0002]

2. Description of the Related Art In recent years, digital recording / reproducing apparatuses such as home digital VTRs called DVCs have been actively developed. In the digital data processing of such a digital recording / reproducing apparatus, encoding / decoding of an error correction product code is performed. Hereinafter, a conventional digital recording / reproducing apparatus will be described with reference to the drawings.

First, FIG. 4 shows a configuration diagram of one track of audio video data to be recorded and reproduced. This configuration is a DV
In the case of C, when recording and reproducing an NTSC television signal, one frame is divided into ten tracks. In each track, a unit called a sync block composed of a total of 85 bytes of a 77-byte data portion and an 8-byte inner code parity portion in one track forms an error correction inner code, and audio data is composed of 9 sync blocks. And a sync code of 5 sync blocks constitutes one product code. The video data is composed of 138 sync block data portions and 11 sync block outer code parity portions, for a total of 149 sync blocks. One product code is composed of blocks and is recorded and reproduced in the order of audio data to video data.

FIG. 5 shows a configuration diagram of a conventional digital recording / reproducing apparatus. In FIG. 5, the main memory unit 5
Reference numeral 1 denotes a main memory, which is an SRAM 511 for storing one frame of data and storing one address and one byte;
Main memory control means 512 for controlling RAM 511
When there is an access request, data writing and reading are performed.

The first data block processing means 52 includes a signal recording processing section 521 for converting an analog audio video signal into a sync block, and a signal reproduction processing section 522 for converting a sync block into an analog audio video signal.
During a recording operation, an analog audio video signal is input, and a 77-byte sync block is output to the main memory unit 51 together with an access request. During a reproduction operation, an access request is output to the main memory unit 51. A 77-byte sync block is input from the section 51 to output an analog audio video signal.

The second data block processing means 53 includes an inner code parity adding section 531 for adding inner code parity to a sync block to be recorded, and an inner code error correction process for performing inner code error correction processing on a reproduced sync block. During a recording operation, an access request is output to the main memory unit 51, a 77-byte sync block is input from the main memory unit 51, and an 85-byte sync block to which an inner code parity is added is output. During a reproducing operation, an 85-byte sync block is input, and a 77-byte sync block after inner code error correction processing is output to the main memory unit 51 together with an access request.

[0007] The modulation and demodulation means 54 includes a modulation section 541 for modulating a sync block into a recording signal to be recorded on a magnetic tape,
And a demodulation unit 542 for demodulating a reproduction signal reproduced from the magnetic tape into a sync block. At the time of a recording operation, an 85-byte sync block is input from the second data block processing unit 53 to convert the modulated recording signal. During the playback operation, a playback signal is input, and the 85-byte demodulated sync block is output to the second data block processing unit 5.
Output to 3.

An outer code processing means 55 adds an outer code parity to the data to be recorded.
51, and an outer code error correction processing unit 552 for performing outer code error correction processing on reproduced data. During a recording operation, an access request is output to the main memory unit 51, and an outer code parity is added from the main memory unit 51. Inputting data necessary for processing, outputting outer code parity together with an access request to the main memory unit 51, and outputting an access request to the main memory unit 51 during a reproducing operation;
The data necessary for the outer code error correction processing and the outer code parity are input from the main memory unit 51, and the data after the outer code error correction processing is output to the main memory unit 51 together with the access request.

FIG. 6 shows a main memory access timing chart during a recording operation in a conventional digital recording / reproducing apparatus. In FIG. 6, the transfer of the sync block is 1 byte 9 MHz, and the access to the SRAM 511 is the transfer of 1 byte 27 MHz. The SRAM access window set by the main memory control means 512 is 27 MHz1.
The window A is dedicated to access to the first data block processing means 52, the window B is dedicated to access to the second data block processing means 53, and the window C is dedicated to access to the outer code processing unit 54. And the access request signal of the allocated access of each window is H
Access to the SRAM 511 at the time of the level.

FIG. 7 shows a main memory access timing chart during a reproducing operation in a conventional digital recording / reproducing apparatus. In FIG. 7, the transfer of the sync block is 1 byte 9 MHz, and the access to the SRAM 511 is 1 byte 27 MHz. The SRAM access window set by the main memory control means 512 is the same as in FIG.

The operation of the conventional example in the digital recording / reproducing apparatus configured as shown in FIG.
This will be described below with reference to FIGS. During the recording operation,
First, the signal recording processing unit 521 performs processing such as A / D conversion, shuffling, discrete cosine conversion, and variable length coding on the input analog audio video signal,
The main memory unit 51 includes an access request signal and a sync block composed of a 77-byte data portion as one unit.
Output to The write access of the sync block to the SRAM 511 is performed one byte at a time in the SRAM access window A, as shown in FIG.

The outer code parity adding section 551
Outputs an access request to the main memory unit 51, and inputs data necessary for the outer code parity addition processing from the main memory unit 51. Data read access from the SRAM 511 is performed one byte at a time in the SRAM access window C, as shown by way of example in FIG. 6B, byte 8 of video data.

The outer code parity adding section 551
Performs an outer code parity adding process and outputs the outer code parity to the main memory unit 51 together with an access request. The write access of the outer code parity to the SRAM 511 is performed by the SRAM access window C as shown in FIG.
It is done byte by byte.

Then, an inner code parity adding section 531
Outputs an access request to the main memory, and
The byte sync block is input from the main memory unit 51, and an inner code parity of 8 bytes is added thereto, and the sync block is output to the modulation unit 541 as a sync block of 85 bytes in total.
The read access of the sync block from the SRAM 511 is performed one byte at a time in the SRAM access window B, as shown in FIG.

Then, the modulator 541 modulates the sync block input from the inner code parity adder 531 into a recording signal that can be recorded on a magnetic tape, and outputs the signal. At the time of the reproducing operation, first, the demodulating section 542 inputs the reproduced signal reproduced from the magnetic tape, demodulates it into a sync block composed of a total of 85 bytes of a 77-byte data section and an 8-byte parity section, and performs inner code error. Output to the correction processing unit 532.

Then, the inner code error correction processing section 532
The 85-byte sync block output from the demodulation unit 542 is input, an inner code error correction process is performed, and a 77-byte sync block after the inner code error correction process is output to the main memory unit 51 together with an access request signal. The write access to the SRAM 511 of the sync block is shown in FIG.
As shown in the example of the sync block 3 of the video data in FIG.

Then, the outer code error correction processing unit 552
An access request is output to the main memory unit 51, and data and outer code parity required for the outer code error correction processing are input from the main memory unit 51. Reading access of data and outer code parity from the SRAM 511 is performed one byte at a time in the SRAM access window C, as shown by way of example in FIG. 7B, byte 8 of video data.

Then, the outer code error correction processing unit 552
The outer code error correction processing is performed, and the data after the outer code error correction processing is output to the main memory unit 51 together with the access request. SRAM 51 of data after outer code error correction processing
Write access to 1 is performed one byte at a time in the SRAM access window C, as shown by way of example in FIG. 7C, byte 8 of the video data.

Then, the signal reproduction processing unit 522 outputs an access request to the main memory unit 51 and inputs a 77-byte sync block from the main memory unit 51.
Processing such as decoding of a variable length code, inverse discrete cosine transform, deshuffling, and D / A conversion is performed, and output as an analog audio video signal. SRAM5 of sync block
As shown in FIG. 7 (d), the read access from the sync block 3 of the video data is taken as an example.
This operation is performed one byte at a time in the SRAM access window A.

[0020]

However, in the above-mentioned conventional configuration, since the SRAM is used as the main memory, there is a problem that the mounting area is increased and the cost is increased. Therefore, it is desired to use a DRAM having a small mounting area and low cost as a main memory. A DRAM is generally slower than an SRAM in access, has a two-dimensional address space, and can access one data only by accessing a column address after accessing a row address, and is therefore called a page mode operation. Unless the object is used, the number of accesses increases, and as a result, the access is further slowed down. Page mode operation is an operation in which data on the same row address can be accessed simply by specifying the column address once the row address has been specified. Since the number of accesses can be reduced, fast access is possible. Becomes However, in the above-described conventional configuration, a very high access speed is required, and the page mode operation cannot be used because access in three directions is switched for each address access of the main memory. Therefore, it is impossible to use the DRAM as the main memory with the above-mentioned conventional configuration.

In the above-mentioned conventional configuration, for example, when an insert operation of audio reproduction video recording is to be performed, an audio reproduction sync block is written to the main memory because it is delayed by demodulation and inner code error correction processing. It is necessary to perform reading from the main memory early because the video recording sync block is delayed due to the addition of the inner code parity and the modulation process. As a result, the second data block processing means and the main memory unit Since the overlap occurs in the sync block access, there is a problem that a failure occurs in the main memory access and a normal insert operation cannot be performed.

The present invention solves the above-mentioned conventional problems. A DRAM having a small mounting area and a low cost can be used as a main memory. An object of the present invention is to provide a recording and reproducing device.

[0023]

In order to achieve this object, a digital recording / reproducing apparatus according to the present invention comprises a first adjustment memory for temporarily storing a data block accessed by a first data block processing means with a main memory. And the second
A second adjustment memory comprising two independent memories, a write adjustment memory and a read adjustment memory, for temporarily storing a data block to be accessed by the data block processing means, and a first data block processing means And a main memory control means for receiving an access request from the second data block processing means and an access request from the second data block processing means and accessing the data block in the main memory. Is set as an access window, and if the access window is recognized in response to the input access request, the first data block processing means and the second data block processing means Issue access approval to those who have access requests Then, the data block is accessed to the main memory, and the M-th data (0 <M <N: M is an integer, N is an integer and the type of independently recorded and reproduced data existing in one track) is reproduced. In the operation where the (M + 1) th data is recorded, the transfer of the reproduced data block of the (M) th data is delayed by the demodulation and the inner code error correction processing, and the transfer of the recorded data block of the (M + 1) th data is added with the inner code parity. In addition, the second adjustment memory has a configuration in which the second adjustment memory has a data block storage capacity equal to or more than the overlap at the time of accessing the main memory resulting from the delay due to the modulation processing.

[0024]

According to the present invention, when the first data block processing means writes a data block to the main memory, the data block is stored in the first adjustment memory and an access request is issued to the main memory control means. Then, if the main memory control means recognizes the access window of the data block and gives access approval, the data block is written to the main memory by continuous access. When the first data block processing means reads out the data block, it issues an access request to the main memory control means. If the main memory control means recognizes the access window of the data block and issues an access approval, the data block is read. Is read from the main memory by continuous access, and a data block is stored in the first adjustment memory. The same applies to the case where the second data block processing means accesses the data block with the main memory. With this operation, the data block can be continuously accessed to the main memory, the data block can be accessed to the main memory with a small number of accesses using the page mode operation of the DRAM, and the fast access can be performed even when the DRAM is used. Becomes possible.

Further, the present invention has a second
When an overlap occurs in the data block access between the data block processing means and the main memory, the data block is read from the main memory in advance before the overlap occurs, and
The data block to be written to the main memory is stored in the read adjustment memory, or the data block to be written to the main memory is stored in the write adjustment memory, and when the overlap ends, the main memory is accessed. By this operation, even if an overlap occurs, the access of the data block to the main memory can be performed without failure.

[0026]

An embodiment of the present invention will be described below with reference to the drawings. The configuration of one track of audio / video data to be recorded / reproduced is as shown in FIG. FIG. 1 shows a configuration diagram of a digital recording / reproducing apparatus according to an embodiment of the present invention. In FIG.
The main memory unit 51 is a main memory, which stores 1 address and 2 bytes of data for storing 1 frame of data.
It comprises a RAM 513 and a main memory control means 512 for controlling the DRAM 513, and outputs an access acknowledgment (ACK in the figure) for an access request (REQ in the figure) to write and read data.

The first data block processing means 52 includes a signal recording processing section 521 for converting an analog audio video signal into a sync block, and a signal reproduction processing section 522 for converting a sync block into an analog audio video signal.
During the recording operation, an analog audio video signal is input, a 77-byte sync block is output to the first adjustment memory 11 and stored, and an access request is output to the main memory unit 51 so as to approve the access. When the access request is received, the sync block stored in the first adjustment memory 11 is output to the main memory unit 51. During a reproducing operation, an access request is output to the main memory unit 51 in advance. The 77 byte sync block output from
The sync block is input from the first adjustment memory 11 when necessary, and an analog audio video signal is output.

The second data block processing means 53 includes an inner code parity adding section 531 for adding inner code parity to a sync block to be recorded, and an inner code error correction processing for performing inner code error correction processing on a reproduced sync block. During the recording operation, an access request is output to the main memory unit 51 in advance, and if an access approval is received, the 77 output from the main memory unit 51 is output.
Byte sync blocks are stored in the read adjustment memory 121 of the second adjustment memory 12, and when necessary, the sync blocks are read and input from the adjustment memory 121, and an 85-byte sync block to which an inner code parity is added is output. During the reproducing operation, an 85-byte sync block is input, and the 77-byte sync block after the inner code error correction processing is output to the write adjustment memory 122 of the second adjustment memory 12 to be stored, and the access request is stored. The data is output to the main memory unit 51, and when the access approval is received, the sync block stored in the write adjustment memory 122 is output to the main memory unit 51.

The modulator / demodulator 54 modulates a sync block into a recording signal to be recorded on a magnetic tape,
And a demodulation unit 542 for demodulating a reproduction signal reproduced from the magnetic tape into a sync block. At the time of a recording operation, an 85-byte sync block is input from the second data block processing unit 53 to convert the modulated recording signal. During the playback operation, a playback signal is input, and the 85-byte demodulated sync block is output to the second data block processing unit 5.
Output to 3.

The outer code processing means 55 adds an outer code parity to data to be recorded.
51, and an outer code error correction processing unit 552 for performing an outer code error correction process on the reproduced data. During a recording operation, an access request is output to the main memory unit 51. The data required for the outer code parity addition processing output from 51 is input, and then the main memory unit 51 writes the outer code parity into the DRAM 513 of the main memory.
If you output an access request to and receive access approval,
The outer code parity is output to the main memory unit 51, an access request is output to the main memory unit 51 during the reproducing operation, and the data and outer code parity required for the outer code error correction processing are input from the main memory unit 51, and then In order to write the data after the outer code error correction processing to the DRAM 513 of the main memory,
If you output an access request to and receive access approval,
The data after the outer code error correction processing is stored in the main memory 51.
Output to

Here, the second adjustment memory 12 has a storage capacity for a sync block in which the main memory access overlaps during the insert operation of audio reproduction video recording. Next, FIG. 2 is a timing chart of write access of a sync block from the signal recording processing unit 521 to the DRAM 513 during a recording operation in the digital recording / reproducing apparatus according to the embodiment of the present invention. FIG.
, DRAM access is a 2-byte 9 MHz transfer. DRAM access windows are window A, window B, window C
The window A is a sync block access priority with the first data block processing means 52, and continuous access of the sync block using the page mode operation of the DRAM is possible. Any number of clocks are assigned, and if there is an access request from the first data block processing means 52, a sync block access with the first data block processing means 52 is performed. If there is no access request and there is an access request from the second data block processing means 53, a sync block access with the second data block processing means 53 is performed.

Window B is the second data block processing means 53
In the same way as the window A, the number of clocks sufficient to allow continuous access of the sync block using the page mode operation of the DRAM is assigned. The second data block processing means 53
If the access request from the first data block processing unit 52 is not received and the access request from the first data block processing unit 52 is received, the first
The sync block access with the data block processing means 52 is performed. The window C is allocated for data with the outer code processing unit 54 and outer code parity access.

Therefore, if the access request signal from the signal recording processing unit 521 is high when the window A is recognized, an access acknowledgment signal is output to the signal recording processing unit 521 to switch the sync block to the page mode operation. DRA using
Write to M513. Next, FIG. 3 shows the DRA during the recording operation in the digital recording / reproducing apparatus according to the embodiment of the present invention.
FIG. 10 shows a timing diagram of write access of a sync block from M513 to the inner code parity adding section 531. FIG.
, DRAM access is a 2-byte 9 MHz transfer. The configuration of the DRAM access window is the same as in FIG. If the access request signal from the inner code parity adding unit 531 is H when the window B is recognized, an access acknowledgment signal is output to the inner code parity adding unit 531 and
The sink block is set to the DRAM 5 by using the page mode operation.
Read from 13.

In FIGS. 2 and 3, RAS is a timing signal for setting a certain row address R, CAS is a timing signal for setting column addresses C1 to C39, and ADR
S is an address signal input to the DRAM 513, WE is a control signal to the DRAM 513 to enable writing, OE
Is a control signal to the DRAM 513 that can be output.
In the figure, after setting the row address R, the column address C1
14 shows a page mode operation for changing C39.

As described above, the digital recording / reproducing apparatus constructed as shown in FIG.
The operation will be described below with reference to FIG. At the time of the recording operation, first, the signal recording processing unit 521 performs processing such as A / D conversion, shuffling, discrete cosine conversion, and variable length coding on the input analog audio video signal, and a 77-byte data section. A sync block consisting of
The data is output to the first adjustment memory 11 as a unit and stored, and an access request signal is output to the main memory unit 51. The write access to the DRAM 513 of the sync block is performed by outputting an access approval signal to the signal recording processing unit 521 when the DRAM access window A is recognized, as shown in FIG. When the recording processing unit 521 receives the access approval signal, the recording processing unit 521 transfers the sync block stored in the first adjustment memory 11 to the main memory unit 51, and transfers the sync block to the DRAM 513.
Is continuously performed using the page mode operation of the DRAM.

The outer code parity adding section 551
Outputs an access request to the main memory unit 51. If the main memory control unit 512 recognizes the DRAM access window C, the data is read from the DRAM 513, and the data is output to the outer code parity adding unit 551 together with the access approval signal. The outer code parity adding unit 551 includes:
By repeating this access, data necessary for adding the outer code parity is input from the main memory unit 51.

The outer code parity adding section 551
Performs an outer code parity adding process, outputs an access request to the main memory unit 51 to write the outer code parity to the DRAM 513, and if the main memory control unit 512 recognizes the DRAM access window C, outputs an access approval signal to the outer code. When the access code is output to the parity addition unit 551 and the outer code parity addition unit 551 receives the access approval signal, the outer code parity is transferred to the main memory unit 51 and written to the DRAM 513.

Then, the inner code parity adding section 531
However, it outputs an access request to the main memory unit 51 in advance, inputs a 77-byte sync block from the main memory unit 51, stores the input sync block in the readout adjustment memory 121, and reads out the readout adjustment memory when necessary. Read from 121, inner code parity 8
Bytes are added and output to the modulator 541 as a sync block of a total of 85 bytes. Sync block DRAM
The read access from the 513 is performed as shown in FIG. 3 by taking the sync block 3 of the video data as an example.
If the AM access window B is recognized, an access acknowledgment signal is output to the inner code parity adding section 531 and the DRAM 513 is output.
The read access of the sync block from the CPU is continuously performed using the page mode operation of the DRAM. Upon receiving the access approval signal, the inner code parity adding unit 531 reads out the sync block output from the main memory unit 51 and stores it in the adjustment memory 121.

Then, the modulator 541 modulates the sync block input from the inner code parity adder 531 into a recording signal that can be recorded on a magnetic tape, and outputs the signal. At the time of the reproducing operation, first, the demodulating section 542 inputs the reproduced signal reproduced from the magnetic tape, demodulates it into a sync block of 85 bytes in total of a 77-byte data section and an 8-byte parity section, and corrects an inner code error. Output to the processing unit 532.

Then, the inner code error correction processing section 532
An 85-byte sync block output from the demodulation unit 542 is input, an inner code error correction process is performed, a 77-byte sync block after the inner code error correction process is stored in the write adjustment memory 122, and an access request signal is stored. Output to the main memory unit 51. Sync block DRAM
Write access to 513 is similar to that of FIG.
It may be considered that the processing is performed in the AM access window B. That is, if the DRAM access window B is recognized, the access approval signal is output to the inner code error correction processing unit 532, and the inner code error correction processing unit 532 receives the access approval signal and receives the sync block stored in the write adjustment memory 122. Is transferred to the main memory unit 51, and write access to the DRAM 513 is continuously performed using the page mode operation of the DRAM.

Then, the outer code error correction processing unit 552
An access request is output to the main memory unit 51. If the main memory control unit 512 recognizes the DRAM access window C, the data is read from the DRAM 513, and the data or outer code parity is sent to the outer code error correction processing unit 552 together with the access approval signal. Output. The outer code error correction processing unit 552 repeats this access,
Data and outer code parity required for the outer code error correction processing are input from the main memory unit 51.

Then, the outer code error correction processing section 552
An outer code error correction process is performed, and an access request for writing the data after the outer code error correction process to the DRAM 513 is output to the main memory unit 51. When the main memory control unit 512 recognizes the DRAM access window C, an access acknowledgment signal is issued. Is output to the outer code error correction processing unit 552, and when the access approval signal is input, the outer code error correction processing unit 552 transfers the data after the outer code error correction processing to the main memory unit 51 and writes the data to the DRAM 513.

Then, the signal reproduction processing unit 522 outputs an access request to the main memory unit 51 in advance, and
A 7-byte sync block is input from the main memory unit 51, and the input sync block is stored in the first adjustment memory 11, and is read out from the first adjustment memory 11 when necessary to decode a variable-length code, Processing such as discrete cosine transform, deshuffling, and D / A conversion is performed, and output as an analog audio video signal. The read access from the DRAM 513 of the sync block corresponds to FIG.
Is performed in the DRAM access window A. That is, when the DRAM access window A is recognized, the access approval signal is output to the signal reproduction processing unit 522, and the read access of the sync block from the DRAM 513 is continuously performed by using the page mode operation of the DRAM. When receiving the access approval signal, the signal reproduction processing unit 522 stores the sync block output from the main memory unit 51 in the first adjustment memory 11.

In the configuration of the present embodiment, when the insert operation of the audio reproduction video recording is performed, the audio reproduction sync block is delayed by demodulation and inner code error correction processing, so that the writing to the main memory is delayed. Since the video recording sync block is delayed by the addition of the inner code parity and the modulation process, it is necessary to read the data from the main memory at an early stage. As a result, the sync between the second data block processing means and the main memory unit is required. Overlap occurs in the block access, but in an operation in which overlap occurs, DR is required before the overlap occurs.
The sync block is read from the AM 513 and stored in the read adjustment memory 121 or the DRAM 5
13 is stored in the write adjustment memory 122, and when the overlap ends, D
The access to the RAM 513 is performed.

As described above, according to the embodiment of the present invention, the DRAM capable of continuously accessing the main memory of the sync block in the main memory control means 512
By setting an access window and using the page mode operation to access the sync block to the main memory, fast access is possible even if a DRAM is used as the main memory.

Further, according to the embodiment of the present invention, in the second adjustment memory 12 composed of two independent memories, the read adjustment memory 121 and the write adjustment memory 122, the total data block storage capacity of the memory is reduced. By setting the length to be equal to or more than the overlap in the main memory access at the time of the insert operation, no failure occurs in the main memory access at the time of the insert operation.

The setting of the DRAM access window is performed by setting the sync block to the DR using the page mode operation of the DRAM.
Any format that can access the AM may be used, and is not limited to the format in the present embodiment. Further, the capacity of the DRAM as the main memory only needs to have a capacity capable of performing the error correction processing of the product code, and is not limited to the embodiment.

[0048]

As described above, according to the present invention, the main memory control means sets the data block access period in which the data block can be continuously accessed to the main memory as an access window, thereby enabling the page mode operation of the DRAM. The data block can be accessed to the main memory with a small number of access times using
Even if a RAM is used, quick access is possible. Therefore, the DRAM can be used as the main memory, and the mounting area can be reduced and the cost can be reduced.

Further, according to the present invention, the second adjustment memory includes:
It is composed of two independent memories, a write adjustment memory and a read adjustment memory, and the total memory block storage capacity of the two memories is equal to or more than the overlap in the main memory access at the time of insert operation. Even when the main memory access is not broken, a normal insert operation can be performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a digital recording / reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a timing diagram of write access of a sync block from a signal recording processing unit to a DRAM during a recording operation in the digital recording / reproducing apparatus.

FIG. 3 is a timing diagram of write access of a sync block from a DRAM to an inner code parity adding section during a recording operation in the digital recording / reproducing apparatus.

FIG. 4 is a configuration diagram of one track of audio / video data to be recorded / reproduced in a conventional digital recording / reproducing apparatus.

FIG. 5 is a configuration diagram of a conventional digital recording / reproducing apparatus.

FIG. 6 is a main memory access timing diagram during a recording operation in a conventional digital recording / reproducing apparatus.

FIG. 7 is a main memory access timing diagram during a reproducing operation in a conventional digital recording / reproducing apparatus.

[Explanation of symbols]

 Reference Signs List 11 first adjustment memory 12 second adjustment memory 51 main memory section 52 first data block processing means 53 second data block processing means 54 modulation / demodulation means 55 outer code processing means 121 reading adjustment memory 122 writing adjustment memory 512 Main memory control means 513 DRAM 521 Signal recording processing unit 522 Signal reproduction processing unit 531 Inner code parity addition unit 532 Inner code error correction processing unit 541 Modulation unit 542 Demodulation unit 551 Outer code parity addition unit 552 Outer code error correction processing unit

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kenichi Nakamura 1006 Kazuma Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. (56) References JP-A-8-273347 (JP, A) JP-A-8- 6842 (JP, A) JP-A-5-204751 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/91-5/956 G11B 20/18

Claims (5)

(57) [Claims] 1. A digital recording / reproducing apparatus for recording / reproducing a data block forming an inner code as one transfer processing unit with respect to digital data constituting an error correction product code, wherein at least And a first data block for writing or reading data blocks to or from the main memory when an access request for a data block is output to the main memory and an access approval is received. A processing unit, a first adjustment memory for temporarily storing a data block accessed by the first data block processing unit with the main memory, and an asynchronous operation of the first data block processing unit with respect to the main memory. Access request of data block is output at timing of Receiving an access approval, temporarily storing a second data block processing means for writing or reading data block access to the main memory, and temporarily storing a data block which the second data block processing means accesses the main memory. A second adjustment memory, main memory control means for receiving an access request from the first data block processing means and an access request from the second data block processing means, and accessing a data block in the main memory; The first data block processing means outputs an access request to a main memory control means according to the accumulation state of the first adjustment memory, and the second data block processing means outputs the second adjustment memory To the main memory control means depending on the accumulation status of the Access request, the main memory control means sets a data block access period in which data blocks can be continuously accessed to the main memory as an access window, and recognizes the access window in response to the input access request. For example, an access acknowledgment is output to one of the first data block processing means and the second data block processing means that has made an access request, and the data block is accessed in the main memory. Digital recording and playback device. 2. In the main memory control means, priority is set in each access window for access to the first data block processing means and access to the second data block processing means. 2. The digital recording / reproducing apparatus according to claim 1, wherein when the access requests are duplicated, an access acknowledgment is output to a person having the priority of the access window. 3. A main memory control means, comprising:
If there is no access request from the first data block processing means and there is an access request from the second data block processing means in the access priority access window with the data block processing means, The second data block processing means outputs an access acknowledgment to the first data block processing means, and there is no access request from the second data block processing means in the access priority access window with the second data block processing means. 3. The digital recording / reproducing apparatus according to claim 2, wherein when there is an access request from the block processing means, an access approval is output to the first data block processing means. 4. A digital recording / reproducing apparatus for recording / reproducing digital data on / from a magnetic tape in track units, wherein one track contains N types of data (N> 1: N is an integer) which are independently recorded / reproduced. A digital recording / reproducing apparatus wherein said N kinds of data are recorded and reproduced in order from first data to Nth data, wherein a modulation unit for modulating a data block into a recording signal to be recorded on a magnetic tape; A demodulation means for demodulating a reproduction signal reproduced from the magnetic tape into a data block; and a second data block processing means for adding an inner code parity to a data block to be recorded and outputting the inner code parity. The second adjustment memory includes an addition unit and an inner code error correction processing unit that performs inner code error correction processing on the reproduced data block. And two independent memories, a write adjustment memory and a read adjustment memory, and the M-th data (0 <M <N: M is an integer) is the (M + 1) th data
In the operation of recording the data of the Mth data, the transfer of the reproduction data block of the Mth data is delayed by the demodulation and the inner code error correction processing, and the transfer of the recording data block of the M + 1th data is the addition of the inner code parity and modulation 2. The second adjustment memory according to claim 1, wherein the second adjustment memory has a data block storage capacity equal to or larger than an overlap at the time of main memory access resulting from the delay caused by the second adjustment memory.
4. The digital recording / reproducing apparatus according to any one of items 3 to 3. 5. The second data block processing means according to claim 2, wherein
The access request is output to the main memory control means by giving priority to the storage state of the read adjustment memory among the storage states of the write adjustment memory and the read adjustment memory in the adjustment memory. Claim 4
The digital recording / reproducing apparatus according to the above.