JP4026214B2 - Memory control method and recording / reproducing apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory control method applied to a memory used for recording deshuffling processing and reproduction shuffling processing of video data in, for example, a consumer digital video tape recorder, and a recording / reproducing apparatus to which the memory control method is applied About.
[0002]
[Prior art]
In recording signal processing in a consumer digital video tape recorder to which a so-called digital video format (hereinafter referred to as DV format) is applied, a video signal generated by a camera block or a video signal supplied from outside is blocked. The data is recorded on the magnetic tape in a predetermined tape format through shuffling processing, DCT (discrete cosine transform) processing, framing processing, recording deshuffling processing, parity generation and addition processing, recording modulation processing, and the like.
[0003]
Conversely, when reproducing a magnetic tape on which the video signal is recorded, the video signal reproduced from the magnetic tape is reproduced and demodulated, error-corrected, reproduced shuffling, deframing, IDCT (inverse discrete cosine). The image data is sent to a monitor or the like and displayed through a conversion process, a deblocking process, and a deshuffling process.
[0004]
Here, in the digital video tape recorder, recording deshuffling at the time of recording is performed by so-called bank operation in which two 1 Mbit memories (RAM) corresponding to the amount of video data for one frame are used alternately. Realizes processing and playback shuffling during playback.
[0005]
That is, in the recording deshuffling process, as shown in FIG. 15, the data for one screen already shuffled according to a certain regularity (shuffling pattern) is rearranged in the order from the upper left to the lower right of the screen. In contrast, the playback shuffling process reads out data of one screen input in an order corresponding to the order from the upper left to the lower right of the screen in accordance with a certain regularity (deshuffling pattern). Is the action. Therefore, in both the recording deshuffling process and the reproduction shuffling process, the data is shuffled between the input and the output. For example, when it is time to output a certain data, the data is still in time It can happen that it is not entered. For this reason, in both the recording deshuffling process and the reproduction shuffling process, data for one frame is stored in advance in the frame memory, and is read from the frame memory in accordance with the shuffling pattern or the deshuffling pattern. In order to maintain temporal continuity of frames, the frame memory is provided for two banks (BANK1, 2), and one frame memory is provided in one frame period. While a write operation (for example, BANK1) is being performed, a bank operation is performed such that the other frame memory (for example, BANK2) is read.
[0006]
The units of shuffling (or deshuffling) in the recording deshuffling process and the reproduction shuffling process are A0 to A9, B0 to B9, C0 to C9, D0 to D9, E0 to E9 in FIGS. 15 and 16C. It is performed for each unit called a super block indicated by. In the case of the SD mode (basic specification mode) of the so-called NTSC broadcasting system of the television standard broadcasting system in the DV format, the super block has 10 screens (PAL system) as shown in FIGS. In this case, it is divided into 12 tracks), and each track is further divided into 5 tracks. One super block is composed of 27 macroblocks MB0 to MB26 as shown in FIG. 16 (b), and one macroblock is composed of 80 compressed luminance and as shown in FIG. 16 (a). It consists of color difference data G0 to G79.
[0007]
[Problems to be solved by the invention]
By the way, the bank operation of the two frame memories as described above can simply configure the memory address arrangement with respect to the input / output data (super block), but requires a large amount of memory to be used. The area has also increased. In addition, address management in the control for banking two 1-Mbit RAMs is also complicated. Further, it is disadvantageous when a DRAM (dynamic RAM) or the like is built in an ASIC (Application Specific Integrated Circuit) in the future.
[0008]
Therefore, the present invention has been made in view of such circumstances, and a memory control method capable of reducing the memory capacity, reducing the board area and cost, and facilitating memory address management, and the memory control method It is an object to provide a recording / reproducing apparatus to which a memory control method is applied.
[0009]
[Means for Solving the Problems]
The memory control method of the present invention is a memory control method for performing writing / reading by shuffling or deshuffling data in a certain unit within a frame, and in one memory based on the shuffling or deshuffling rules. Read a certain unit of data from one area, write new data to one area where the certain unit of data has been read, and simultaneously read a certain unit of data from the other area In the long-time specification mode in which the data amount in one frame is ½ of the basic specification mode, the shuffling using half the area of the memory for the data with half the data amount in one frame Or deshuffling This solves the above-mentioned problem.
[0010]
The recording / reproducing apparatus according to the present invention is a recording / reproducing apparatus that records / reproduces data in units of frames by shuffling or deshuffling. The storage means stores data for one frame and the writing / reading of the storage means. An address control means for controlling the address, and based on the rules of shuffling or deshuffling, read a certain unit of data from one area in the storage means, and the one area from which the certain unit of data is read At the same time as writing new data to the In the long-time specification mode in which the amount of data in one frame is ½ of the basic specification mode, the above-described half area of the storage means is used for data of half the amount of data in one frame. Perform shuffling or deshuffling This solves the above-mentioned problem.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
[0012]
FIGS. 1 and 2 show schematic configurations of a recording system and a reproducing system of, for example, a consumer digital video tape recorder (VTR) as an embodiment to which the memory control method and recording / reproducing apparatus of the present invention are applied. Indicates.
[0013]
In the digital VTR recording system shown in FIG. 1, the camera / external line input unit 10 is a video signal generated by a camera unit having an imaging CCD (solid-state imaging device) and a lens system, or as a line input from the outside. The supplied video signal is sent to the blocking / shuffling processing unit 11. When the video signal from the camera unit or the video signal input on the line is an analog signal, it is converted into digital video data and then sent to the blocking / shuffling unit 11.
[0014]
The blocking / shuffling unit 11 blocks the supplied digital video data for each predetermined unit, and further performs shuffling (recording shuffling). The blocked and recording shuffled video data is sent to the transform coding processing unit 12.
[0015]
The transform coding processing unit 12 performs discrete cosine transform (DCT) processing on the blocked and recording shuffled video data, further zigzag scans the DCT coefficient data, and then performs quantization and variable length coding. The compressed code data obtained by the conversion is sent to the framing processing unit 13.
[0016]
The framing processing unit 13 forms a frame using the compression code data obtained by the variable length coding. The data framed by the framing processing unit 13 is sent to the recording deshuffling processing unit 14.
[0017]
The recording deshuffling processing unit 14 performs a recording deshuffling process on the data of the frame using one frame memory 17 as described later. The compressed code data subjected to the recording deshuffling processing by the recording deshuffling processing unit 14 is sent to the parity generation and addition processing (PTG) unit 15.
[0018]
The parity generation / addition processing unit 15 generates a parity from the compressed code data supplied from the recording deshuffling processing unit 14, adds the generated parity, and sends the parity to the recording modulation processing unit 16.
[0019]
The recording modulation processing unit 16 generates a recording signal that codes the supplied data and records it on a magnetic tape (video tape). This recording signal is recorded on the magnetic tape in a predetermined tape format by a head (not shown).
[0020]
On the other hand, in the consumer digital VTR reproduction system shown in FIG. 2, as shown in FIG. 2, a signal (reproduction signal) is read from the magnetic tape on which the recording signal is recorded, and this reproduction signal is reproduced and demodulated. It is sent to the processing unit 20.
[0021]
In the reproduction demodulation processing unit 20, the reproduction signal is decoded and supplied to the error correction (ECC) processing unit 21.
[0022]
The error correction processing unit 21 performs error correction processing using the parity added to the data from the reproduction demodulation processing unit 20, and sends the compressed code data after error correction to the reproduction shuffling processing unit 22.
[0023]
The playback shuffling processing unit 22 performs playback shuffling processing on the compressed code data using one frame memory 27 as described later. The compressed code data subjected to the reproduction shuffling process by the reproduction shuffling processing unit 22 is sent to the deframing processing unit 23.
[0024]
The deframing processing unit 23 deframes the compressed code data of the frame, and further sends the compressed code data after the deframing process to the decoding inverse transform processing unit 24.
[0025]
The decoding inverse transform processing unit 24 restores DCT coefficient data by decoding and decompressing and dequantizing the compressed code data, and further performing inverse zigzag scanning processing, and then performing inverse discrete cosine transformation (IDCT), This is supplied to the blocking / deshuffling processing unit 25.
[0026]
The deblocking / deshuffling processing unit 25 performs the deshuffling process on the data from the decoding inverse transformation processing unit 24 and then unblocks the block.
[0027]
The luminance and color difference signals after being decompressed and deshuffled as described above are then sent to the monitor 26 for display, for example.
[0028]
The digital VTR according to the present embodiment has a frame memory (RAM) 17 in the recording deshuffling process in the recording deshuffling process unit 14 in FIG. 1 and in the reproduction shuffling process in the reproduction shuffling process unit 22 in FIG. , 27 address control using dynamic addressing as shown in FIG. 3 makes it possible to realize efficient recording deshuffling processing and reproduction shuffling processing with only one frame memory 17, 27.
[0029]
That is, in FIG. 3, as an example of the dynamic addressing operation, as shown in FIG. 3A, for example, an input data series in which super blocks are arranged in the order of D, C, B, A is shuffled (this In this case, the output data series in which super blocks are arranged in the order of A, B, C, and D is given.
[0030]
In FIG. 3, the input data series is first arranged as shown in FIGS. 3B and 3G as an initial setting. In this initial setting state, the super block A0 is output.
[0031]
Next, as shown in FIG. 3 (c), the super block D1 is placed at the position where the super block A0 is output, and at the same time, the super block B0 is output. Next, as shown in FIG. 3D, the super block C0 is output at the same time as the super block C1 is placed at the position where the super block B0 is output.
[0032]
Similarly, as shown in FIG. 3 (e), the super block B1 is output at the same time as the super block B0 is placed at the position where the super block C0 is output, and the next is shown in FIG. 3 (f). As shown, the super block A1 is placed at the position where the super block D0 is output.
[0033]
With the above operation, the state shown in FIG. 3G becomes the state shown in FIG. 3H, and the movement (location) of each super block A, B, C, D is completed.
[0034]
Here, FIG. 4 shows an example of the address arrangement of the frame memory. In the example of FIG. 4, the NTSC SD mode is taken as an example.
[0035]
In FIG. 4, (a) shows one screen in the NTSC SD mode, and the one screen is composed of 720 pixels × 480 pixels. As shown in FIG. 4B, this one screen is divided into 10 tracks 0 to 9 (12 in the case of PAL), and each track is divided into five super blocks A, B, C, Divided into D. One super block is composed of 27 macroblocks MB from 0 to 26 as shown in FIG. FIG. 4 shows an example in which the relationship between the track, the super block, and the macro block is arranged on the memory as it is for easy understanding of the address arrangement.
[0036]
The unit of compression described above is one video segment composed of five macroblocks as shown in FIG.
[0037]
That is, in FIG. 5, one video segment is composed of five macroblocks each collecting one macroblock MB from each of the superblocks A, B, C, D, and E. 5, A, B, C, D, and E correspond to the super blocks A, B, C, D, and E, respectively, m is 0 to 9 (corresponding to the number of tracks), and n is 0. ~ 27 (corresponding to the number of macroblocks in one superblock).
[0038]
Thus, since the unit of compression is one video segment, it is appropriate to transfer data to the frame memory in units of one video segment.
[0039]
A specific operation of dynamic addressing in units of one video segment in the frame memory will be described below in the digital VTR of the present embodiment.
[0040]
FIG. 6 shows a simple timing chart of dynamic addressing in units of one video segment in the frame memory. Note that VS1 to VS5, VS1 ′ to VS5 ′ in FIG. 6 are data of one video segment, and R1, R2, and R3 in the figure indicate a certain memory area on the frame memory.
[0041]
That is, in FIG. 6, the dynamic addressing in one memory means that the data VS1 corresponding to one video segment stored in the memory area R1 in a certain unit processing time Ta is read from the frame memory, and the next unit This is to repeat the process of writing a new video segment data VS1 ′ in the vacant memory area R1 at the processing time Tb.
[0042]
FIG. 7 shows a timing chart when the dynamic addressing operation in units of video segments is realized by using, for example, two frame memories of 2-bank operation.
[0043]
In FIG. 7, when two frame memories operating in two banks are used, when data VS1 ′, VS2 ′, VS3 ′ of one video segment is sequentially written in one bank (BANK1), the other bank (BANK2), data VS1, VS2,. The operation of sequentially reading out VS3 is performed, and after switching between writing and reading by the bank signal, data VS1 ′, VS2 ′, VS3 ′ of one video segment is read out in one bank (BANK1). In the other bank (BANK2), an operation of writing data VS4 ′, VS5 ′,.
[0044]
As described above, in the two-bank operation as shown in FIG. 7, the write and read periods of the frame memory in each bank are controlled by the bank signal, whereas the dynamic addressing operation in FIG. There is no such thing.
[0045]
Next, with reference to FIG. 8, a description will be given to which address on the frame memory the super block of each track moves by the dynamic addressing described above. In FIG. 8, as an example, the relationship between the recording deshuffling processing unit 14 and the frame memory 17 of the recording system of FIG. In addition, although A0 to E9 in FIG. 8 each indicate a super block, the super block to which “′” is attached represents the super block input to the memory. FIG. 8A shows an example of an initial state where each super block is stored on the frame memory, and FIG. 8B shows a state after one track from the initial state.
[0046]
In FIG. 8, at the time of recording, that is, the recording deshuffling processing unit 14 of the recording system of FIG. 1 writes 27 video segment data per track into the frame memory 17, while converting the 27 video segment data into a deshuffling pattern. Since the data is read from the frame memory 17 by regular recording deshuffling, if the initial state of the data remaining in the frame memory 17 is the state shown in FIG. It becomes the state of.
[0047]
Next, in the NTSC SD mode, the transition of the address with respect to the super block of each track as seen in one frame unit which is a slightly longer processing unit is as shown in FIG. That is, when the initial state is the state shown in FIG. 9A, the state transitions to the state shown in FIG. 9B after one frame from the initial state, and the state shown in FIG. 9C after one more frame. In the same manner, each time one frame elapses, the state transitions to the states shown in FIGS. 9D and 9E. After one frame (that is, after five frames) from the state shown in FIG. 9E, the state returns to the state shown in FIG.
[0048]
The same thing is performed in the case of the PAL system. However, in the case of the PAL system, the state returns to the same state as the initial state after 6 frames. That is, as shown in FIG. 10, when the initial state is the state shown in FIG. 10A, the state transitions to the state shown in FIG. 10B after one frame from the initial state, and after one frame, The state transitions to the state of FIG. 10C, and thereafter transitions to the states of FIGS. 10D, 10E, and 10F each time one frame passes. After one frame (six frames later) from the state of FIG. 10 (f), the state returns to the state of FIG. 10 (a).
[0049]
Next, in the relationship between the playback shuffling processing unit 22 and the frame memory 27 in the playback system shown in FIG. 2 during playback, the transition of the address with respect to the super block of each track when viewed in units of frames is as shown in FIG. . That is, when the initial state is the state shown in FIG. 11A, the state transitions to the state shown in FIG. 11E after one frame from the initial state, and the state shown in FIG. In the same manner, the state transitions to the states of FIGS. 11C and 11B every time one frame passes. After one frame (that is, after five frames) from the state of FIG. 11B, the state returns to the state of FIG.
[0050]
As described above, the reproduction shuffling process in the reproduction system has the same five states as the recording deshuffling process in the recording system, but the transition order is reversed. Thus, the memory control unit of the recording deshuffling processing unit 14 and the memory control unit of the reproduction shuffling processing unit 22 can be used together.
[0051]
In the above description, the SD mode is taken as an example. However, in the DV format SDL mode (long-time specification mode), the data amount in one frame is ½ that in the SD mode. By performing dynamic addressing with half the memory capacity of the SD mode, recording deshuffling processing and reproduction shuffling processing are possible.
[0052]
FIG. 12 shows the state of address transition in the NTSC SDL mode. That is, in the SDL mode, dynamic addressing is performed without using half the memory area of the frame memories 17 and 27. The same applies to the PAL SDL mode.
[0053]
Further, in the dynamic addressing in the case of the SDL mode, not only the half of the memory capacity of one frame memory 17 or 22 is used as described above but also the bank in one frame memory using the remaining memory capacity. It is also possible to perform the operation.
[0054]
FIG. 13 shows an operation example in the case of performing the bank operation by dividing the memory capacity of one frame memory in half in the SDL mode and performing dynamic addressing in each bank memory. In FIG. 13, Wp represents a dynamic addressing pattern for writing, Rp represents a dynamic addressing pattern for reading, P1, P2, P3,. f4 represents the order of input and output frames. As shown in FIG. 13, the recording deshuffling process and the reproduction shuffling process can also be performed by performing the bank operation in the frame memory in the SDL mode.
[0055]
In this case, as shown in FIG. 14, two frames of data having a time difference of one frame exist in the frame memory at the same time. Therefore, the block in error during reproduction is replaced with the data one frame before. Data supplementation (conceal) is also possible.
[0056]
As described above, in this embodiment, dynamic addressing is used for memory address control for performing recording deshuffling processing or playback shuffling processing of video data in a consumer digital video format (DV format). , Recording deshuffling processing or playback shuffling processing in the DV format SD mode is performed with a memory capacity (equivalent to 1 Mbit) for storing data of one frame of video data in the DV format such as SD mode. It is possible. That is, according to the embodiment of the present invention, the processing that conventionally required the memory for two frames can be realized with half the memory. This is advantageous when a large capacity memory is built in the ASIC in the future.
[0057]
Further, in the present embodiment, the memory capacity (equivalent to 0.5 Mbit) required for storing data of one frame of video data in DV format, for example, SDL mode, in the DV format SLD mode. The recording deshuffling process or the reproduction shuffling process can be realized. Further, in this SDL mode, inter-frame data complementation (concealment or the like) at the time of reproduction by data transfer between bank memories divided in one frame memory becomes possible.
[0058]
As described above, in the present embodiment, a frame memory equivalent to 1 Mbyte is compatible with both the NTSC and PAL SD and SDL modes.
[0059]
【The invention's effect】
As is clear from the above description, in the present invention, by using dynamic addressing, shuffling or deshuffling can be performed with one frame memory, so that the memory capacity can be reduced, the substrate area and cost can be reduced, Memory address management can also be facilitated. This is also advantageous when a large capacity memory is built in the ASIC in the future.
[Brief description of the drawings]
FIG. 1 is a block circuit diagram showing a schematic configuration of a recording system of a consumer digital VTR according to an embodiment of the present invention.
FIG. 2 is a block circuit diagram showing a schematic configuration of a reproduction system of a consumer digital VTR according to an embodiment of the present invention.
FIG. 3 is a diagram used for explaining a basic operation of dynamic addressing.
FIG. 4 is a diagram illustrating an example of an address arrangement when one frame memory is used.
FIG. 5 is a diagram used for explaining one video segment;
FIG. 6 is a diagram used for explaining dynamic addressing processing in units of one video segment by one frame memory.
FIG. 7 is a diagram used for explaining processing in units of one video segment by a two-bank memory.
FIG. 8 is a diagram used for explaining address transition (after one track) at the time of dynamic addressing;
FIG. 9 is a diagram used for explaining address transition in recording deshuffling processing in the NTSC SD mode.
FIG. 10 is a diagram used for explaining address transition in recording deshuffling processing in the PAL SD mode;
FIG. 11 is a diagram used for explaining address transition in the reproduction shuffling process in the SD mode of the NTSC broadcasting system.
FIG. 12 is a diagram used for explaining address transitions in recording deshuffling processing in the NTSC SDL mode;
FIG. 13 is a diagram used for explaining how to use the frame memory in the SDL mode (dynamic addressing + 2-bank control);
FIG. 14 is a diagram used for explaining how to use a memory in the SDL mode (dynamic addressing + 2-bank control + interbank complementary transfer);
FIG. 15 is a diagram used for explaining a recording deshuffling process by a two-bank operation of two frame memories.
FIG. 16 is a diagram used for explaining an address arrangement when two frame memories of a two-bank operation are used.
[Explanation of symbols]
10 camera / external line unit, 11 blocking / shuffling processing unit, 12 transform coding unit, 13 framing processing unit, 14 recording deshuffling processing unit, 15 parity generation and addition processing unit, 16 recording modulation processing unit, 17 frame memory
20 reproduction demodulation processing unit, 21 error correction processing unit, 22 reproduction shuffling processing unit, 23 deframing processing unit, 24 decoding inverse transformation processing unit, 25 deblocking / deshuffling processing unit, 26 monitor, 27 frame memory

Claims (8)

In a memory control method when writing / reading data by shuffling or deshuffling data in a certain unit in a frame,
Based on the shuffling or deshuffling rules, a certain unit of data is read from one area in one memory, and new data is written to the one area from which the certain unit of data is read. to read out the data of certain units from one region,
In the long-time specification mode in which the amount of data in one frame is ½ of the basic specification mode, the shuffling or deconstructing using half the area of the memory is performed on the data of half the amount of data in one frame. A memory control method comprising shuffling . 2. The memory control method according to claim 1, wherein the predetermined unit is one macroblock or one video segment of a digital video format. Using alternating half area of the memory, the memory control method according to claim 1, wherein the performing the shuffling or de-shuffling. 4. The memory control method according to claim 3 , wherein when the half area of the memory is alternately used, inter-frame data interpolation is performed by transferring data between the half areas. In a recording / reproducing apparatus for recording / reproducing data in units of frames by shuffling or deshuffling,
Storage means for storing the data for one frame;
Address control means for controlling the write / read address of the storage means,
The address control means reads a fixed unit of data from one area in the storage means based on a shuffling or deshuffling rule, and adds new data to the one area from which the fixed unit of data is read. written at the same time, have the row address control for reading the data of the predetermined unit from the other one of the regions,
In the long-time specification mode in which the data amount in one frame is ½ of the basic specification mode, the shuffling using half the area of the storage means for the data amount half of one frame or A recording / reproducing apparatus that performs deshuffling . 6. The recording / reproducing apparatus according to claim 5, wherein the predetermined unit is one macroblock or one video segment in a digital video format. 6. The recording / reproducing apparatus according to claim 5 , wherein the shuffling or deshuffling is performed by alternately using a half area of the storage means. 8. The recording / reproducing apparatus according to claim 7 , wherein when the half area of the storage means is alternately used, inter-frame data interpolation is performed by data transfer between the half areas.

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