JP3334140B2 - Digital video signal recording apparatus, reproducing apparatus and recording method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for compressing a digital video signal by compression coding and recording the digital video signal on a magnetic tape
In addition, the present invention relates to a recording apparatus , a reproducing apparatus, and a recording method for reproducing a compressed signal from a magnetic tape , and particularly to improving the image quality during variable speed reproduction.

[0002]

2. Description of the Related Art Recently, a digital VT for digitizing a color video signal and recording it on a recording medium such as a magnetic tape.
As R, a D1 format component digital VTR and a D2 format composite digital VTR for broadcasting stations have been put to practical use.
These digital VTRs record component signals or composite signals on magnetic tape without compression.

In order to reduce the amount of tape required for recording and to use a small-sized tape cassette, it has been considered to compress the information amount of a digital video signal by highly efficient encoding. Transform coding is known as one of the high-efficiency coding methods. Transform coding, for example, two-dimensional coding, divides image data into code blocks of (8 × 8) pixels, for example, and performs orthogonal transform for each code block. The conversion component (referred to as a coefficient) includes a DC component to a high-frequency component. Generally, since the DC component is large and the high-frequency component is small, the number of bits is reduced as a whole by allocating an appropriate number of bits to each coefficient. Recently, DCT (Discrete Cosine Transform) has been particularly noted.

As another method of the compression encoding, the present applicant defines the maximum and minimum values of a plurality of pixels included in a two-dimensional block as described in Japanese Patent Application Laid-Open No. 61-144,891. A high-efficiency coding apparatus (referred to as ADRC) for determining a dynamic range to be performed and performing coding adapted to the dynamic range has been proposed.

[0005] A shuffling technique is generally used in order to disperse the influence of a burst error that occurs during recording / reproducing as well as high-efficiency coding such as conversion coding and ADRC. In other words, after shuffling to make the position of the data generated by the high efficiency encoding different from the original position, the data is recorded, and after the data is reshuffled to return the reproduced data to the original position, high shuffling is performed. Decoding of efficiency coding is performed. Conventionally, pixels (samples) or code blocks have been adopted as the size of the shuffled data.

[0006]

A VTR requires a variable speed reproduction function for making the tape speed different from that at the time of recording. At the time of variable speed reproduction, since the scanning position of the rotary head is different from that at the time of recording, the recorded data can be reproduced only in pieces. As a result, an image of one frame is restored using the reproduction data included in the plurality of frames. In a digital VTR employing the above-described shuffling, data reproduced fragmentarily from a magnetic tape during variable speed reproduction is deshuffled and then decoded. Therefore, when shuffling is performed in units of samples, adjacent samples are often included in different frames, and when shuffling is performed in units of code blocks, adjacent code blocks have different frames. Is similarly generated. This leads to a deterioration in the quality of the restored image at the time of variable-speed playback, especially in the case of an image with fast movement.
Only images that are difficult to distinguish can be obtained.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a digital video signal recording apparatus and a reproducing apparatus which can improve the quality of a restored image even when a shuffling process is employed or during variable speed reproduction.
And a recording method .

[0008]

According to the present invention, an input digital video signal is subdivided into data in units of blocks each consisting of a plurality of pixel data, and the input digital video signal is subjected to high-efficiency encoding for each block. In a digital video signal recording device in which output data is recorded on a magnetic tape by a plurality of magnetic heads mounted on a rotating drum, a storage circuit for storing pixel data,
Readout circuit for reading desired pixel data from storage circuit
Consisting of multiple blocks that are spatially adjacent
For each macroblock unit, a predetermined position within the macroblock
By reading out the pixel data in the readout circuit by a readout circuit, a first shuffling circuit (4) for performing shuffling in units of macroblocks and output data of the first shuffling circuit (4) are supplied , and a high-efficiency encoding circuit for using the correlation of the compression de <br/> over data amount (5), high
A second shuffling circuit (6) for shuffling output data of the efficiency encoding circuit (5) in macroblocks on a sample basis, and a circuit for error correction encoding the output of the second shuffling circuit (6) (7) A digital video signal recording device comprising: According to a second aspect of the present invention, there is provided a reproducing apparatus for decoding a high efficiency coded digital video signal read in units of blocks from a magnetic tape and decomposing the digital video signal into blocks to obtain a reproduced digital video signal. An error correction decoding circuit for decoding an error correction code of the video signal,
A macro block composed of a plurality of spatially adjacent blocks
A first deshuffling circuit for restoring the output data of the error correction decoding circuit shuffled on a sample basis within the lock, and using the correlation between the output data of the first deshuffling circuit in the block. a decoding circuit for decoding in block units Te, for each macro block, a macro
To read the pixel data in a predetermined position in the block
Accordingly, the playback apparatus of the digital video signal and a second de-shuffling circuit undo output of shuffled Tei Ru decoding circuit in macroblock units. A third aspect of the present invention, subdivided into data blocks comprising an input digital video signal from a plurality of pixel data, and high-efficiency encoding an input digital video signal for each block, the rotary drum output data of the high-efficiency coding A digital video signal recording method for recording on a magnetic tape by a plurality of magnetic heads mounted on the
A macro block composed of a plurality of spatially adjacent blocks
The pixel at a predetermined position in the macroblock for each lock unit
A first shuffling step of performing shuffling in units of macroblocks by reading data, and data subjected to the first shuffling are supplied, and a data amount is reduced by utilizing a correlation in the block. Highly efficient encoding of the data for compression, and second encoding of the highly efficient encoded data in macroblocks on a sample basis .
Performing a shuffling, comprising: a second shuffling is error correction encoded data made a recording method of a digital video signal consisting of.

[0009]

The shuffling circuit 4 performs shuffling on a macroblock basis. Therefore, the encoded output of the macro block is recorded on the magnetic tape in a lump, and the data of the macro block can be obtained at the time of variable speed reproduction.
In addition, random errors in a macroblock are easily corrected because shuffling is performed in the macroblock.

[0010]

An embodiment of the present invention will be described below. FIG. 1 shows a signal processing unit of a recording system and a reproducing system of this embodiment. An analog video signal is supplied to an input terminal 1 and is converted into a digital video signal by an A / D converter 2. This digital video signal has a sampling frequency of 13.5 MHz and the number of bits per sample is 8 bits. Data of the blanking period is removed from the input video signal, and only the information of the effective area is recorded / reproduced. The digital video signal is obtained by converting the data order from the raster scanning order to the code block order by the blocking circuit 3.

In this example, the effective area of one frame is set to (8
× 8) Subdivide into many code blocks of pixels. Therefore, as shown in FIG. 2A, the inside of the screen of one frame is (mx
n) Divided into blocks. An output signal of the blocking circuit 3 is supplied to a shuffling circuit 4 in macroblock units. In this embodiment, as shown in FIG. 2B, (2 ×
2 = 4) A macroblock is constituted by a code block. Therefore, in one frame, (m / 2 × n / 2) macro blocks are generated. The shuffling circuit 4 performs shuffling on a macroblock basis. That is,
The data is rearranged so that macroblocks included in one frame are located at positions different from the original positions.
FIG. 3 shows shuffling in units of macro blocks. Numerals 1, 2 and 3 indicate the order of macro blocks read from the memory from the shuffling circuit 4. The dot at the upper left corner of each macroblock means the start address when shuffling is performed by the memory.

The output data of the shuffling circuit 4 is supplied to a block coding circuit 5 for performing compression coding in code block units. For example, when performing DCT encoding, the block encoding circuit 5 includes a DCT conversion circuit, a quantization circuit,
It includes a variable length encoding circuit and the like, and (8 ×
The coefficient data of 8) is output in order from the DC component to the higher order. When the encoding circuit 5 performs ADRC encoding, it includes a circuit for detecting a dynamic range DR, a minimum value MIN, a circuit for requantizing pixel data normalized by removing the minimum value MIN, and the like. A dynamic range DR, a minimum value MIN, and a code signal of (8 × 8) are output for each coding block.

The output data of the block encoding circuit 5 is supplied to a shuffling circuit 6 in sample units. The shuffling circuit 6 performs shuffling that is completed within a macroblock. That is, as shown in FIG.
The position (16) of the sample (coefficient data or code signal) is different from the original position in the macro block. In FIG. 4, the numbers marked on the samples indicate the order of the samples read from the memory.

The output of the shuffling circuit 6 in sample units is supplied to a parity adding circuit 7. The parity adding circuit 7 adds the parity of the error correction code. As the error correction code, for example, a product code using a Reed-Solomon code can be used. Output data of the parity adding circuit 7 is supplied to a sync blocking circuit 8. The sync block is a fixed-length data having a synchronization code at the beginning, and includes ID data representing output data of the block encoding circuit 5, parity, the address of the sync block, and the like.
Contains code. This sync block is the minimum unit for recording / playback, and during variable speed playback, when the entire sync block can be played back, it is treated as valid data.

The output of the sync blocking circuit 8 is supplied to an encoder 9 for channel coding. Channel coding reduces the DC component of the recording data. Output data of the channel encoder 9 is supplied to a plurality of magnetic heads of a tape head system 12 via a parallel-serial conversion circuit 10 and a recording amplifier 11, and is recorded on a magnetic tape. The tape head system 12 is, for example, a double azimuth head in which two head elements are arranged close to each other and attached to a rotating drum at an interval of 180 °.
Book tracks are simultaneously formed on the magnetic tape. As described above, shuffling is performed for each macroblock,
Since shuffling in sample units is completed within a macroblock block, macroblock data is collectively recorded on tracks on a magnetic tape on which serial data having a sync block structure is recorded.

The reproduction data from the tape head system 12 is supplied to a serial-parallel conversion circuit 22 via a reproduction amplifier 21 and is converted from serial data to parallel data. The reproduced data is supplied to a sync block decomposition circuit 24 via a channel coding decoder 23. The sync block decomposition circuit 24 detects a break of the sync block and separates an ID code or the like in the sync block. The output of the sync block decomposition circuit 24 is supplied to the error correction circuit 25, where the error correction code is decoded.

After the error correction circuit 25 corrects, the reproduced data is supplied to the deshuffling circuit 26 in sample units. This deshuffling circuit 26 returns each sample shuffled in the macroblock to the original position. Output data of the deshuffling circuit 26 is supplied to a block decoding circuit 27.

The decoding circuit 27 includes, in the case of DCT, a decoder for variable-length codes, an inverse quantization circuit, and an inverse transform circuit. The decoded data of 64 pixels included in an (8 × 8) code block is decoded. Generated. In the case of ADRC, the decoding circuit 27 includes a ROM for generating a restoration level after removing the minimum value from the dynamic range DR and the code signal, a circuit for adding the minimum value MIN to the output of the ROM, and the like.

The decoded output of the decoding circuit 27 is supplied to a deshuffling circuit 28 for each macroblock. The deshuffling circuit 28 performs a conversion in a direction opposite to that of the shuffling circuit 4, that is, a process of arranging the position of the macroblock in one frame at the original position. The output signal of the deshuffling circuit 28 is supplied to the block decomposition circuit 29, and the data order is converted from the code block to the raster scan order. The output of the block decomposition circuit 29 is supplied to the error correction circuit 30. As described above, the error correction circuit 30 interpolates the pixel data having an uncorrectable error with the surrounding correct pixel data in the decoded reproduced data. For example, the pixel data of the error is replaced with the average value of four pixel data located on the upper, lower, left and right sides. An output signal of the error correction circuit 30 is supplied to a D / A converter 31, and an analog reproduction video signal is obtained at an output terminal 32.

Shuffling circuit 4 in macroblock units
An example is shown in FIG. When the input video signal is a component signal composed of a luminance signal and a chrominance signal (including two color difference signals), a digital luminance signal and a digital chrominance signal are supplied to input terminals 41Y and 41C of the shuffling circuit 4, respectively. You. Two SRAMs 42A and 42B are provided for the luminance signal, and two SRAMs 43A and 43
3B are provided to form a so-called double bank.
Each SRAM has a capacity to store one frame of data. The data amounts of the luminance signal and the chrominance signal in one frame are equal in this example. RAMs 42A and 42B,
Output data read from 43A and 43B is taken out to output terminals 44Y and 44C.

The SRAM 42 via the multiplexer 45
Address signals are supplied to A, 42B, 43A and 43B. The multiplexer 45 is supplied with a write address from the address counter 46W and a read address from the ROM 47. In one frame period,
Multiplexer 45 allows SRAMs 42A and 4A
A write address is supplied to 3A, a read address is supplied to SRAMs 42B and 43B, and in the next one frame period, a write address is supplied to SRAMs 42A and 43A and a read address is supplied to SRAMs 42B and 43B.

The ROM 47 has an address counter 46R.
Is supplied as an address. In ROM47,
A table for converting the output of the counter 46R according to the shuffling rule is stored. This table is for generating a read address obtained by adding an offset to the output of the counter 46R. In the configuration shown in FIG. 5, the luminance signal and the color signal of one frame input in the raster scanning order are written in the SRAM, and are read at the read address from the ROM 47 in the next frame.

The read address performs the above-described shuffling in the unit of a macroblock, and outputs the samples in the macroblock in a predetermined order. Therefore, the shuffling circuit in FIG. 5 has the function of the blocking circuit 3 in addition to the shuffling in units of macroblocks, and as a result, the memory capacity is reduced. The sample-based shuffling circuit 6 performed after performing the DCT coding can have the same configuration as that of FIG. However, the cycle of bank switching is the cycle of a macroblock, and the capacity of the SRAM is one macroblock.

When ADRC is used for high-efficiency encoding, the encoded output includes an important word (dynamic range and minimum value) generated for each block and (8 × 8
= 64) code signals for each pixel. When this encoded output is shuffled by a double bank, the timing of input / output to the SRAM differs. Therefore, when shuffling the encoded output of the ADRC, it is necessary to provide a key word shuffling circuit and a code signal shuffling circuit having separate address generation circuits. Further, the deshuffling circuits 26 and 2
Reference numeral 8 denotes a configuration similar to that of the above-described shuffling circuit, and a deshuffling table is used as a ROM table for generating addresses.

When constructing a macroblock, as shown in FIG. 6A, a macroblock may be composed of nested code blocks other than a macroblock in which four adjacent code blocks are collected. FIG. 6A shows portions of four macroblocks 1 to 4. This FIG. 6A
For example, a macroblock to which a numeral of 1 is attached is, as shown by hatching, a four-line macroblock selected from two lines alternately.
It consists of code blocks.

In such a macroblock configuration, for example, when all of the four code blocks in the macroblock of the number 2 have an error, if the other macroblocks (1, 3 and 4) are not errors, As shown in FIG. 6B, an example of a code block marked with “x” includes a non-error code block around the error code block. Therefore, it is possible to interpolate the data of the erroneous code block by the data of the surrounding code blocks. Further, even if a macroblock is constituted by a code block located at the fifth eye (Quincanx), it is equally advantageous in terms of error correction.

[0027]

According to the present invention, since shuffling is performed in units of macroblocks, data contained in macroblocks is recorded collectively on a magnetic tape. Therefore, at the time of variable-speed reproduction, pixel data included in different frames does not exist in the reproduced image in a lump, and a good reproduced image can be obtained. Further, according to the present invention, since a shuffling is performed in a macroblock, when a random error occurs in the macroblock, the error sample can be satisfactorily modified. In addition, before high efficiency coding
Blocking is performed because shuffling is performed in macro block units.
Compression efficiency when performing high-efficiency coding using intra-
There is an advantage that the rate does not decrease.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a recording system and a reproducing system according to an embodiment of the present invention.

FIG. 2 is a schematic diagram used for describing a code block and a macro block according to one embodiment of the present invention.

FIG. 3 is a schematic diagram used for explaining shuffling in units of macroblocks according to an embodiment of the present invention;

FIG. 4 is a schematic diagram used for explaining shuffling in sample units according to an embodiment of the present invention.

FIG. 5 is a block diagram illustrating an example of a shuffling circuit.

FIG. 6 is a schematic diagram illustrating another example of the configuration of a macroblock.

[Explanation of symbols]

 4 Shuffling circuit per macroblock 5 Encoding circuit for high efficiency coding 6 Shuffling circuit per sample 7 Parity addition circuit

────────────────────────────────────────────────── ─── Continued from the front page Examiner Tetsuo Tomizawa (56) References JP-A-2-220270 (JP, A) JP-A-62-253277 (JP, A) JP-A-2-121584 (JP, A) JP-A-1-34076 (JP, A) JP-A-4-278261 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11B 20/10-20/16 H04N 5/91- 5/95

Claims (3)

(57) [Claims] 1. An input digital video signal is subdivided into data of a block unit composed of a plurality of pixel data, the input digital video signal is encoded with high efficiency for each of the blocks, and output data of the high efficiency encoding is output to a rotating drum. In a digital video signal recording apparatus in which recording is performed on a magnetic tape by a plurality of magnetic heads mounted on a storage device, storage means for storing pixel data;
Readout means for reading the desired pixel data
Macro block consisting of a plurality of above blocks close to
Image at a predetermined position in the macroblock for each
A first shuffling means for performing shuffling in units of the macroblock by reading raw data by the reading means, and output data of the first shuffling means,
High-efficiency encoding means for compressing the data amount using the correlation in the block; and second shuffling means for shuffling output data of the high-efficiency encoding means in sample units in the macroblock. And a means for performing error correction coding on the output of the second shuffling means. 2. A reproducing apparatus for decoding a digital video signal, which has been efficiently coded in units of blocks read from a magnetic tape, and for obtaining a reproduced digital video signal by decomposing the blocks, comprising the steps of: An error correction decoding means for decoding an error correction code of a signal, and a macro comprising a plurality of blocks which are spatially adjacent to each other.
A first method for restoring the output data of the error correction decoding means shuffled in sample units in the
Di shuffling means and said blanking output data of the first de-shuffling means
Decoding means for decoding in units of blocks using the correlation in the lock; and for each macroblock unit,
By reading pixel data in a predetermined position, the reproducing apparatus of the digital video signal and a second de-shuffling means for returning to the original output of the shuffled Tei Ru said decoding means in units of macroblocks. 3. A segmented by data of the input digital video signal block comprising a plurality of pixel data, said input digital video signal for each of the blocks and high-efficiency encoding, the output data of the upper Symbol efficient coding In a digital video signal recording method in which a plurality of magnetic heads mounted on a rotating drum record on a magnetic tape, a digital video signal recording method comprising:
A predetermined position in the macroblock is
By reading the location of the pixel data, performing a first shuffling performing shuffling in units of the macroblock, the first shuffling is supplied data made, the correlation within the block Highly efficient encoding the data in order to compress the amount of data by utilizing the data; performing a second shuffling of the highly efficient encoded data in the macroblock on a sample basis; step a method of recording a digital video signal consisting of the error correction coding shuffling is performed data.