JP3624457B2 - Image signal encoding apparatus and image signal decoding apparatus - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to an image signal encoding device and an image signal decoding device using a synchronous DRAM (Synchronous DRAM) as a frame memory.
[0002]
[Prior art]
Conventionally, an image signal encoding device and an image signal decoding device have a frame memory for storing an image signal for each frame.
[0003]
When a dynamic RAM (hereinafter referred to as DRAM), which is a volatile read / write memory having a large capacity and low price, is used as a semiconductor memory for this frame memory, there is a problem because the operation speed is not high. In addition, the non-volatile static RAM has a problem that the operation speed is high but the storage capacity is small.
[0004]
Therefore, it is considered to use a synchronous DRAM that can perform continuous access at high speed, so-called synchronous DRAM (hereinafter referred to as SDRAM).
[0005]
This SDRAM is a DRAM that performs high-speed burst transfer in synchronization with the rising edge of an input clock signal, in compliance with JEDEC (Joint Electron Engineering Engineering Council). This burst transfer is a method in which data on the same row address is read / written continuously in units of 2, 4 or 8 multiple word blocks. This number of read / write words is called a burst length or burst length.
[0006]
Since this SDRAM also has two banks, the access time while changing the row address is equivalent to the access time of a normal DRAM due to the necessity of precharging, but the banks are accessed alternately. By doing so, it is possible to write or read data in the other bank during the precharge of one bank.
[0007]
However, in order to continuously write or read data while switching the row address, it is necessary to set the number of clocks to be written or read after giving a column address to 8 or more.
[0008]
Here, for example, a timing chart at the time of random row reading is shown in FIG. 5, and the operation of the SDRAM will be described.
[0009]
The burst length is set to 8, and the two banks A and B are switched.
[0010]
First, after the active command RBa for the bank B is output, the read command CBa is output. As a result, the read of data BBa _{1 to} QBa ₈ is sequentially performed after a predetermined time of output of the read command CBa, specifically, after 3 clocks.
[0011]
Further, while the data in the bank B is being read, the read command CAa is output after the active command RAa in the bank A is output. As a result, the data read QAa _{1 to} QAa ₈ of the bank A are sequentially performed following the data read QBa ₈ of the bank B.
[0012]
As described above, the burst length of 8 in the SDRAM means that data for 8 consecutive addresses is written or read. When data on continuous addresses is written or read, The use efficiency of the SDRAM data bus is high.
[0013]
Further, in order to access the SDRAM at high speed, it is necessary to set the number of clocks from the read command until the data is output to 3. This is a value representing the delay time from the input of the column address strobe (hereinafter referred to as CAS) to the data output in terms of the number of clocks, and is called CAS latency.
[0014]
FIG. 6 shows the CAS latency and command timing. Here, the burst length is 4.
[0015]
For example, the CAS latency is 1 when the operating clock is 25 to 50 MHz, the CAS latency is 2 when the operating clock is 50 to 66 MHz, and the CAS latency is 3 when the operating clock is 66 MHz or higher. When the CAS latency is 1, as shown in A of FIG. 6, the write command WA is output by the clock T _1, when the read command RB clock T ₂ is continuously output to the data DA ₁ is Data is read QB ₁ , QB ₂ , QB ₃ , QB ₄ after writing and after one clock interval. When the CAS latency is 2, as shown in FIG. 6B, after data DA ₁ is written and two clock intervals are left, data read QB ₁ , QB ₂ , QB ₃ , QB ₄ is performed. Is called. Further, when the CAS latency is 3, as shown in C of FIG. 6, the lead _QB 1 of the data after the data DA ₁ is placed 3 clock interval is _written, QB _2, QB 3, QB ₄ row Is called.
[0016]
[Problems to be solved by the invention]
By the way, when this SDRAM is used as a frame memory of an image signal encoding device and an image signal decoding device, the burst length of this SDRAM is set to 8, and when it is desired to read a part of data of continuous addresses, the address is Since it is continuous, unnecessary data is also read.
[0017]
For example, in compression encoding of a moving image, when performing discrete cosine transform (hereinafter referred to as DCT) processing, an 8 × 8 pixel sub-block is used. Specifically, as shown in FIG. 7, four luminance signal DCT blocks Y ₁ , Y ₂ , Y ₃ , Y ₄ , two color difference signal DCT blocks Cr ₁ , Cr ₂ , and two color difference signals. A total of 512 bytes of 8 DCT blocks consisting of DCT blocks Cb ₁ and Cb ₂ are used. A block of 16 × 16 pixels obtained by collecting a plurality of these DCT blocks is called a macro block. The size on the screen is 16 × 16 because the luminance signal Y and the color difference signals Cr and Cb overlap.
[0018]
Therefore, as shown in FIG. 8, macro block data on the same row address is read into the banks 0 and 1 of the SDRAM. Data in the same macroblock is recorded at the same row address, and control of the row address is less and signal processing is simplified.
[0019]
Thus, when motion compensation is performed after macroblock data is recorded, if the motion vector is an integral multiple of the macroblock size, the selected macroblock data may be read from the frame memory as it is.
[0020]
However, when the motion vector does not take a value that is an integral multiple of the macroblock size, it is necessary to read data across a plurality of macroblocks.
[0021]
Here, when the burst length in the SDRAM is set to 8, data can always be read only in units of 8 × 8 DCT blocks, so that unnecessary data is read very much. For example, when the motion vector is an integer and this motion vector is (X, Y) = (2, 2), as shown in FIG. 9, when reading the macroblock of the luminance signal Y, (24 × 24) / (16 × 16) = 9/4 times the burst transfer of data is required. The same applies to the macro blocks of the color difference signals Cr and Cb.
[0022]
On the other hand, when the burst length is switched to 8 or less, several clocks are required to send a command, and data transfer cannot be performed while the command is being sent.
[0023]
Therefore, in view of the above situation, the present invention provides an image signal encoding device capable of accessing only necessary data without lowering the data bus use efficiency when it is desired to access the SDRAM in units of 8 or less. An image signal decoding apparatus is provided.
[0024]
[Means for Solving the Problems]
An image signal encoding apparatus according to the present invention is an image signal encoding apparatus for writing an image signal into a storage means composed of a synchronous DRAM, and reading out the written image signal to perform compression encoding. The length is fixed, multiple types of image signals are stored on the same row address with different column addresses, and a plurality of read commands are output within the burst length while the row address is specified by an active command. By having a memory control means for sequentially switching and specifying the column addresses, the above-mentioned problems are solved.
[0025]
The image signal decoding device according to the present invention is an image signal decoding device for writing and outputting decompressed and decoded image data to a storage means comprising a synchronous DRAM, and fixing the burst length of the storage means, A plurality of types of image signals are stored on the same row address with different column addresses, and a plurality of read commands are output within the burst length in a state where the row address is specified by an active command, and a plurality of column addresses are sequentially By having the memory control means for designating switching, the above-described problems are solved.
[0026]
[Action]
In the present invention, the burst length of the storage means composed of the synchronous DRAM is fixed, a plurality of types of image signals are stored on the same row address, and the row address is designated by an active command, and then read several times. A command is output to sequentially switch a plurality of column addresses, and image signals with different column addresses are read out.
[0027]
【Example】
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a schematic configuration of an image signal encoding device according to the present invention, and FIG. 4 shows a schematic configuration of an image signal decoding device according to the present invention.
[0028]
The image signal encoding apparatus shown in the embodiment of FIG. 1 performs an image compression encoding process using the correlation in the time direction, and records the compressed image data on a tape, for example, as a recording medium. In the image signal composite apparatus shown in the embodiment of FIG. 4, the recorded image data is read out, subjected to image expansion composite processing, and output as an image signal.
[0029]
Note that there is a moving picture experts group (MPEG) system as a high-efficiency encoding system that uses correlation in the time direction of image signals. Or any one of the three types of pictures: P picture (Predictive Picture: forward predictive encoded picture) and B picture (Bidirectionally predictive Picture: bi-predictive encoded picture) A method of performing compression coding by combining frame images of these three types of pictures is used.
[0030]
In the image signal encoding apparatus shown in FIG. 1 and the image signal decoding apparatus shown in FIG. 4, a process of switching between a B picture and an I picture is performed.
[0031]
First, in the image signal encoding apparatus of FIG. 1 on the recording side, a digital image signal for each frame is input from the signal input terminal 1. Here, the frame memories 3 and 4 made of SDRAM are controlled by the memory control circuit 5, and for example, the image signal of the (N + 1) th frame image two frames before the (N-1) th frame image is obtained. The image signal of the Nth frame image one frame before the (N−1) th frame image is written to the frame memory 4.
[0032]
Thereafter, an image signal of the (N−1) th frame image is input from the signal input terminal 1, and the image signals of the three frame images are sent to the motion vector detection circuit 6.
[0033]
In the motion vector detection circuit 6, the motion vector between the (N + 1) th frame image in the frame memory 4 and the Nth frame image in the frame memory 3, and the Nth frame image in the frame memory 3 are displayed. A motion vector between the frame image and the (N-1) th frame image is detected.
[0034]
If the image data to be output is B-picture image data, the image signal of the (N + 1) th frame image written in the frame memory 4 is read and sent to the motion compensation circuit 7, and , The (N−1) th frame image is sent to the motion compensation circuit 8.
[0035]
In general, the size of a DCT block used for DCT processing described later is 8 × 8. If one pixel, that is, one pixel is 8 bits (= 1 byte), the data amount of one DCT block is 64 bytes. If four 8-bit width SDRAMs or two 16-bit width SDRAMs are used and the SDRAM bit width is 32 bits, 64/4 = 16 clocks are required to transfer 64 bytes of data. .
[0036]
The data is a macro block composed of a luminance signal Y and color difference signals Cr and Cb, and exists at the same row address as shown in FIG. Therefore, when the macroblock data is read from the SDRAM, the luminance signal Y and the color difference signals Cr and Cb are read simultaneously by one burst transfer by switching the column address to be read every two clocks and generating them. Reduce burst transfer of unnecessary data.
[0037]
Specifically, as shown in FIG. 2A, when an 81 MHz clock signal is output, as shown in FIG. 2B, when the bank 0 active command is output at the 34th clock, the macro In order to switch the column address of the block data, read commands RD ₁ , RD ₂ , RD ₃ , and RD ₄ are output every two clocks, that is, at 37, 39, 41, and 43 clocks, respectively. Specifically, for example, when reading the data of the macroblock shown in FIG. 8, the read commands RD ₁ , RD ₂ , RD ₃ , and RD ₄ have values 0, ₂ , 32, and 48 as column addresses. Assigned respectively. As a result, as shown in FIG. 2C, from the 40th clock to the 47th clock, the data of the macroblock in the bank 0 whose column address is switched is sequentially read.
[0038]
Similarly, when the bank 1 active command is output at the 42nd clock, the read commands RD ₁ , RD ₂ , RD ₃ , and RD ₄ are output at the 45th, 47th, 49th, and 51st clocks, respectively. As a result, the bank 1 data whose column address has been switched is sequentially read from the 48th clock to the 55th clock following the bank 0 data.
[0039]
The amount of data read out in this way is indicated by the hatched portion in the case of reading the data of 16 × 16 bytes of the thick line shown in FIG. 3 and reading only the data of 20 bytes in width and 24 bytes in length. It is not necessary to transfer 4 × 24 = 96 bytes of data. That is, a data transfer amount of (20 × 24) / (16 × 16) = 15/8 is sufficient. The reduction rate at this time is 17%.
[0040]
As a result, the data bus occupation period when data is transferred to the motion compensation circuits 7 and 8 is shortened, and the data can be distributed to other data processing data transfers accordingly.
[0041]
The motion compensation circuits 7 and 8 are supplied with the motion vector detected by the motion vector detection circuit 6, and the motion compensation circuits 7 and 8 perform motion compensation using the motion vector. The output from the motion compensation circuit 7 and 8, the predicted value N _E obtained are averaged by the adder 9. Further, the predicted value _NE is sent to the subtracter 10, the difference from the Nth frame image read from the frame memory 3 is taken, and the difference N _B is output to the terminal a of the signal switcher 11.
[0042]
Here, the signal switching unit 11 is switched by the B / I select signal input from the signal input terminal 2 and switches the output of the image signal of the B picture or the I picture.
[0043]
When B / I select signal indicating the output of the image signal of the B picture, the signal switching device 11 is switched to terminal a, the image compression is performed by the difference N _B obtained via the terminal a to the group.
[0044]
When the B / I select signal indicates the output of the image signal of the I picture, the image signal of the Nth frame image is output to the terminal b of the signal switch 11. The signal switch 11 is switched to the terminal b, and image compression is performed using a signal output via the terminal b.
[0045]
Any motion detection method may be used, but as a motion detection method, a difference between pixels is calculated between corresponding blocks, the difference is integrated in the block, and the block having the smallest integrated value is obtained. The method used for prediction is often used.
[0046]
The image signal switched and output from the signal switch 11 is subjected to DCT processing by the DCT circuit 12, and after the DCT coefficients are quantized by the quantization circuit 13, variable length coding is performed by the variable length coding circuit 14. Then, it is sent to the recording / encoding circuit 15 as image data.
[0047]
In the recording encoding circuit 15, the transmitted image data is recorded for recording after the error correction code and the synchronization identification information are added together with the motion vector information and the B / I select signal from the motion vector detecting circuit 6. Recording coding such as channel coding is performed.
[0048]
The recording-encoded signal is recorded on a tape (not shown) as a recording signal by a recording unit 16 including a recording amplifier and a head.
[0049]
Next, in the image signal decoding apparatus in FIG. 4 on the reproduction side, a recording signal is read from a tape (not shown) by a reproduction unit 21 including a reproduction head, an amplifier, and the like. The read signal is returned to the original channel coding in the recording / decoding circuit 22, and the error correction code, the motion vector information B / I select signal, and the like are separated.
[0050]
Thereafter, the decoded image data is subjected to variable length decoding by the variable length decoding circuit 23, is inversely quantized by the inverse quantization circuit 24, and is then subjected to an inverse discrete cosine transform (hereinafter referred to as IDCT) circuit 25. The IDCT process is performed and an image signal is output.
[0051]
Here, when the image signal of the decoded frame image is an image signal processed as an I picture on the recording side, the frame image signal of this I picture is signaled via a frame memory 26 made of SDRAM. It is output to the terminal b of the switch 33. The signal switch 33 is switched to the terminal b side by the B / I select signal separated by the recording / decoding circuit 22, and the image signal of the frame picture of the I picture is output from the signal output terminal 34 via the terminal b. The
[0052]
In addition, when the image signal of the decoded frame image is an image signal processed as a B picture on the recording side, the image signal is written in frame memories 26 and 27 formed of SDRAM. Specifically, if the currently decoded frame image is the (N−1) th frame image, the (N + 1) th frame image two frames before the (N−1) th frame image. The image signal of the Nth frame image one frame before is written in the frame memory 26. These frame memories 26 and 27 are controlled by a memory control circuit 28.
[0053]
As described above, the delayed image signal written in the frame memory 27 is read out by the same operation as the data reading in the above-described image signal encoding device, sent to the motion compensation circuit 29, and (N -1) The image signal of the first frame image is sent to the motion compensation circuit 30. The motion vectors separated by the recording / decoding circuit 22 are input to the motion compensation circuits 29 and 30, and motion compensation is performed using the motion vectors. The outputs from the motion compensation circuits 29 and 30 are added and averaged by an adder 31, and further, an image signal obtained by adding and averaging the image signal of the Nth frame image read from the frame memory 26 by the adder 32. Is output to the terminal a of the signal switch 33. The signal switch 33 is switched to the terminal a side by the B / I select signal from the recording / decoding circuit 22 and is output from the signal output terminal 34 via the terminal a.
[0054]
In the embodiment described above, the burst length is set to 8, but this burst length is not limited to 8.
[0055]
The number of column address switching clocks is not limited to 2, and may be 4, for example.
[0056]
【The invention's effect】
As is clear from the above description, the image signal encoding device according to the present invention fixes the burst length of the storage means, stores a plurality of types of image signals with different column addresses on the same row address, and Fewer burst transfers when reading data for motion compensation by having memory control means that outputs multiple read commands and sequentially switches multiple column addresses while specifying the row address with the active command This makes it possible to increase the use efficiency of the data bus.
[0057]
Also, the image signal decoding apparatus according to the present invention fixes the burst length of the storage means, stores a plurality of types of image signals on the same row address with different column addresses, and designates the row address with an active command. In this state, by having a memory control means that outputs multiple read commands and sequentially switches and designates multiple column addresses, it is possible to perform less burst transfer when reading motion compensation data. The use efficiency of the data bus can be improved.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of an image signal encoding device according to the present invention.
FIG. 2 is a diagram illustrating data read timing.
FIG. 3 is a diagram illustrating a read amount of data of a macroblock.
FIG. 4 is a schematic configuration diagram of an image signal decoding apparatus according to the present invention.
FIG. 5 is a diagram showing a timing at the time of random row reading of an SDRAM.
FIG. 6 is a diagram for explaining CAS latency;
FIG. 7 is a diagram illustrating a macroblock.
FIG. 8 is a diagram showing data on the same row address.
FIG. 9 is a diagram illustrating a data read amount of a conventional macroblock.
[Explanation of symbols]
3, 4 frame memory 5 memory control circuit 6 motion vector detection circuit 7, 8 motion compensation circuit 9 adder 10 subtractor 11 signal switcher 12 DCT circuit 13 quantization circuit 14 variable length coding circuit 15 recording coding circuit 16 recording Unit 21 Playback unit 22 Recording decoding circuit 23 Variable length decoding circuit 24 Inverse quantization circuit 25 IDCT circuit 26, 27 Frame memory 28 Memory control circuit 29, 30 Motion compensation circuit 31, 32 Adder 33 Signal switcher

Claims (4)

In an image signal encoding apparatus that writes an image signal into a storage means including a synchronous DRAM, reads out the written image signal, and performs compression encoding.
The burst length of the storage means is fixed, a plurality of types of image signals are stored on the same row address with different column addresses , and a read command is issued within the burst length with the row address designated by an active command. An image signal encoding apparatus comprising memory control means for outputting a plurality and sequentially switching a plurality of column addresses. 2. The image signal encoding apparatus according to claim 1, wherein the storage means is a frame memory used when performing motion vector detection and motion compensation signal processing. In an image signal decoding apparatus for writing and outputting decompressed and decoded image data to a storage means comprising a synchronous DRAM,
The burst length of the storage means is fixed, a plurality of types of image signals are stored on the same row address with different column addresses , and a read command is issued within the burst length with the row address designated by an active command. An image signal decoding apparatus comprising memory control means for outputting a plurality and sequentially switching a plurality of column addresses. 4. The image signal decoding apparatus according to claim 3, wherein the storage means is a frame memory used when performing motion vector detection and motion compensation signal processing.

Images