JP2826897B2 - Motion compensation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion compensation circuit used in a reproduction apparatus for an image signal encoded at a low bit rate by information compression.

2. Description of the Related Art Since an image, particularly a moving image, has a very large amount of information when digitized, it is recorded or transmitted after being encoded at a low bit rate by information compression.

For example, when recording a moving image on a CD-ROM, inter-frame predictive coding, inter-frame motion compensation, DCT transform, etc. are performed as low bit rate coding. CD in this way
-To reproduce an image signal recorded in the ROM, processing reverse to that of the recording system, that is, inverse DCT transformation, inter-frame addition, motion vector processing, and the like are performed.

Generally, in the case of a CD-ROM, an image signal (inter-frame difference signal) before inverse DCT conversion is provided with 16 lines of Y signal, 8 lines of RY signal and 8 lines of BY signal per packet, and usually 15 lines. One frame image is composed of packets. In a conventional reproduction system circuit, such an inter-frame difference signal is inverted.
On the other hand, the image signal of the previous frame is subjected to motion vector processing in an image memory for storing image signals of 15 packets (one frame) while performing DCT conversion, and the reproduced image signal of the previous frame after the motion vector processing is inverted. Adds the difference signal between frame memories after DCT conversion (addition between frames)
Thus, a reproduced image signal of the current frame is obtained.

[Problems to be Solved by the Invention] In the conventional reproducing system circuit as described above, a 15-packet image memory is used, and an image signal for 15 packets is stored in the memory to perform motion vector processing. A large memory circuit, an address operation unit, and the like were used.

The present invention has been made in view of the above problems, and has as its object to provide a motion compensation circuit that performs motion vector processing using a small-capacity image memory and a simple address calculation circuit.

[Means for Solving the Problems] In order to achieve the above object, the motion compensation circuit according to the present invention has 16 lines of Y signals, RY signals, and B-signals per packet.
Inverse DCT transforms the inter-frame difference signal in which each of the Y signals is transmitted by eight lines, and corrects the position in the previous frame of the moving area of the Y signal based on the motion vector. Is added to the reproduced image signal of the previous frame after the motion compensation to obtain the reproduced image signal of the current frame, in one line, one line of the Y signal and one line of the RY signal or the B-line. An image memory for storing Y signals and accumulating a total of 64 lines of Y signals and 32 lines of RY and BY signals, and this image memory functions as a ring memory for 64 lines. A write address generating means for generating a write address signal for causing the read address signal to have an offset of two packets with respect to the write address signal for a predetermined period. Means for generating a read address, means for adding a motion vector to a read address signal generated by a read address generating circuit, and alternately applying a write address signal and a read address signal obtained by adding the motion vector to the image memory. A write / read control unit for alternately performing a write operation and a read operation; and a FIFO memory for adjusting the delay amount of the entire motion compensation circuit to one frame.

[Operation] Although the image memory for motion compensation used in the present invention has a storage capacity of only 64 lines (4 packets), a write address generation unit, a read address generation unit, an addition unit, and write / read control are provided. By functioning as a ring memory by the action of the means or the like, it is possible to handle a large number of packets (for example, 15 packets). That is, the area in this memory is
If A, B, C, and D are separated by packets, the first 4
When the packets are sequentially written to A, B, C, and D, the next fifth and sixth packets are written to A, B, and so on. Then, reading is performed at a position two packets away from the writing position. Thus, for example, reading is performed at a position in the area B, and even if the reading position may reach the adjacent areas A and C by the motion vector processing, it does not reach the area D being written. As a result, the write and read motion vector processes are performed normally.

Embodiment FIG. 5 shows a configuration of a main part of a CD-ROM reproducing apparatus including a motion compensation circuit according to an embodiment of the present invention.

The recording medium of the CD-ROM 100 records image signals that have been compressed by various encoding processes such as DCT (Discrete Cosine Transform), variable length encoding, and motion compensation inter-frame prediction encoding. The image signal read from the CD-ROM 100 is temporarily stored in a buffer memory 104 via an interface 102, decoded by a variable-length code decoder 106, and then inverted by a DCT ^-1 (inverse discrete cosine transform) circuit 108. Receive conversion processing.

In the image signal input to the DCT- ¹ circuit 108, one block is composed of 8 lines × 8 pixels, and one packet is composed of 16 lines × 352 pixels (88 blocks) for a Y signal, an RY signal, and a B-signal.
Each of the Y signals is composed of 8 lines × 176 pixels (each of 22 blocks), and a frame of one frame is constituted by 15 packets. This image signal is a signal that completely represents the image content of one frame for a certain reference frame (usually, a frame immediately after a scene change) according to the inter-frame predictive coding. Each subsequent frame having a characteristic is a signal (inter-frame difference signal) indicating a difference from the previous frame. Also, Y
As for the signal, an X-direction component Vx and a Y-direction component Vy of a motion vector are added to each block. In the inverse DCT transform of the DCT- ¹ circuit 108, the pixel block represented in the frequency domain is transformed into the time domain, but the configuration of the image signal in one packet does not change.

The difference signal between frames output from the DCT- ¹ circuit 108 is
The signal is input to the adder 114, where it is added to the reproduced image signal of the previous frame from the motion compensation circuit 120. As a result, a reproduced image signal that uniformly represents the image content of the current frame is obtained at the output of the adder 114, and the reproduced image signal is written to the frame memory 118 and input to the motion compensation circuit 120. When a reproduced image signal of the reference frame is output from the DCT- ¹ circuit 108, the switch 116 is switched to the a side (value [0]), and the reproduced image signal passes through the adder 114 as it is, and is stored in the frame memory 118. Is supplied to the motion compensation circuit 120. Switching of the switch 116 is performed by the switch switching circuit 110.
Done by The motion compensation circuit 120 corrects the position of the motion area in the previous frame based on the motion vector (Vx, Vy) from the motion vector separation circuit 112. As described above, since the motion area portion of the previous frame is used by the motion vector, the image information of the current frame is compressed. The motion compensation circuit 120 according to the present embodiment has a
Motion compensation is performed using an image memory having a packet (64 lines) capacity.

FIG. 1 shows a configuration example of the motion compensation circuit 120. An 8-bit image signal (inter-frame difference signal) input from the output terminal of the adder 114 is delayed by a FIFO (first-in first-out) memory 10 for a certain period of time, and then the D-type flip-flop 14
, Is subjected to motion vector processing in the process of being read from the memory 16, and is then output to the input terminal side of the adder 14 via D-type flip-flops 18 and 20. Writing and reading of the FIFO memory 10 are controlled by the control circuit 12, and the delay time is selected so that the entire motion compensation circuit becomes one frame. As will be described later, it takes 2 packets time in the memory 16,
The delay time of the FIFO memory 10 is approximately [(1 frame) − (2
Packet)].

The memory 16 has an address configuration as shown in FIG. 2 and has a storage capacity for four packets. In the X direction, the Y signal and the C (RY / BY) signal are combined with 528 pixels, and in the Y direction, there are 64 lines, and one packet is stored in each of the areas A to D.
Write / read addressing is performed using a 16-bit address signal, of which the upper 6 bits specify the Y-direction address and the lower 10 bits specify the X-direction address.

Writing is repeatedly performed in the order of A → B → C → D.
That is, when four packets of image signals are written in A → B → C → D one by one, the next four packets are written again in A → B → C → D one by one.

Reading is performed on an area delayed by two packets from the writing area. To perform motion compensation, the X-direction component Vx and the Y-direction component Vy of the motion vector are added to the X-direction component (X address) and the Y-direction component (Y address) of the read address, respectively. Since the pixels have a data width of ± 15 lines, the readout area has a fluctuation width of ± 1 packet. Therefore, an offset of two packets is provided between the write area and the read area so that they do not conflict with each other. Further, the timing of writing and reading is such that writing is performed in the first half of a clock cycle and reading is performed in the second half.

FIG. 4 shows the relationship between writing and reading of the memory 16.
Assuming that one frame is composed of 15 packets P1 to P15, the packets P1 to P15 are A → B → C → D → A
The data is sequentially written in each area of B. Then, after a delay time of two packets, reading is sequentially performed for each area of A → B → C → D → A → B..., And packets P1 to P15 are sequentially read. At the time of reading, due to the motion vector processing, the read area (motion vector area) extends over the upper and lower areas (C, A) of the central area (for example, B), but does not extend over the area (D) being written.

As described above, the memory 16 functions as a ring memory having a capacity of 4 packets (64 lines), in which writing and reading are performed in parallel while maintaining an offset of 2 packets.
Motion vector processing is performed during the reading process.

Next, a control unit for causing the memory 16 to perform the above-described operation will be described with reference to FIG. 1 again. The control unit includes a counter 22, an address generator 24, a timing circuit 28, adders 36, 38, 40, D-type flip-flops 30, 32, 4
2, 44, an AND gate 26, an OR gate 34, and an address changeover switch 46.

The counter 22 responds to the frame synchronization signal by a clock.
CK counting is started, and a 16-bit output signal corresponding to each count value is generated. This counter output signal is input to the address generator 24, where the count value is stored in the memory 16
Is converted to a 16-bit address signal. As shown in FIG. 2, an image signal is written or read in units of one packet, and in each packet, first, eight pixels in a first row (line), then eight pixels in a second row (line),
.., And then addressing is performed in the order of eight pixels in the eighth row (line). The address generator 24 is, for example, a ROM
And outputs an address signal for performing such addressing.

The counter output signal is also provided to the timing circuit 28. When data is written to the last storage position of the area D of the memory 16, a timing signal is output from the output terminal OUT2 of the timing circuit 28 in response to the counter output signal at that time. As a result, the counter 22 is reset, the count output signal returns to the initial value [0], and the address signal of the address generator 24 also returns to the initial value (a value specifying the head storage position of the area A). ing.

The address signal from the address generator 24 is taken into the D-type flip-flop 32 and then applied to the D-type flip-flop 44 as a write address signal, and the upper 6 bits (Y address signal) for the read address signal Is added to the adder 36, the lower 10 bits (X address signal)
Is supplied to the adder 40. The 16-bit write address signal captured by the flip-flop 44 is supplied to the memory 16 via the switch 46 at a predetermined timing in response to the clock CK.
Is supplied to the address terminal ADR.

The upper 6 bits of the Y address signal input to the adder 36 are added with the offset value [32] for two packets.
When reading is performed for the area C or D, the offset value [32] is added to the Y address signal, and the data after the addition becomes 7 bits, and the limit value of the Y address of the memory 16 (the 64th line) ). Therefore, in the adder 36, the most significant bit of the 7-bit data is discarded (the address value [64] is subtracted). Then, the remaining 6-bit data becomes an address value in the area A or B which is offset by two packets from the value of the Y address signal before addition,
This is supplied to adder 38 as a read Y address signal.

In the adders 38 and 40, in order to perform motion vector processing,
The readout Y address signal (6 bits) and the readout X address signal (10 bits) have the Y-direction component Vy of the motion vector, respectively.
(5 bits) and the X-direction component Vx (5 bits) are added. By this motion vector processing, the readout position fluctuates in the X and Y directions within a range of ± 15 pixels and ± 15 lines around the reference position. Then, for example, when reading is performed on the area D of the memory 16, the value obtained by adding the Y-direction component Vy of the motion vector to the read Y address signal becomes 7-bit data and exceeds the address range of the memory 16. There is. Therefore, the most significant bit is discarded by the adder 38 (thus, the address value [64] is subtracted), and the remaining 6-bit data representing the position in the area A is output. On the other hand, in the X direction, at the stage of motion detection before recording, the X direction component Vx of the motion vector is set (defined) so as not to enter the C (RY / BY) area from the Y signal area. Therefore, the read X address signal (10 bits)
Is added to the X-direction component Vx (5 bits) of the motion vector and is 10-bit data, which is output as it is.

The read Y address signal and the read X address signal output from the adders 38 and 40 are stored in the upper 6 bits and lower 10 bits of the read address signal via the D-type flip-flop 42 and the address switch 46, respectively. 16
Address terminal ADR.

The address switch 46 is provided with a write / read control signal ▲ ▼ provided from the output terminal of the OR gate 34 to the memory 16.
In response to / RE, the control signal is “L” (write enable)
In this case, the terminal is switched to the terminal a, and when "H" (read enable), the terminal is switched to the terminal b. As shown in FIG. 3, the write / read control signal ▼ / RE goes “L” in the first half of the clock (CK) cycle and goes “H” in the second half. At the same time,
The write address signal and read address signal alternately
Given to.

In the present embodiment, since the common lower 10 bits obtained from the address generator 24 are used for the X-direction component of the address signal, the X-direction position for writing and the Y-direction position for reading (the center of the motion vector) in the memory 16 are used. Position) is the same, and address calculation and control are simplified.

The control signal ▼ provided from the D-type flip-flop 30 to the chip select terminal ▼ of the memory 16 is 1
This signal is an enable state ("L") for making the memory 16 accessible for each block (FIG. 3).
This control signal CS is generated by the timing circuit 28. Further, the image signal is alternately written to and read from the memory 16 in units of 8 bits. The timing for this is controlled as follows. That is, the output enable terminal of the D-type flip-flop 14 from the OR gate 34
Data is supplied from the flip-flop 14 to the memory 16 at the timing when the control signal ▲ / RE supplied to ▼ falls to “L”. Then, data is transferred from the memory 16 to the D-type flip-flop 18 at the timing when the inverted clock signal ▼ applied to the clock terminal CK of the D-type flip-flop 18 from the output terminal of the inversion circuit 48 rises to “H”.

[Effects of the Invention] The present invention has the following effects by having the above-described configuration.

An image memory having a storage capacity of 64 lines (4 packets) is made to function as a ring memory, and motion vector processing is performed while maintaining an offset of 2 packets between a writing position and a reading position. Small memory,
It is possible to obtain a motion compensation circuit including a simple address operation unit and the like.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of a motion compensation circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing an address configuration of a memory according to the embodiment, and FIG. 3 is a motion compensation circuit of the embodiment. FIG. 4 is a diagram showing the relationship between the writing and reading of the memory of the embodiment for one frame (15 packets), and FIG. 5 is a diagram showing the operation according to an embodiment of the present invention. Includes compensation circuit
FIG. 3 is a block diagram illustrating a configuration of a main part of the CD-ROM playback device. In the figure, 10 ... FIFO, 12 ... Control circuit, 16 ... Memory, 22 ... Counter, 24 ... Address generator, 28 ... Timing circuit, 36,38,40 ... Adder, 46 ... Address changeover switch, 108: DCT circuit, 120: Motion compensation circuit.

Claims (1)

(57) [Claims] 1. Y signal is 16 lines per packet, RY
The signal and the B-Y signal are each subjected to inverse DCT conversion between the inter-frame difference signals transmitted by eight lines, and the position in the previous frame for the moving region of the Y signal is corrected based on the motion vector. In the image reproducing apparatus which obtains a reproduced image signal of the current frame by adding the inter-frame difference signal of the current frame to the reproduced image signal of the previous frame after the motion compensation, a Y signal for one line per line and an R signal for one line -Y signal or BY signal is accumulated, and Y lines for 64 lines in total are stored.
An image memory for accumulating signals and RY signals and BY signals for each of 32 lines, and a write address signal for causing the image memory to function as a ring memory for 64 rows are generated at predetermined intervals. Address generating circuit for generating a read address signal having an offset of two packets with respect to the write address signal in a predetermined cycle, and a read address generated by the read address generating circuit Means for adding a motion vector to a signal; and writing the read address signal obtained by adding the write address signal and the motion vector to the image memory alternately to perform a write operation and a read operation alternately. A motion compensation circuit comprising: read control means; and a FIFO memory for adjusting the delay amount of the entire motion compensation circuit to one frame.