JP3033653B2 - Digital audio interface circuit and recording / playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital audio interface circuit and a recording / reproducing apparatus, and more particularly to a jitter absorbing function for absorbing jitter generated in digital audio data, and a sound skip caused by a shock in a mini disc player or the like. The present invention relates to a digital audio interface circuit having a function of controlling a shock-proof memory and a recording / reproducing apparatus including the same.

[0002]

2. Description of the Related Art When transferring digital audio data, a digital audio interface (hereinafter referred to as DAI) format is employed. Generally, in DAI, jitter occurs in digital data due to wiring and the like between a transmission side and a reception side. Jitter impairs the quality of digital audio data, so DA
In the I circuit, a jitter absorbing circuit that removes or absorbs this is employed.

[0003] A DAI circuit is employed in a recording / reproducing apparatus such as a mini-disc player for recording / reproducing digital audio data to / from a mini-disc and functions as a signal transmission circuit.
In a mini-disc (hereinafter, referred to as MD) or the like, for example, when a player receives an impact, the pickup may be separated from an original position due to the impact. In such a case, sound skips occur in the reproduced data and good audio data cannot be obtained. Therefore, a DAI circuit used in an MD player or the like employs a shock-proof memory control circuit (SPMC circuit) that suppresses sound skips. ) In the circuit. The SPMC circuit employs a method in which data read from an MD or the like is temporarily stored in a large-capacity RAM, and the stored data is sequentially read from the RAM and transmitted.

FIG. 4 shows the jitter absorbing circuit and the SPM.
1 shows an example of a mini-disc player including a conventional DAI circuit composed of a C circuit. Either an analog signal shown as an audio signal or a digital signal shown as a digital audio data (DAD) reception signal is input to an input portion of the player, and an audio signal is input to an output portion of the player. Either or both of the analog signal indicated as “1” and the digital signal indicated as the DAD reception signal are output.

DAD receiving circuit 41 for receiving a DAD signal
Includes a PLL circuit (not shown). When recording digital audio data, a DAI clock for reading the DAD signal is read from the received DAD signal.
The digital audio data is read out by being reproduced by the circuit. DIR reproduced by DAD receiving circuit 41
The signal and the DIR clock are input to the jitter absorbing circuit 42. The jitter absorbing circuit 42 has an RA for jitter absorption.
M43 is connected, and the output of the jitter absorbing circuit 42 is recorded on MD2 via MD signal processing circuit 3.

At the time of reproducing data recorded on the MD, M
The signal read from D2 by the pickup and reproduced by the MD signal processing circuit 3 is sent to the SPMC circuit 45.
The SPMC circuit 45 once writes data into the attached SPMC RAM 46 and reads it out after a predetermined time. With this configuration, even when the pickup separates from the disk due to an impact, the normal data is read again from the MD by utilizing the time difference between the data writing to the SPMC RAM 46 and the data reading, and the normal data is read from the SPMC RAM 4.
Write to 6. In this way, skips included in the read reproduction output, that is, the DAD transmission signal or the audio signal are suppressed.

FIG. 5 shows an example of the jitter absorbing circuit 42 shown in FIG. In FIG. 5, the jitter absorbing circuit includes a RAM interface 50, a CPU,
It basically comprises an interface 51, a serial / parallel conversion circuit 52, a parallel / serial conversion circuit 53, a write address register 54, a read address register 55, adders 56 and 57, an address comparison circuit 58, and a timing generator 59. The input audio data is temporarily stored in the jitter absorbing RAM 43 under the control of the CPU.

[0008] The write address register 54 is
3, and the read address register 55 stores a read address for the RAM 43.
From these registers 54 and 55, the write and read addresses are transferred to the RAM via the RAM interface 50.
43. Input data, which is a DIR signal passing through the serial / parallel conversion circuit 52, is sequentially written to the address of the RAM 43 specified by the write address register 54, and from the address of the RAM 43 specified by the read address register 55, The written data is read. The read data is
The signal is supplied as an MD recording signal to the MD signal processing circuit via the parallel / serial conversion circuit 53.

The registers 54 and 55 are initialized by a CPU signal passing through the CPU interface 51,
From the initial state in which an address having a predetermined offset is stored between the two, the outputs of the adders 56 and 57 attached thereto are sequentially applied, and the address is sequentially incremented. The operation timing of each of the registers 54 and 55 is controlled by a timing generator 59. When there is a difference between the periods of the write and read operation timings, for example, when the write timing is ahead of the read timing, the jitter is absorbed until the RAM overflows. On the other hand, when the write timing is later than the read timing, the jitter is absorbed until the addresses of both registers match.
The address comparison circuit monitors that both addresses maintain a predetermined offset, and when the two addresses are out of the predetermined offset range, temporarily controls the operation speed of the write address register 54, or By specifying the address separately, both registers 54,
Control is performed so that 55 addresses operate within a predetermined offset range.

The timing generator 59 is a circuit for generating a timing signal necessary for the entire jitter absorbing circuit.
The read timing for reading data from the RAM requires an accurate clock with no variation. From the timing generator 59, a so-called crystal clock generated by the crystal oscillation circuit of the MD signal processing circuit is used for reading. The timing is supplied to a read unit from the RAM 43 including the read address register 55.
In addition, the write portion to the RAM 43 including the write address register 54 has a timing generator 59
The DIR clock reproduced by the PLL circuit of the DA receiving circuit is supplied.

FIG. 6 shows an example of the configuration of the conventional SPMC circuit 45 shown in FIG. This SPMC circuit has the same configuration as the jitter absorption circuit except that it does not have an address comparison circuit.
Small capacity RAM for signal processing circuit to absorb jitter
It is adopted when it has. The MD signal processing circuit having the RAM for jitter absorption generates a crystal clock with a crystal oscillation circuit, and the crystal clock of the MD signal processing circuit is input to the timing generator 69 of the SPMC circuit as write timing. You. In this case, the MD reproduction signal read from the MD and input to the SPMC circuit is also synchronized with the crystal clock, and the write address register 64 and the read address register 65 operate at the same cycle. Therefore, a comparison circuit for comparing both addresses is not required.

FIG. 7 shows another example of the configuration of the SPMC circuit. In this SPMC circuit, the MD signal processing circuit
This is adopted when there is no small-capacity RAM for absorbing jitter in the read signal. M without jitter absorption function
The D signal processing circuit reproduces the PLL clock from the MD read data by the internal PLL circuit, and both the PLL clock and the crystal clock are input to the timing generator 79 of the SPMC circuit. Each clock is supplied from the timing generator 79 to the write address register 74 and the read address register 75, respectively. This SP
In the case of the MC circuit, an address comparison circuit 78 for comparing the addresses of the write address register 74 and the read address register 75 is required, similarly to the jitter absorbing circuit shown in FIG.

[0013]

In a conventional DAI circuit used for recording / reproducing of an MD or the like, two large-capacity RAMs are required for the jitter absorbing circuit and the SPMC circuit. Therefore, there are disadvantages such as an increase in the cost of the RAM, an increase in the complexity of a circuit for accessing the RAM, and an increase in the space for implementing the DAI circuit.

In view of the above, the present invention overcomes the drawbacks of a conventional DAI circuit employed in a recording / reproducing apparatus for recording / reproducing to / from an MD or the like, and has a simple configuration.
It is an object of the present invention to provide an AI circuit and a recording / reproducing apparatus having a simple configuration including the AI circuit.

[0015]

In order to achieve the above object, a digital audio interface circuit according to the present invention comprises a minidisk signal processor having a jitter absorbing function.
Recording / playback on a mini-disc via a logic circuit
In digital interface circuits,
Recording mode for recording to a disc and playback from a mini disc.
Switching for switching input data with playback mode for
Means and the contents are incremented for each writing from the set initial value.
Write address register that stores the RAM write address
Data writing unit with a
Recording mode for sound and playback from mini disc
Second switching means for switching input data with the reproduction mode
And the contents are incremented every time reading is performed from the set initial value.
Read address register for storing RAM read addresses
A data reading unit having a write address
The address of the register and the read address register.
An address comparison circuit for monitoring the offset;
Based on the output of the comparison circuit, the write address register
Offset of the address of the read address register and the read address register.
A register control unit for controlling the number of bits within a predetermined range; and a RAM.
RAM control to write or read to / from
Change timing of writing or reading to RAM
Digital audio having a timing change circuit
Interface circuit for recording,
Set the first switching means and the second switching means to the recording mode.
And the timing change circuit is configured to
Supplies a DIR clock and writes to the RAM,
A crystal clock is supplied to the data reading unit.
Jitter is absorbed by reading from the RAM.
In reproduction, the first switching means and the second switching
Switching means and the playback mode, and
The path is closed for both the data write section and the data read section.
Supply a listal clock to write to the RAM and
SPMC processing is performed by reading .

[0016] In addition, recording and reproducing apparatus of the present invention, the jitter
-Via the mini-disc signal processing circuit with absorption function
Recording / playback device for recording / playback on mini-disc
Recording mode and recording mode for recording to a mini disc
Playback mode and input data for playback from two discs
Switching means for switching between the two, and writing from the set initial value.
RAM write address, whose contents are incremented every time
Data write section having a write address register
And a recording mode and a mini disc for recording to a mini disc.
Switch input data with playback mode to play from disc
Second switching means, and each time the data is read from the set initial value.
To store the RAM read address whose contents are incremented
A data reading unit having an output address register;
A write address register and the read address register
Address comparison time to monitor the address offset of the
The address and the output of the address comparison circuit.
Address register and the read address register
To control the offset of the address within the specified range
To write or read data to and from the RAM
RAM control and writing or reading to or from the RAM
And a timing change circuit for changing the timing of the
An interface circuit for digital audio,
In recording, the first switching means and the second switching means
Set the step and the recording mode, the timing change circuit
A DIR clock is supplied to the data writing unit to
Write to RAM, crystal to read data
Reading from the RAM by supplying a clock
To perform jitter absorption, and in reproduction, the first switching
Means and the second switching means are set to a reproduction mode,
The timing change circuit includes the data writing unit and the data
A crystal clock is supplied to both the
SPMC processing by writing and reading to AM
And a digital interface circuit for performing the following.

[0017]

In the digital audio interface circuit of the present invention, the jitter absorbing function and the SPMC function are
Since the operation is performed by a common RAM and a write unit and a read unit that form a control unit thereof, both functions are performed by only one set of the RAM and the R.
This is achieved by the AM control unit, and the configuration of the digital audio interface circuit is simplified.

In the recording / reproducing apparatus of the present invention, the adoption of the digital audio interface circuit having the above-mentioned action allows the RAM for jitter absorption and the RAM for SPMC to be used in common. , The overall circuit configuration is simplified.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS The invention will be further explained with reference to the drawings. FIG.
1 shows the configuration of an MD recording / playback apparatus including a digital audio interface circuit according to an embodiment of the present invention. Referring to FIG. 1, the recording / reproducing apparatus includes a DAI circuit 1 according to an embodiment of the present invention, a first signal output unit and a second signal input unit, and the DAI circuit 1 and the MD 2 MD signal processing circuit 3 for transmitting and receiving signals, large-capacity RAM 4 for DAI circuit 1, DA receiving circuit 5A and A / D converter 5B constituting first signal input unit 5, and second signal output unit 6, a DA transmission circuit 6A and a D / A converter 6B
The digital audio data is recorded / reproduced to / from the MD2 by operating in the recording mode or the reproduction mode.

At the time of recording audio data on the MD2, an input signal input for recording is configured as either an analog audio signal or digital audio data.
The signal is converted into a digital signal by the
It is given to the DAI circuit 1 as a recording signal to D. In the case of digital audio data, the digital audio data is received by the DA receiving circuit 5A and is similarly converted into a DIR signal.
It is provided to the AI circuit 1.

The DA receiving circuit 5A has a PLL circuit (not shown) therein, reproduces a DIR clock from a DA receiving signal input as digital data, and supplies this clock and the DIR signal to the DAI circuit 1. DAI
The circuit 1 is further supplied with a crystal clock from the MD signal processing circuit 3, and the DAI circuit 1 absorbs jitter contained in input data and transmits the data to the MD signal processing circuit 3. The MD signal processing circuit 3 determines M based on this signal.
Data recording is performed on D2.

The MD signal processing circuit 3 includes therein a jitter absorption circuit including a small capacity RAM for jitter absorption.
A reproduction signal read from D and obtained by absorbing jitter and a crystal clock used to obtain the reproduction signal are supplied to the DAI circuit 1. The DAI circuit 1 performs signal processing for preventing sound skipping occurring in the reproduced signal, and then performs the signal processing on the D signal constituting the output unit 6.
The A transmission circuit 6A and the D / A converter 6B. The reproduction signal is output as an analog audio signal from the D / A converter 6B, or is supplied from the DA transmission circuit 6A as digital audio data to another signal processing circuit.

FIG. 1 shows the configuration of the DAI circuit 1 shown in FIG. The DAI circuit includes a RAM interface 31, a CPU interface 32,
A writing section 10 for writing to the AM, a reading section 20 for reading from the RAM, an address comparison circuit (address comparison and control circuit) 33 for monitoring and controlling the offset between the write address of the writing section 10 and the read address of the reading section 20; It comprises a timing generator 34 and a timing selector 35. The writing unit 10 includes an input selector 11 for switching input data, and a serial /
The reading unit 20 includes a parallel conversion circuit 12, a write address register 13, and a write unit adder 14. The read / write unit 20 includes a read / address register 21, a read unit adder 22, and a read / data transfer unit. 2
3 and an output selector 24.

The address comparing circuit 33 is a circuit for monitoring that the address outputs of the write address register 13 and the read address register 21 have a predetermined offset, and has a function of maintaining the offset of both addresses within a predetermined range. Have. The timing generator 34 controls the write timing for controlling the write unit 10 and the read unit 20.
And the read timing for controlling the write unit 10
Alternatively, it is supplied to the reading unit 20.

When data from the DA receiving circuit 5A (FIG. 2) is recorded on the MD, the writing unit 10 is supplied with the DIR clock reproduced by the PLL circuit of the DA receiving circuit, and the reading unit 20 is supplied with the MD clock. A crystal clock for MD signal processing generated by the signal processing circuit is supplied. When reproducing data from the MD, the writing unit 10
The reading unit 20 is supplied with the crystal clock of the MD signal processing circuit. Switching of these timings is performed by a timing selector 35 attached to the timing generator 34.

An overflow signal is input to the timing generator 34 from the MD signal processing circuit. This signal is output when the small-capacity RAM for error correction and jitter absorption provided in the MD signal processing circuit overflows. When this signal is output, the writing from the writing unit 10 to the RAM 4 is stopped until the pickup returns to the original position and normal data is input. Although FIG. 1 shows an example in which the overflow signal is independently input from the MD signal processing circuit to the timing generator 34, the overflow signal may be input via the CPU interface 32.

When the DIR signal and the DIR clock are supplied from the DA receiving circuit to the DAI circuit for recording the digital audio signal, the timing generator 34
Write addresses to the RAM 4 are sequentially generated based on the timing of the DIR clock, and read addresses from the RAM are sequentially generated based on the crystal clock. The address comparison circuit 33 manages an overflow of the RAM 4 which occurs when the jitter of the DIR signal is large. For example, if the operation timing of the write address register 13 is delayed and the addresses of the write address register 13 and the read address register 21 match,
The address comparison circuit 33 transmits the coincidence signal to the MD signal processing circuit,
Temporarily speeds up the operation timing.

When the operation timing of the write address register 13 advances and the RAM 4 overflows, the address of the write address register is set to be delayed. As a result, the offset value between the two registers 13 and 21 is maintained within a predetermined range. In this way, the DAI circuit converts the data to M while absorbing jitter.
The data is sent to the D signal processing circuit 3 and the data is recorded on the MD 2 via the MD signal processing circuit 3. Note that, instead of the configuration in which the address comparison circuit 33 directly controls the register, for example, an address match signal is supplied from the comparison circuit 33 to the CPU,
The address value of the register or the operation timing can be controlled by the CPU. In this case, the response speed is somewhat lower than in the example described above.

At the time of reproducing data from the MD, both the write address register 13 and the read address register 21 operate at the same timing, so that if there is no skip, the initially set offset is maintained. In addition, when skipping occurs, the overflow signal
The signal is supplied from the MD signal processing circuit to the timing generator 34. At this time, the DAI circuit temporarily stops writing to the RAM 4, and then restarts writing after normal data is input. The read address register 21 determines whether or not the write address register 13 has stopped writing.
Reading from AM4 is continued. In this way, by using the address offset between the two registers, the skipped sound generated at the time of impact is removed, and reproduced data with good timing and accurate timing can be obtained.

FIG. 3 shows a DAI circuit according to a second embodiment of the present invention. The DAI circuit of this embodiment corresponds to both the MD signal processing circuit having the jitter absorbing function described above and another type of MD signal processing circuit having no jitter absorbing function. In FIG. 3, when the MD signal processing circuit has a jitter absorbing function, the crystal selector of the MD signal processing circuit is selected by the timing selector 35 during data reproduction.

When the MD signal processing circuit does not have a jitter absorbing function, the PLL clock reproduced by the PLL circuit of the MD signal processing circuit is used as the timing selector 35.
Is selected at the time of reproduction of data from the MD.
The data is RA based on the PLL clock of the signal processing circuit.
To write to M4 and read data from RAM4,
A crystal clock generated by an MD signal processing circuit or the like is used. As a result, the DAI circuit also absorbs jitter caused by fluctuations in the rotation of the MD during data reproduction. Also, regardless of which clock is selected, it has the same SPMC function as the DAI circuit of FIG.

As described above, the DAI circuit of the embodiment of the present invention and the DAI circuit of the recording / reproducing apparatus of the embodiment of the present invention provide a function of absorbing jitter from recorded data including jitter, and reproducing data such as MD. The SPMC processing function for removing the sound skip that occurs in the
The configuration of the DAI circuit and the recording / reproducing apparatus can be simplified by performing the processing using hardware including the M control circuit. Also, by adopting common hardware, it is possible to simplify the access to the RAM, to reduce the number of accesses itself, to suppress unnecessary signal radiation caused by the access to the RAM, and to realize a circuit. There is also an advantage that the space for the space can be reduced.

Although the present invention has been described based on the preferred embodiment, the present invention is not limited to the configuration of the above embodiment, and various modifications and changes can be made from the above embodiment. is there.

[0034]

As described above, according to the digital audio interface circuit and the recording / reproducing apparatus of the present invention, the jitter absorption function and the SPMC function are performed by the common RAM and the RAM control unit.
And the structure of the digital audio interface circuit can be simplified, and the space for implementing the circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital audio interface circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a recording / reproducing apparatus according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a digital audio interface circuit according to another embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional recording / playback apparatus.

FIG. 5 is a block diagram showing a configuration of a conventional jitter absorption circuit.

FIG. 6 is a block diagram illustrating an example of a configuration of a conventional SPMC circuit.

FIG. 7 is a block diagram showing another example of the configuration of a conventional SPMC circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Digital audio interface circuit 2 MD (mini disk) 3 MD signal processing circuit 4 RAM 5 Input part 5A DAD receiving circuit 5B A / D conversion circuit 6 Output part 6A DAD transmission circuit 6B D / A conversion circuit 10 Writing part 11 Input Selector 12 Serial / parallel conversion circuit 13 Write address register 14 Adder 20 Read unit 21 Read address register 22 Adder 23 Parallel / serial conversion circuit 24 Output selector 31 RAM interface 32 CPU interface 33 Address comparison circuit 34 Timing generator 35 Timing selector

Continuation of front page (56) References JP-A-5-217288 (JP, A) JP-A-5-89601 (JP, A) JP-A-5-217339 (JP, A) JP-A-1-2922673 (JP) , A) JP-A-3-39945 (JP, A)

Claims (4)

(57) [Claims] 1. A mini disc signal having a jitter absorbing function.
Recording / playback on a minidisk via a signal processing circuit
Digital interface circuit
Recording mode for recording to disk
The first mode for switching the input data with the playback mode for generating
The switching means and the contents are incremented every writing from the set initial value.
Write address for storing RAM write address
Writing unit having a register and a mini disk
Recording mode for recording to and playback from the mini disc
Switching means for switching input data with playback mode for
The step and the contents are incremented by every reading from the set initial value.
Address register for storing RAM read addresses
A data read unit having a write address and a write address
Register and the address of the read address register.
An address comparing circuit for monitoring an offset, and the address
The write address register based on the output of the
Of the address of the read address register and the read address register
A register control unit for controlling the set within a predetermined range;
RAM control for writing to or reading from M;
Change the timing of writing to or reading from the RAM
Digital audio with a timing change circuit
Interface circuit for audio
The first switching means and the second switching means are in a recording mode.
And the timing change circuit writes the data.
Supply DIR clock to section and write to RAM
Supply a crystal clock to the data reading section
And read from the RAM to absorb jitter
And the first switching means and the second
The switching means is set to the reproduction mode, and the timing change is performed.
The circuit further includes a data writing unit and a data reading unit.
Supply a crystal clock to the RAM and write to the RAM
A digital interface circuit for performing SPMC processing by performing reading and reading . 2. A mini-decoder via a mini-disc signal processing circuit.
Digital interface for recording and playing back discs
In the base circuit, recording for recording to the mini disc
Mode and playback mode for playback from mini disc
First switching means for switching input data;
RAM write address, whose contents are incremented every write from the initial value.
Data having a write address register for storing dresses.
Data writing section and recording mode for recording to mini-disc
And the playback mode for playback from the mini disc.
Second switching means for switching data, and whether the set initial value
RAM read address whose contents are incremented each time data is read
Data having read address register storing data
The write address register and the read address.
Address that monitors the offset of the address of the address register
Address comparison circuit and an output of the address comparison circuit.
The write address register and the read address
Register address offset within specified range
Register control unit, and write / read to / from RAM
RAM control for reading, writing or writing to the RAM
Is a timing change circuit that changes the read timing
Digital audio interface circuit comprising:
In recording, the first switching means and the second
2 is set to the recording mode with the switching means
The change circuit supplies a DIR clock to the data writing unit.
And write it to the RAM, and to the data readout unit
Supply crystal clock and read from RAM
Is performed to perform jitter absorption, and in reproduction, the
Set the first switching means and the second switching means to the reproduction mode.
Set, the mini disk signal processing circuit absorbs jitter
If it has a function, the timing change circuit
Both the data writing section and the data reading section
Supply lock to write and read to / from the RAM
The SPMC processing is performed by performing
If the processing circuit does not have a jitter absorbing function,
The timing change circuit sends the mini data to the data write section.
PLL signal generated by the PLL circuit of the disk signal processing circuit.
Supply lock to write to the RAM and read data
A crystal clock is supplied to the output unit to
Readout from Jitter to reduce jitter and SPMC processing
Digital interface circuit characterized by performing . 3. A mini-disc signal having a jitter absorbing function.
Recording / playback on a minidisk via a signal processing circuit
Recording on a mini-disc in a recording / playback device
Recording mode for playback and playback mode for playback from a mini disc.
First switching means for switching input data with the code, and setting
RAM contents in which the contents are incremented each time writing is performed from the initialized initial value
And a write address register for storing embedded addresses.
Data writer and recording for recording to mini disc
And a reproduction mode for playback from the sound mode and a mini disk
Second switching means for switching the input data of
For RAM read where the contents are incremented every time read from the initial value
A read address register for storing an address.
Data read unit, the write address register and the
Monitors the address offset of the read address register
Address comparing circuit and an output of the address comparing circuit
The write address register and the read
The address offset of the address register
Register control part to control inside and write to RAM
RAM control for reading or reading, and writing to the RAM
Timing for changing write or read timing
Interface for digital audio having a change circuit
A first switching means for recording.
And the second switching means are set to a recording mode.
The timing change circuit sends a DIR clock to the data write section.
And write the data to the RAM and read the data.
The crystal clock is supplied to the memory and the RAM
Jitter is absorbed by reading, and the
And reproduces the first switching means and the second switching means.
Mode, and the timing change circuit
Both the write section and the data read section have a crystal clock.
To write and read data to and from the RAM
Digital interface that performs SPMC processing
A recording / reproducing device comprising a circuit . 4. A mini disk signal processing circuit through a mini disk signal processing circuit.
A recording / playback device that records and plays back discs
Recording mode and mini disc for recording to a mini disc.
Switch input data with playback mode to play from disc
The first switching means which obtains data from the set initial value and
To store RAM write addresses whose contents are incremented
A data write unit having a write address register;
Recording mode and mini disc for recording to disc
Switch the input data with the playback mode for playback from the
2 switching means and contents every time read from the set initial value
The read address that stores the RAM read address at which the
A data reading unit having a dress register;
Address register and the read address register.
An address comparison circuit that monitors an address offset;
Based on the output of the address comparison circuit, the write
Address register and the read address register.
Control to control the offset of the address within a specified range
Unit that writes or reads data to or from RAM
M control and the timing of writing to or reading from the RAM
Having timing change circuit for changing timing
Interface circuit for audio
The first switching means and the second switching means
Set to recording mode, and the timing change circuit
A DIR clock is supplied to the data
To the data readout section and the crystal clock to the data readout section.
Reads from the RAM by supplying a
And in the regeneration, the first switching means and
Setting the second switching means and the reproduction mode to
When the disk signal processing circuit has a jitter absorption function
The timing change circuit is provided in front of the data writing unit.
Supply a crystal clock to both the data reading section
By writing and reading to and from the RAM, the SPM
C processing and the mini disc signal processing circuit
-In case of not having the absorption function, the timing change circuit
Indicates the mini disc signal processing circuit to the data writing unit.
Supply the PLL clock generated by the PLL circuit
Write to the RAM and Chris to the data readout
Read from the RAM by supplying a clock
Digital input to perform jitter absorption and SPMC processing.
A recording / reproducing device comprising an interface circuit .