JPH05217339A - Data reproducing device - Google Patents

Abstract

PURPOSE:To display and control an audio output signal in conformity with timing while a storage capacity is effectively utilized from a buffer RAM where only main data is stored. CONSTITUTION:Data read out of a disk 1 is decoded by a signal processing part 4 to take out its main data, which is then controlled of write/read on the buffer RAM 6 by a RAM controller 5, so that the main data is sent to a D/A converter 7 at a constant rate and is outputted via an LPF 8. A delay amt. between write and read is evaluated by a system controller 10 based on a data amt. stored in the buffer RAM 6, and time information and control information of subcode data from the signal processing part 4 are delayed by this delay amt., and are displayed on a display part 11, or are controlled for a changeover to the LPF 8, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing apparatus for storing data read from a recording medium in a memory, reading the data from the memory at a constant rate and reproducing the data.

[0002]

2. Description of the Related Art Generally, in a tape recorder, a disc player or the like for recording and / or reproducing a digital audio signal or a digital video signal, the recorded digital signal is digital audio data which has been subjected to error correction coding processing or interleave processing. Many have main data such as digital video data and auxiliary data such as address information and control information. For example, in a so-called compact disc (CD) format, stereo left and right two-channel audio signals are sampled at 44.1 kHz and quantized with 16 bits to produce an audio PCM signal, and a CIRC (cross.
Interleaved Reed-Solomon code) is used as main data. This main data contains auxiliary information, such as identification information indicating whether the song is in-between songs or a song number (track number), elapsed time within a song (lap time), absolute time (absolute time), emphasis control, etc. The subcode data is added to form recording data, and the recording data is modulated by the EFM (8-14 modulation) method to form a recording signal.

When a compact disc (CD) having such a format is reproduced by a normal reproducing apparatus, a PLL is generally used from an EFM signal read from the disc.
A clock component is detected (clock reproduction) using a (phase locked loop) configuration, binary data is taken in by the reproduced clock, and EFM signal demodulation is performed.
The data after EFM demodulation is usually RA for decoding processing.
M is used to perform error correction based on CIRC and decoding (decoding) processing including deinterleaving to obtain a digital audio signal (PCM signal). Data is written to the decoding RAM in synchronization with the PLL reproduction clock, and data is read out in synchronization with a clock from a reference oscillator such as a crystal oscillator. The digital audio PCM signal obtained by the decoding process becomes an analog audio signal via a D / A converter and a low pass filter (LPF).

By the way, a data reproducing device, especially the above-mentioned CD
In a device equipped with an optical pickup such as a player, mechanical disturbance such as shock or vibration to the device causes
The servo system such as the focus servo and tracking servo of the optical pickup may be disconnected, and normal data reproduction may not be performed. In this case, it is impossible to deal with the error correction as described above, and there is a possibility that the reproduction is temporarily interrupted.

Therefore, the applicant of the present application has previously described that in the specification and drawings of Japanese Patent Application No. 3-25566, the reproduction data is stored in a relatively large capacity RAM for buffer and read at a constant rate. And the RAM for the buffer
By always storing a predetermined amount or more of reproduced data in the buffer, even if normal data cannot be obtained from a medium such as a disk due to a read error or the like, the buffer R
A system is proposed in which the data stored in the AM is read to compensate for interruptions in the reproduced signal such as sound breaks.

As such a system, for example, in the case of the compact disc reproducing apparatus as described above, data is read from the disc at high speed in bursts (intermittently) and sequentially written in the buffer RAM.
To read data continuously from the
When writing data to the buffer RAM, it is necessary to control the write address and store adjacent data in the RAM in a continuous state. Specifically, for example, the disc is rotationally driven at a rotation speed that is about twice or three to four times the standard rotation speed, and the data read from the disc is recorded in a sub-coding frame (sub-code block, 13.3 msec for standard reproduction). It is conceivable to write the data into the buffer RAM as a unit.

[0007]

By the way, a data reproducing device using such a buffer RAM, such as a CD, is used.
In the player, at least the data corresponding to the data stored in the buffer RAM is provided between the data read from the disc and the signal (music, etc.) read from the buffer RAM and currently being reproduced. There is a time difference of. Further, the decoded main data (PCM data) itself has auxiliary information such as the subcode data, that is, information such as a song number (track number), absolute time, in-time (lap time), de-emphasis and the like. Etc. are not left.

Therefore, the subcode data read from the disc is used to display the song number and time of the reproduced music,
Alternatively, if the de-emphasis is controlled, the time difference causes a deviation from the music that is actually being reproduced, resulting in unnatural display or unnatural de-emphasis switching.

Here, not only the main data but also the auxiliary data (subcode data etc.) is directly used as a buffer RAM.
However, the storage capacity of the main data is reduced correspondingly, and the writing / reading process and the configuration are complicated, which is not preferable.

The present invention has been made in view of the above circumstances, and is a data reproducing apparatus for controlling writing / reading of main data read from a medium such as a disk and reproduced to a buffer memory. In the data reproducing device, the main data read from the buffer memory can display time information and the like having an accurate correspondence, and control such as de-emphasis switching can be performed at correct timing. For the purpose of provision.

[0011]

SUMMARY OF THE INVENTION A data reproducing apparatus according to the present invention is a data reproducing apparatus for reading recorded data from a recording medium having recorded data in which auxiliary data is added to main data and reproducing the main data. In the apparatus, a signal processing means for separating the main data and the auxiliary data from the recording data read from the recording medium, a buffer memory for storing the separated main data, and a buffer memory for the buffer memory. Memory control means for controlling writing / reading of the main data, a delay amount between writing / reading according to the amount of reproducible data stored in the buffer memory, and the signal processing means. Based on the time-related information obtained from the auxiliary data, the time-related information of the main data read from the buffer memory By having a control means for calculating, to solve the problems described above.

Further, the data reproducing apparatus according to the present invention, as the control means, obtains a delay amount between writing and reading in accordance with the amount of reproducible data stored in the buffer memory, and calculates the signal. The above problem is solved by delaying the control information signal obtained from the auxiliary data from the processing means by the amount of the delay amount to control the main data read from the buffer memory.

Here, the buffer memory has a memory space of a ring-shaped address, and the delay amount (time difference) is determined according to the address difference from the write address to the read address. The auxiliary data is, for example, subcode Q data in a so-called CD format, and the subcode Q data includes absolute time information from the head position of the disc,
It includes time-related information such as elapsed time (lap time) information, music number (track number) information, index number information and the like for each music, and control information such as emphasis information.
When displaying such time information or number information or performing control such as de-emphasis switching, the information of the obtained sub-code Q data is displayed after being delayed by the delay time in the buffer memory. You can let them do the control. Here, the time information such as the absolute time and the elapsed time in the song (lap time) is obtained by subtracting the delay time from the value of each time information obtained from the auxiliary data (subcode Q data). You can

Further, the amount of reproducible data stored in the buffer memory is displayed, and the pause and A
It is preferable to obtain the time-related information in consideration of the delay amount even during special reproduction such as -B repeat.

[0015]

The time-related information whose timing coincides with the main data actually read out from the buffer memory is obtained, and control such as de-emphasis switching is performed.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a device of one embodiment in which a data reproducing device according to the present invention is applied to a so-called compact disc (CD) player. That is, the optical disc 1 has a so-called C
Recorded data in D format is recorded. Briefly explaining this so-called CD format, 1
The upper and lower 8 bits of 16-word PCM digital audio data are separated into a symbol that is an error correction coding unit.
(Cross interleaved Reed-Solomon code) adds error correction parity and interleaves. A total of 32 symbols of 24 symbols of this CIRC-encoded audio data and 8 symbols of parity
Main data of symbol is one recording unit (frame)
Then, a so-called sub code, which is 8-bit auxiliary data, is added to this, so-called EFM (8-14 modulation).
By being modulated by the method and adding the frame synchronization pattern, one frame is recorded on the optical disc 1 as an EFM signal of 588 channel bits.
The sub-code is made up of one block (sub-coding frame) in 98 frames and carries auxiliary information for eight channels P to W. The Q channel of this subcode contains auxiliary data such as the song number, index number, elapsed time within the song, and absolute time.

In FIG. 1, the optical disk 1 is rotationally driven by the drive motor 13 at a speed (for example, twice the speed) higher than the standard speed (linear speed), and the optical pickup 2 intermittently or bursts signals. It is read, amplified by the preamplifier 3, and sent to the signal processing unit 4 as a so-called RF signal. This RF signal is a signal modulated by the EFM method described above, and the signal processing unit 4 performs processing such as EFM demodulation, deinterleaving, error correction, interpolation, and subcode decoding, and the main data ( Audio PCM data) output is from the RAM controller 5
It is stored in the buffer RAM 6 via. The data transfer rate up to this point is higher than the standard reproduction rate (for example, double the rate) in response to the high-speed disk rotation drive. However, the reading of data from the optical disc 1 is performed intermittently or in a so-called burst manner, and even if the instantaneous data transfer rate is higher than the standard, the average rate including the read pause period is almost standard playback. It is a rate. In this way, the data sent to and accumulated in the buffer RAM 6 intermittently or in bursts is continuously read out at a standard reproduction rate by the RAM controller 5, and the D / A converter 7, LP
By passing through an F (low-pass filter) 8, an analog audio output signal is taken out.

The servo control circuit 9 includes, for example, a focus servo, a tracking servo, a spindle motor servo,
The sled (head movement) servo and other control operations are performed. That is, the focus servo controls the focus of the optical system of the optical pickup 2 so that the focus error signal becomes 0, and the tracking servo controls the tracking of the optical system of the optical pickup 2 so that the tracking signal becomes 0. Further, the spindle motor servo controls the rotation of the spindle motor 13 so that the optical disc 1 is rotationally driven at a predetermined linear velocity (for example, a standard double linear velocity). Further, the sled servo controls the movement of the optical pickup 2 to the target track position of the optical disc 1 designated by the system controller 10. The servo control circuit 9 that performs such various control operations sends information indicating the operating state of each unit controlled by the servo control circuit 9 to the system controller 10.

The system controller 10 stores a CPU (central processing unit) such as a microprocessor for controlling the operation of each unit, a ROM (read only memory) in which a control program executed by this CPU is stored in advance, and various data. RAM for writing / reading and temporary storage
It is a so-called microcomputer system configured by including a (random access memory) and an I / O (input / output) circuit that transmits and receives various signals between the CPU and the outside. The system controller 10 includes a display unit 11 for displaying the operation state of each unit and a key input operation unit 12 for instructing various operations.
Etc. are connected. The display unit 11 includes, for example, an LCD
(Liquid crystal display), LED (light emitting diode) display device,
An FL display device, a plasma display device, or the like is used. The key input operation unit 12 is provided with various operation keys such as a play button, a stop button, and a fast-forward button. In addition, the system controller 10
Sends and receives signals to and from the signal processing unit 4 and the RAM controller 5 to control the operations of the signal processing unit 4 and the RAM controller 5.

Here, for example, when a cause such as a disturbance of the servo system due to a disturbance or the like causes the reproduction signal to be interrupted, that is, specifically, for example, a) out of focus, b) subcode Q data When it becomes discontinuous, c) when the PLL system becomes unstable for a certain period of time, d) when interpolation processing is performed (interpolation flag is raised), etc. Monitor and
The writing to the buffer RAM 6 is interrupted. And
After the servo system is restored, for example, the address immediately before the interruption of the reproduction signal is accessed, and writing is restarted from that address position. As a result, continuous reproduction output can be obtained unless the data stored in the buffer RAM 6 becomes empty. Further, even when the data stored in the buffer RAM 6 becomes full, the writing to the RAM 6 is temporarily stopped and the pause operation or the like is started.

By the way, the RF signal input to the signal processing unit 4 is synchronized with a so-called PLL system clock including uneven rotation of the optical disc 1, whereas the main data output to the RAM controller 5 is: Since it is synchronized with, for example, a so-called crystal system clock as a reference clock, jitter exists between the two. For this reason,
If the timing of starting writing to the buffer RAM 6 depends on the absolute time obtained by decoding the so-called sub-code Q data in the signal processing unit 4, a connection error such as data loss or duplication occurs. Therefore, a data comparison block is provided in the RAM controller 5, and data of the last several samples of the data written in the buffer RAM 6 and the RA from the signal processing unit 4 are stored.
The data sent from the M controller 5 to the RAM 6 are compared with each other, and the data from the signal processing unit 4 is written to the buffer RAM 6 at the timing when these data match.

That is, FIG. 2 shows a specific example of the signal processing section 4, and FIG. 3 shows a specific example of the RAM controller 5. In FIG. 2, the RF signal from the preamplifier 3 is sent to the EFM demodulation circuit 21, the synchronization detection circuit 22 and the PLL / timing generation circuit 23, respectively. The EFM demodulation circuit 21 demodulates the RF signal modulated by the EFM system, and sends the main data signal to the data bus DB and the subcode data signal to the subcode Q processing circuit 24. The synchronization detection circuit 22 detects the sub-coding frame synchronization signal and sends it to the PLL / timing generation circuit 23. PLL / timing generation circuit 23
Detects the channel bit clock (EFM clock) component of the RF signal and locks the PLL, and
The channel bit clock is divided by using the sub-coding frame synchronization signal to generate a word clock, a bit clock of data after EFM demodulation, and the like, and a write clock WCK is read / write control circuit 27. Send to. The PLL / timing generation circuit 23 outputs a sub-coding frame synchronization signal or the like for use in, for example, a spindle servo. Subcode Q data and the like are serially output from the subcode Q processing circuit 24 and used as current position information of the optical pickup 2 on the optical disc 1.

The main data (audio data and parity data for error detection and correction) sent from the EFM demodulation circuit 21 to the data bus DB includes a PLL / timing generation circuit 23 containing a jitter component due to uneven rotation of the optical disc 1. Data is written in the decoding processing RAM 26 by the read / write control circuit 27 in synchronization with the write clock WCK from. Thereafter, while the read / write control circuit 27 controls the read / write to the decoding processing RAM 26, error detection / correction processing and deinterleave processing are performed by the error correction processing circuit 25 based on the CIRC. .. The decoding processing RAM 26 is
In addition to the capacity required for RC decoding (for example, about 108 frames), it has a capacity for allowing a predetermined (for example, ± 24 frames) margin to absorb the above jitter. For example, a 32 kbit RAM is used. Be done. The decoded main data (PCM data) has a timing generation circuit 2 including a reference oscillator such as a crystal oscillator.
In synchronization with the read clock RCK from 9, the read / write control circuit 27 reads from the decoding processing RAM 26 and sends it to the interface circuit 28. From the interface circuit 28, the decoded main data, the bit clock BCK, and the word clock W are input.
Various clocks such as DCK, LR (for switching stereo left and right channel words) clock LRCK, etc. are output, and the RAM controller 5 and the system controller 10 are output.
Etc. Here, the write / read operation is intermittently performed at a speed higher than the standard, for example, double speed.

Next, referring to FIG. 3, the signal processing circuit 4
The input data from (the interface circuit 28 of) is
16 sample PCM sent to register 31
It is stored as data, and the system controller 10
Is permitted to write data, the data is written in the buffer RAM 6 according to the write address output from the address generation circuit 34 via the data selector 32. At this time, data writing is intermittently performed at a speed faster than the standard. Data is read from the buffer RAM 6 via the data selector 32 in accordance with the read address output from the address generation circuit 34 to the register 33.
Sampling frequency (eg 44.1k
It is continuously output from the register 33 at a constant reproduction rate according to (Hz) and sent to the D / A converter 7.

Here, the buffer RAM as described above
When the writing to 6 is suspended and then the writing is resumed, that is, when data connection is performed, the address when the last data is written to the buffer RAM 6 is output from the address generation circuit 34, and the data is used for the buffer. It is taken into the register 35 from the RAM 6 via the data selector 32. This data is compared with the data input to the register 31 from the signal processing unit 4 by the data comparator 36, and when both match, a coincidence output is output to determine the timing of data connection. That is, the input data from the next signal processing unit 4 for which a coincident output is obtained may be written in the buffer RAM 6.

Next, FIG. 4 schematically shows the write / read operation for the buffer RAM 6 in the memory space, and FIG. 5 shows an example of the internal configuration of the address generation circuit 34. 4 and 5, in FIG.
When the write enable signal W-EN from the system controller 10 is sent to the write address counter 13, the write address counter 13 operates and the write address is advanced (incremented) at a speed faster than the standard. W
A is generated. Data is written in the buffer RAM 6 by the write address WA. Further, the system controller 10 or the like checks the subcode information or the like to check for skipped sounds, etc., and sends a good state signal SOK to the effective write address latch 14 if there is no problem. Effective write address latch 14 latches write address WA from write address counter 13 in response to this signal SOK, and outputs it as effective write address VWA. The stored data up to the address VWA is reproducible data with no skipped sound, and can be sent to the D / A converter 7.

The read address counter 15 operates in response to the read enable signal R-EN from the system controller 10 to advance the read address RA at the standard speed.
And the data written in the buffer RAM 6 are sequentially read. Since the step speed (write speed) of the write address WA is higher than the speed (read speed) of the step (increment) operation of the read address RA, the address WA is the address RA in the loop memory space. However, at this time, the stepping operation of the write address WA is stopped, and the writing is restarted when the read address RA advances and the remaining amount of data falls below a predetermined amount (the step of the write address WA. Restart the advancing operation). The remaining amount of data at this time indicates the amount of actually reproducible data from the valid write address VWA to the read address RA. The subtracter 16 obtains the address difference ΔA by subtracting the address RA from the address VWA.

Here, the data read from the buffer RAM 6 and sent to the D / A converter 7 and the system controller 1 obtained by the subcode Q processing circuit 24 and the like.
The time difference between the subcode time information held by 0 is the sum of the delay amount in the decoding process RAM 26 and the delay amount in the buffer RAM 6 and is the delay amount in the decoding process RAM 26. Is about ten and several msec including the above-mentioned jitter correction amount, and can be ignored in the case of time display or the like. Therefore, only the delay amount in the buffer RAM 6 is taken into consideration in the following description.

Therefore, the time difference Td between the actual reproduction data and the time information of the subcode is the address difference ΔA.
The data amount Dm corresponding to (= VWA-RA) is divided by the data read rate Dr. RAM 6 for buffer
Assuming that the number of bits of the storage unit (word) for one address is n bits, the time difference Td is Td = Dm / Dr = (n × ΔA) / Dr.

From the above, the system controller 1
For 0, the subcode information received from the subcode Q processing circuit 24 or the like of the signal processing unit 4 may be delayed by the time difference Td to perform control operations such as actual time display and de-emphasis switching. That is, the display unit 11
Absolute time T _ABS and elapsed time in the song (lap time) T
When displaying the _{LAP and the} like, it is _sufficient to display the values obtained by subtracting the time difference Td from the absolute time T _QABS and the in-tune time T _{QLAP and the} like obtained from the sub-code Q information, and switching control such as de-emphasis is performed. Also in the case of switching, it is possible to match the content of the reproduced audio signal by delaying and switching the time difference Td. The same applies to the display of song numbers (track numbers) and index numbers.

Further, even in a special reproduction state such as pause (pause) and re-beat between A and B, the above-mentioned time difference Td is taken into consideration to perform control so that the display, the audio output and the key operation are performed between the apparatus. You can avoid giving it an unnatural feel.

For the address difference ΔA, it is not necessary to obtain all the bits of the address (for example, 20 bits).
You may make it use about several high-order bits according to the required precision. Here, as a specific example of the buffer RAM 6, the storage capacity is such that the bit number n of one word is 4 bits and the address bit number is 20 bits (A _{0 to} A ₁₉ ).
When using an M-bit memory, the upper 4 bits (A ₁₆
When to A ₁₉₎ using only becomes distinguishable accuracy 0.25M bits. The data read rate Dr is about 1.
When it is set to 4 Mbits / sec, the data amount [M bits] with respect to the value of the upper 4 bits (A _{16 to} A ₁₉ ) of the 20-bit address (A _{0 to} A ₁₉ ) representing the address difference ΔA and the time conversion amount [Second. Frame] is shown in Table 1 below.

[0033]

[Table 1]

However, in this case, an error may occur in the calculated data, and the time may be returned when the elapsed time of the CD is displayed. In such a case, an unnatural feeling can be prevented by using a program so that the calculated value does not decrease due to the error.

Further, the address difference ΔA is displayed on the display unit 11 by a numeral or a visual representation of the quantity, so that the user of the device can know the remaining memory capacity of the buffer RAM 6 and the memory storage data quantity. Can inform,
This is useful for checking the operating status. Here, the display that expresses the visual amount is, for example, the buffer RAM 6
And a fixed display element that represents a container that reminds of
6 and a variable display element that expresses the reproducible data amount stored in the storage device 6.

As is apparent from the above description, according to the present invention, it is only necessary to store the main data in the memory (RAM 6), the memory capacity can be effectively used, and the read main can be performed by the information of the write data. You can control the data. Further, by simply subtracting the delay time Td in the buffer RAM 6 from the absolute time T _QABS based on the subcode Q data, the in-track elapsed time (lap time) T _QLAP, etc., with respect to the main data actually reproduced, It is possible to obtain time information (T _ABS , T _LAP, etc.) at the same timing, to perform an appropriate display, and to display the amount of reproducible data in the buffer RAM 6 to inform the operating state of the device. You can also Further, it is possible to control reproduction data such as de-emphasis switching at the correct timing. Further, even when a special operation such as a pause or an AB repeat is performed, a natural operation or display without a feeling of strangeness can be performed.

The present invention is not limited to the above-mentioned embodiments, and for example, as recording media, in addition to optical disks, magneto-optical disks, magnetic disks, magnetic tapes, etc. can be used, and the format is so-called. It is not limited to the CD format. In addition to PCM audio data, video data, compressed data, etc. can be used as the main data. Further, the auxiliary data is not limited to the above subcode data, and can be applied to a format in which error correction processing is not performed. Of course, the hardware configuration is not limited to the illustrated example.

[0038]

As is apparent from the above description, according to the data reproducing apparatus of the present invention, the recording data in which the auxiliary data is added to the main data is read from the recording medium to separate the main data, When controlling writing / reading to / from the buffer memory, the amount of delay between writing / reading according to the amount of reproducible data stored in the buffer memory and the reading from the recording medium are performed. Since the time-related information of the main data read from the buffer memory is calculated based on the time-related information obtained from the auxiliary data, it is necessary to store only the main data in the buffer memory. The effective utilization rate of the storage capacity is often increased, and the time-related information whose timing coincides with the main data that is actually read from the buffer memory is reproduced. It is obtained.

Further, the data reproducing apparatus according to the present invention writes the control information signal such as de-emphasis switching obtained from the auxiliary data according to the amount of reproducible data stored in the buffer memory. Since the control such as de-emphasis switching is performed with a delay of the delay amount between readings, the control of the main data read from the buffer memory is performed at the correct timing.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall schematic configuration of an embodiment of a data reproducing apparatus according to the present invention.

FIG. 2 is a block circuit diagram showing a specific example of a signal processing unit in the above embodiment.

FIG. 3 is a block circuit diagram showing a specific example of a RAM controller in the above embodiment and its periphery.

FIG. 4 is a diagram for explaining movement of a write address and a read address in the memory space of the buffer RAM in the above embodiment.

5 is a block diagram showing an example of an internal configuration of an address generation circuit in FIG.

[Explanation of symbols]

 1 ... Optical disc 2 ... Optical pickup 4 ... Signal processing unit 5 ... RAM controller 6 ... Buffer RAM 9 ... Servo control circuit 10-System controller 11-Display 12-Key input 13-Write address counter 14-Effective write-address counter 15- ..Read address counter 16 ... Subtractor 21 ... EFM demodulation circuit 23 ... PLL / timing generation circuit 24 ... Subcode Q processing circuit 25 ... Error correction processing circuit 26 ... Decoding processing RAM 27 ... Read / write control circuit 29 ... Timing generation circuit 31, 33, 35 ... Register 36 ... ..Data comparators

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Toru Tsunono 134 Toyohama Business Park East Tower 11F Kobe Tower, Hodogaya-ku, Yokohama, Kanagawa Prefecture Sony LSI Design Co., Ltd.

Claims (2)

[Claims] 1. A data reproducing apparatus for reproducing the main data by reading the recording data from a recording medium on which recording data in which auxiliary data is added to main data is recorded, and the recording data read from the recording medium. Signal processing means for separating the main data from the auxiliary data, a buffer memory for storing the separated main data, and a memory for controlling writing / reading of the main data with respect to the buffer memory. The control means and the delay amount between writing and reading in accordance with the amount of reproducible data stored in the buffer memory are calculated, and the delay amount and the time obtained from the auxiliary data from the signal processing means are obtained. Control means for calculating time-related information of the main data read from the buffer memory based on the related information. Data reproduction apparatus characterized by. 2. A data reproducing apparatus for reproducing the main data by reading the recording data from a recording medium in which recording data in which auxiliary data is added to main data is recorded, and the recording data read from the recording medium. Signal processing means for separating the main data from the auxiliary data, a buffer memory for storing the separated main data, and a memory for controlling writing / reading of the main data with respect to the buffer memory. The control means and the delay amount between writing and reading depending on the amount of reproducible data stored in the buffer memory are obtained, and the control information signal obtained from the auxiliary data from the signal processing means is obtained as described above. A control procedure that delays the delay time to control the main data read from the buffer memory. Data reproducing apparatus characterized by having and.