JPH08194649A - Memory address line abnormally detecting method - Google Patents

Abstract

PURPOSE: To detect the normality/abnormality of a memory address line before the write/read of a memory by detecting the abnormality of the address line by checking the memory data of an address other than for the written address. CONSTITUTION: When certain one bit of the address line can net be controlled, for example, first of all, all memory areas to be checked are cleared to '0' and after it is confirmed that the data of addresses 0000H and 0001H are '0', data other than '0' are written in the address 0001H. When the data of the address 0000H are not '0', it is decided there is abnormality at an address line A0. When two or more bits of the address line are in contact with each other, the memory areas to be checked are cleared to '0' and after it is confirmed that the data of addresses 0001H and 0002H are '0', data other than '0' are written in the address 0001H. When the data of the address 0002H are not '0', it can be confirmed that the bits of address lines A0 and A1 are in contact with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for checking a plurality of expandable memories or memory units accessed by a microprocessor. It should be noted that the memory unit here is composed of a memory chip, a memory module, or a plurality of memories as an expansion unit.

[0002]

2. Description of the Related Art A conventional memory check method only sets physical addresses of all memory areas and writes / reads check data to check whether the memory module is normal or not.

[0003]

In the above method, when a defect occurs in the address line, the address itself to be checked cannot be set correctly, so that "one address for one address" cannot be set for all areas to be checked. It is impossible to check "write / read one data correctly". This will be described below with reference to the drawings. FIG. 2A shows a case where the address line is functioning normally. A0-A
RAM 1 having 8 address lines 7 and its internal memory map are shown. When writing data by designating the first address 0000H represented by a hexadecimal number, if all address lines are correct, address 00 on RAM1
Data is written to 00H. Similarly, the address 000
If 1H is specified, the data is written in the correct position on RAM1.

Next, in the case of a defect that the output bit of the address line A0 is always "0", when the address 0000H is designated as shown in FIG. 3A, the data is correctly written in the designated address. However, as shown in FIG. 3B, when the address 0001H is designated, it is written in the wrong address 0000H. In the case of a defect that the output bit of the address line A0 is always "1", when the address 0001H is designated as shown in FIG. 4B, the data is correctly written in the designated address, but the address 0000H is written. When is specified, data is written to the wrong address 0001H.

It is an object of the present invention to provide a memory address line abnormality detecting method for checking the normality / abnormality of the address line before writing / reading the memory.

[0006]

The above object can be achieved by checking the normality / abnormality of the address line itself by using the check address of a specific address line before writing / reading the memory.

[0007]

[Action]

(1) A check example is shown when one bit on the address line cannot be controlled. Clear all memory areas to be checked to 0. Confirm that the data at address 0000H is 0. Confirm that the data at address 0001H is 0. Data other than 0 is written to address 0001H (check address). If the data at address 0000H is not 0, it can be confirmed that the address line A0 is abnormal. (2) A check example is shown when two or more bits of the address line are in contact with each other. Clear the memory area to be checked to 0. Confirm that the data at address 0001H is 0. It is confirmed that the data at the address 0002H is 0. Data other than 0 is written to address 0001H (check address). If the data of the address 0002H is not 0, it can be confirmed that the bits of the address lines A0 and A1 are in contact with each other.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An actual memory address line abnormality detection method will be described below with reference to a flow chart. In FIG. 1, the flow of the abnormality detection method is performed in the following procedure. VCHKA here
D indicates an address line to be checked. Clear the memory area to be checked to 0. Confirm that the data at address 0000H is 0. It is confirmed that the data at the address 8000H (check address) is 0. If the data at address 0000H is not 0, it is an error. Write / read check of address 8000H (check address) is performed. Confirm that the data at address 0000H is 0. If the data at address 0000H is not 0, it is an error. Change the check address to 1/2 (change from 8000H to 4000H). Are repeated until the check address becomes 0001H.

[0009]

As described above, according to the present invention, by detecting the address line access failure of the hardware, the address line disconnection, the solder failure, etc. at the time of power-on,
Printing defects due to the memory module can be eliminated.

[Brief description of drawings]

FIG. 1 is a flowchart showing an abnormality detecting method of the present invention.

FIG. 2 is a schematic diagram showing a conventional address line, a RAM and a memory map thereof.

FIG. 3 is a schematic diagram showing a case where an address line A0 is “0” is abnormal.

FIG. 4 is a schematic diagram showing a case where an address line A0 is “1” is abnormal.

Claims (1)

[Claims] 1. A method for detecting an abnormality in a memory address line, which comprises detecting an abnormality in a memory address line by checking memory data at an address other than an address at which writing is performed in detecting an abnormality in a memory.