JP3098363B2 - Storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device having a memory unit having a semiconductor storage element having an ECC function, and more particularly to control of a partial write operation thereof.

[0002]

2. Description of the Related Art In a conventional storage device having a memory unit having a semiconductor storage element having an ECC function and a partial write function, a memory unit (partial write execution in the case of bank control) is performed during a partial write operation. bank)
Cannot accept the next command (data write command or data read command) until the operation of this cycle is completed.

[0003]

As described above, in the conventional storage device, during the execution of the partial write operation, the next data write instruction or data read instruction cannot be accepted until the operation of this cycle is completed. If the write operation is divided into an old data read operation, a data correction operation by the ECC circuit, a replacement operation with new data, and a new data write operation, the data correction operation by the ECC circuit and the new If the time of the replacement operation with data is long, the data read operation and the data write operation, which are performed as a series of operations related to the partial write operation, have a free time during which other data can be read or written. Until the partial write operation is completed, the next data write instruction or read Not made accept instruction, therefore use efficiency of the memory portion, i.e., the operation efficiency of the storage device has the disadvantage that low.

[0004]

The storage device according to the present invention has an E storage device.
A memory unit configured by a semiconductor memory element having a CC function, a partial write control unit that inputs an address, write data, and an operation command from a higher-level device, and inputs the address and the operation command to the memory unit. A memory control signal generating circuit for generating a memory control signal including a chip select signal and a write enable signal, and an address for monitoring the presence or absence of a data write request or a data read request for the same address during execution of the partial write operation of the memory unit. And a monitoring circuit.

[0005]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, when a partial write instruction is started for a memory unit 8 having an ECC function and configured by a semiconductor memory device, an address 20, write data 21 and an operation as information necessary for the partial write operation are provided. A command 22 is input from a higher-level device (not shown), an address 20 and write data 21 are held in the partial write control unit 1, and an operation command 22 is held in the memory control signal generation circuit 2 to store a memory control signal for the memory unit 8. (For example, a chip select signal, a write enable signal, etc.) 23. At the same time, the address 20 is held in the address register 6 via the selector 4a.

In order to read data from the address as a first step of the partial write operation, the memory unit 8 uses a signal from the address register 6 and a memory control signal 23 from the partial write control unit 1 to read data. Perform reading. The read data is held in a read data register 9 and then read by a data correction circuit (EC
C) A 1-bit error is corrected in 10 and output as read data 24, and is input to the partial write control unit 1.

Next, as a second step, a portion of the write data 21 designated by the operation command 22 is replaced with the read data 24 with respect to the address held in the partial write control section 1, and then the write operation is performed. Move to

The selector 4a selects the address 20a, and the address 20a is held in the address register 6. The selector 4 b selects the operation data 21 a, generates an ECC check bit for the operation data 21 a by the check bit generation circuit (ECG) 5, holds the ECC check bit in the write data register 7, and writes the data generated by the memory control signal generation circuit 2. The control signal is sent to the memory unit 8 as the memory control signal 23 to perform writing. Thus, one cycle of the partial write operation is completed.

As described above, during a one-cycle partial write operation, two operations, a read operation and a write operation, are performed. The interval between these two operations is determined by the data correction circuit (ECC) 10 and the partial write operation. Since there is an operation time in the control unit 1, there is a margin for the operation time required by the semiconductor storage element in the memory unit 8. Therefore, between the above-mentioned read operation and write operation, the memory unit 8
An address monitoring circuit 3 is provided in order to effectively use the memory unit 8 by performing a normal read operation or write operation on the memory unit 8. The address monitoring circuit 3 monitors a memory address in order to prevent data corruption during the execution of the partial write operation. During the execution of the partial write operation, the address monitoring circuit 3 selects a selector 4a for an address other than the partial write execution address. Selects the address 20, the selector 4b selects the write data 21, and performs the normal read operation or the write operation by the memory control signal 23 generated by the memory control signal generating circuit 2 by the normal read command or the write command. Let

When a normal read command or a write command is issued to the address during the partial write operation, the address monitoring circuit 3 outputs the error report signal 2
An error is reported to the host device by 5 and the requested normal read command or write command is invalidated to prevent data corruption.

As a result, the use efficiency of the memory section 8 is improved.

[0014]

As described above, the storage device of the present invention is provided with the address monitoring circuit and the memory control signal generation circuit, monitors the memory address by the address monitoring circuit, and performs the read operation during the execution of the partial write operation. Between the operation and the write operation, the memory unit performs a normal read operation or a write operation for an address other than the address where the partial write is being executed, and performs a normal read command or write for the address where the partial write operation is being executed. When a command is issued, the normal read command or write command is invalidated to prevent data from being garbled, so that the use efficiency of the memory unit, that is, the operation efficiency of the storage device can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Partial write control part 2 Memory control signal generation circuit 3 Address monitoring circuit 4a ・ 4b Selector 4a 5 Check bit generation circuit (ECG) 6 Address register 7 Write data register 8 Memory part 9 Read data register 10 Data correction circuit (ECC) 20・ 20a address 21 write data 21a operation data 22 operation command 23 memory control signal 24 read data 25 error report signal

Claims (2)

(57) [Claims] A memory unit having a semiconductor storage element having an ECC function; a memory control signal generating circuit for generating a memory control signal including a chip select signal and a write enable signal for the memory unit; A storage device comprising: an address monitoring circuit that monitors whether there is a data write request or a data read request for the same address during execution of a partial write operation of the unit. 2. A memory section comprising a semiconductor memory element having an ECC function, a partial write control section for inputting an address, write data, and an operation command from a host device, and a memory for inputting the address and the operation command. A memory control signal generating circuit for generating a memory control signal including a chip select signal and a write enable signal for the memory unit, and a data write request or a data read request for the same address during a partial write operation of the memory unit. A storage device comprising: an address monitoring circuit that monitors presence / absence.