JPH07160594A - Information processor - Google Patents

Abstract

PURPOSE:To provide an information processor capable of storing data comparatively low in access frequency with high reliability. CONSTITUTION:A disk controller 3 equipped with cache memory 7 and backup. memory 8 is constituted in such a way that a dummy read control part 16 is provided in the backup memory 8 with nonvolatile memory 9, a memory control part 10, and a redundant data processing part 11 for error control, and a dummy read request signal and a readout address to read out data in the nonvolatile memory 9 in the idling period of the nonvolatile memory 9 is generated in the dummy read control part 16, and the memory control part 10 performs the memory readout control of dummy data. Consequently, error check for the data read out from the nonvolatile memory 9 is performed by the redundant data processing part 11, and the reliability for the data in the backup memory 8 with comparatively low access frequency can be maintained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing technique, and more particularly to a technique effectively applied to an information processing technique for improving reliability of stored data in a memory by adding redundant data for error control. It is a thing.

[0002]

2. Description of the Related Art In the information-oriented society of recent years, the role of a storage device for accumulating the data of the information is very large. Among them, the disk device is currently high-speed and highly reliable. It is indispensable for technology. However, there is a strong need for further speeding up and reliability improvement, and various technologies are being considered in order to meet such needs.
For example, in the technique disclosed in Japanese Patent Laid-Open No. 59-220856, a disk controller for controlling a disk device holds a non-volatile data which holds the disk address of the unwritten data to the disk in the cache and the corresponding unwritten data. Reliability memory, it is possible to improve reliability when the power is turned off.

FIG. 12 shows a schematic block diagram of a conventional information processing apparatus.

Reference numeral 1 is a central processing unit for performing information processing, 2 is a disk device for storing information, 3 is a disk controller for controlling the disk device 2, 5 and 6 are disk controller 3 and central processing unit 1, disk device, respectively. A central processing unit interface for connecting to 2 and a disk device interface, 7 has a built-in memory capable of reading and writing faster than the disk device 2, and transfers data by storing data to be read from and written to the disk device 2 in a shared memory. A cache memory for speeding up the process, and 8 stores data not yet written in the disk device 2 in the cache memories 7 and 2.
A backup memory that retains data even when the power is cut off by double writing, 12 is a bus including address, data, and control signals, 13 is a control signal line of the backup memory 8, 14 is an address bus, and 15 is a data bus, Reference numeral 9 is a non-volatile memory in which data is not lost even when the power is cut off, 10 is a memory control unit for controlling the non-volatile memory 9, 11 is parity or ECC (Error Correction Code) when writing data to the non-volatile memory 9. The redundant data processing unit adds redundant data for error control such as error detection and error correction and checks whether the data is normal when reading.

The operation of the conventional information processing apparatus will be described below.

First, when reading data, the disk device 2 transfers the data to the central processing unit 1 via the disk device interface 6 and the central processing unit interface 5. At this time, the same data is written also in the cache memory 7. After that, when reading the same data, the data is read not from the disk device 2 but from the cache memory 7 capable of reading and writing at a higher speed, thereby enabling a high read speed.

Next, when writing data, the data is transferred from the central processing unit 1 to the disk unit 2 via the central processing unit interface 5 and the disk unit interface 6. However, the central processing unit 1 needs to wait until the data writing is completed. At this time, the data is written in the cache memory 7 that can be read and written at a higher speed than the disk device 2, and at the time when the data has been written in the cache memory 7, the central processing unit 1 continues the next processing. The data written in the cache memory 7 is
It is written in the disk device 2. This enables a high writing speed.

At this time, the data written in the cache memory 7, that is, the data not written in the disk device 2 is also written in the backup memory 8 at the same time. If the backup memory 8 is not provided, the data stored in the cache memory 7 that has not been written to the disk device 2 will be permanently lost when the power supply of the disk controller 3 is cut off. However, when the backup memory 8 is provided and the unwritten data for the disk device 2 is stored, the data can be restored even when the power is cut off.

Some of the backup memories 8 are further improved in reliability by writing data including redundant data in the non-volatile memory 9.

FIG. 13 shows a block diagram of a conventional backup memory.

Reference numeral 20 is a memory control signal, 21 and 22 are data buffers, 23 is a redundant data generator for generating redundant data such as parity and ECC, 24 is a data bus containing redundant data, and 25 is read from the non-volatile memory 9. An error detection unit 26 for checking whether or not there is an error in the data is an error signal.

In the above circuit, when writing data in the non-volatile memory 9, redundant data such as parity and ECC is added by the redundant data generating section 23, and when reading, original data and redundant data read by the error detecting section 25. The presence or absence of an error is obtained from the calculation of. When an error is detected, "1" is output to the error signal 26. If the redundant data is ECC, error correction is also performed.

[0013]

However, conventionally, the error check is performed on the data in the non-volatile memory 9 when the data is read, that is, after the power is suddenly cut off, the power is restored and the disk device 2 On the other hand, it was only before writing the unwritten data, and the error could not be detected early. Further, when the redundant data processing unit 11 detects an error in the data, the existence of the error can be confirmed, but when the redundant data is the parity, correct data is lost, and also in the case of the ECC,
If a plurality of data bits that exceed the ECC capability are in error, there is a problem that error correction may not be possible.

As described above, conventionally, in a memory in which redundant data such as ECC and parity is added to improve reliability, an error is detected only when data is read, so that the data is, for example, backup data. If it is something that is not read frequently, early detection of errors is impossible, and even if errors are detected, correct data may be lost due to slow detection. There was a problem.

An object of the present invention is to provide an information processing technique capable of storing data with relatively low access frequency with high reliability.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0017]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, the present invention is an information processing apparatus including a memory and error control means for writing and reading data to which redundant data for error control is added and read from the memory. In addition to the above control, a dummy read control means for controlling the reading of data from the memory is provided.

As the dummy read control means, for example, at least a dummy read request signal generating means for generating a dummy read request signal, an address counter for generating an address of the dummy read, a dummy read for the memory and a normal read / write operation. It is conceivable to include a selector for selecting an address and an arbitration means for arbitrating a dummy read request and a normal read / write request.

It is also conceivable that the dummy read request signal generating means performs, for example, an operation of detecting an idle period during which no reading or writing is performed on the memory and generating a dummy read request signal.

Further, it is considered that the dummy read request signal generating means carries out an operation of periodically generating a dummy read request signal, for example.

Further, it is conceivable that the memory comprises a multiport memory having at least one of a data bus, an address bus, and a control signal in two or more systems.

Further, it is conceivable that the memory is composed of, for example, an image memory having a serial data bus in addition to an ordinary data bus.

For example, the dummy read control means is
For example, it is conceivable that the software is configured so that the memory is read out periodically and the error control means performs an error check on the data.

Further, it is conceivable that the information processing apparatus is, for example, a disk controller which is interposed between the host apparatus and the disk apparatus to control the exchange of information between them.

[0026]

For example, in the dummy read request signal generator,
A dummy read request signal for requesting data read is generated by detecting an idle state in which no data is written to the memory, and the arbitration unit arbitrates between the normal read / write request and the dummy read request. Then, the address counter generates an address at the time of dummy read, and the selector selects an address at the time of dummy read and a normal read / write address.

By the above operation, the data in the memory is read during the idle period in which the data is not written to the memory, the data is checked for errors, and the error in the backup data or the like having a relatively low access frequency is detected. It enables early detection of. Therefore, even if there is an abnormality in the data in the memory, it is possible to improve reliability by early error detection.

[0028]

Embodiments of the present invention will now be described in detail with reference to the drawings.

In the following description, components and signals having the same reference numerals are the same in different drawings.

(Embodiment 1) FIG. 1 is a schematic block diagram showing an example of the configuration of an information processing apparatus which is an embodiment of the present invention.

In this embodiment, as an example of the information processing apparatus, a case where it is applied to a disk controller 3 which is interposed between the central processing unit 1 and the disk device 2 to control the exchange of information between the two will be described.

In the disk controller 3, 2 is a disk device for storing information, 3 is a disk controller for controlling the disk device 2, 5 and 6 are the disk controller 3 and the central processing unit 1 and the disk device 2, respectively. A central processing unit interface, a disk unit interface, 7 is a cache that has a built-in memory capable of reading and writing faster than the disk unit 2, and stores data to be read from and written to the disk unit 2 in a shared memory to accelerate data transfer. The memory 8 stores the data not written in the disk device 2 in the cache memories 7 and 2.
This is a backup memory that retains data even when the power is cut off by writing multiple times.

Further, 12 is a bus including address, data and control signals, 13 is a control signal line of the backup memory 8, 14 is an address bus, 15 is a data bus, and 9 is non-volatile so that data is not lost even when power is cut off. A memory 10 is a memory control unit for controlling the non-volatile memory 9, and 11 is a parity or E when writing data in the non-volatile memory 9.
It is a redundant data processing unit that adds redundant data for error control such as error detection and error correction such as CC and checks whether the data is normal when reading.

In this case, the backup memory 8 is provided with a dummy read control section 16 for performing dummy read control of data from the non-volatile memory 9.

The dummy read control unit 16 will be described below with reference to the block diagram of the backup memory 8 shown in FIG.

Reference numeral 30 is a dummy read request signal generating section for generating a dummy read request signal, 31 is an arbitration section for arbitrating a normal read / write request and a dummy read request, and 32 is a memory address for dummy read. An address counter 33 for selecting, a selector for selecting an address for dummy read and an address for normal read / write,
As a result of arbitration performed by the arbitration unit 31, 34 is a write / read request signal for making a memory read / write request to the memory control unit 10, 35 is a dummy read request signal, 36 is a dummy read address bus, and 37 is an address bus. .

First, the normal operation will be described.

As with the conventional backup memory shown in FIG. 13, when writing data, unwritten data for the disk device 2 is written to the backup memory 8 together with the cache memory 7.

The selector 33 outputs the address bus 14 to the address bus 37 as it is, and the memory control unit 10 generates a memory write control signal from the control signal line 13 and outputs it to the memory control signal 20. The memory 9 is controlled. Then, the redundant data processing unit 11 writes the data to which the redundant data is added to the non-volatile memory 9.

Data reading is also performed in the same manner as in the conventional case after the power is suddenly turned off.

Next, the dummy read will be described.

The dummy read request signal generating section 30 outputs a pulse signal to the dummy read request signal 35, and the arbitration section 31 arbitrates the pulse signal and the normal read / write request signal of the control signal line 13. Read /
In response to the write request signal 34, a memory read / write request signal is output. Further, a pulse signal is applied to the clock input of the address counter 32, the address counter value is incremented, and output to the dummy read address bus 36. At the time of dummy read, the selector 33 outputs the value of the dummy read address bus 36 to the address bus 37 as it is.

By repeating the above operation, dummy reading is performed on all the memory spaces of the non-volatile memory 9, and the read data is error-checked in the redundant data processing unit 11.

The address counter 32 may be an up counter that increases its value or a reverse down counter.

The details of the dummy read request signal generator 30 will be described below.

FIG. 3 shows the backup memory 8 for a certain period.
FIG. 6 is a first block diagram showing an example of the configuration of a dummy read request signal generation unit 30 that detects that reading and writing is not performed on and from, and that generates a pulse signal.

Reference numeral 40 designates an idle time setting register for setting a period from the immediately preceding write in order to determine the idle state when the memory is not read or written.
45 is an idle time output, 41 is a counter, 46 is a counter output, 42 is a comparison circuit which compares the idle time output 45 with the counter output 46 and outputs "1" when they match, 47 is a comparison output, and 43 is a pulse A pulse signal generation unit that generates a signal to generate the dummy read request signal 35, 44 a clear signal generation unit that generates a clear signal 48 of the counter 41, 49 a clock signal, and 50 a write signal to the backup memory 8. Of these, the pulse signal generator 43 and the clear signal generator 44 can be configured by the circuits shown in FIGS. 4 and 5, respectively.

The operation of this circuit will be described below with reference to the timing chart shown in FIG.

First, "n" is set in the idle time setting register 40. The counter output 46 is the clock signal 4
Incremented by 9, idle time output 45
When it is equal to “n”, “1” is output to the comparison output 47, and the pulse signal generation unit 43 outputs “1” to the dummy read request signal 35. Similarly, the clear signal generator 44 outputs "1" to the clear signal 48, and as a result, the counter output 46 is cleared to "0". After that, the counter output 46 is incremented each time the clock signal 49 becomes “1”.

When writing to the backup memory 8 occurs before the counter output 46 becomes "n", the write signal 50 becomes "1". As a result, the clear signal 48 becomes "1", the counter output 46 is cleared and becomes "0". After that, the counter output 46 is incremented each time the clock signal 49 becomes “1”, and unless writing to the backup memory 8 occurs again, the dummy read request signal 35 is generated each time the counter output 46 becomes “n”. Becomes "1".

To summarize the above operation, the dummy read request signal 35 is kept at "0" while the backup memory 8 is being written, and the dummy read request signal 35 is periodically provided if the writing is not performed for a certain period.
Becomes "1". As a result, when the backup memory 8 is not written for a certain period of time, it is determined that the backup memory 8 is in the idle state and a dummy read, that is, an error check of the memory data is performed. Therefore, conventionally, the error check is not performed on the memory data unless the power is turned off, whereas the error check is always performed at the idle time, so that the speed is not deteriorated and the reliability is improved.

The write signal 50 may be reduced in this circuit. In this case, the dummy read is regularly performed regardless of whether the backup memory 8 is written. Further, instead of the write signal 50, a read signal or a signal obtained by logically adding the write signal and the read signal may be given. In this case, it is determined that the backup memory 8 is in the idle state because the backup memory 8 is not read or read or written.

Further, the idle time setting register 40 is
It may be a register writable by the central processing unit 1 or a fixed value set by hardware.

FIG. 7 shows the backup memory 8 for a certain period.
FIG. 6 is a second block diagram showing another configuration example of the dummy read request signal generation section 30 which detects that reading and writing with respect to is not performed and generates a pulse signal.

Reference numeral 52 is a down counter having a load function, 53 is a load signal generator, and 54 is a load signal. Others have the same configuration as the block diagram shown in FIG. Of these, the pulse signal generator 43 and the load signal generator 53 can be configured by the circuits shown in FIGS. 4 and 8, respectively.

The operation of this circuit will be described below with reference to the timing chart shown in FIG.

First, "n" is set in the idle time setting register 40. The down counter 52 decrements each time the clock signal 49 becomes “1”, and when the counter output 46 becomes “0”, outputs “1” to the comparison output 47, and the pulse signal generation unit 43 causes the dummy read request signal to be output. “1” is output to 35. Similarly, the load signal generator 53 outputs “1” to the load signal 54,
As a result, the counter output 46 becomes the idle time output 45.
The value "n" is output. After that, the counter output 46
Decrements each time the clock signal 49 becomes "1". If writing to the backup memory 8 occurs before the down counter 52 reaches "0", the write signal 50 becomes "1", which causes the load signal 54
Outputs "1", the counter output 46 is loaded,
It becomes "n". After that, the counter output 46 is decremented each time the clock signal 49 becomes “1”, and unless writing to the backup memory 8 occurs again, the dummy read request signal 35 is generated every time the counter output becomes “0”. It becomes "1".

Summarizing the above operation, the dummy read request signal is "0" when the backup memory 8 is being written, as in the circuit described in FIG.
If no write operation occurs for a certain period, the dummy read request signal becomes "1" periodically. by this,
When the backup memory 8 is not written for a certain period of time, it is determined to be in the idle state, and dummy reading, that is, an error check of the memory data is performed. This improves reliability without degrading speed.

The write signal 50 may be reduced in this circuit. In this case, the dummy read is regularly performed regardless of whether or not the backup memory 8 is written. Further, instead of the write signal 50, a read signal or a signal obtained by logically adding the write signal and the read signal may be given. In this case, it is determined that the memory is in the idle state because the memory is not read or the memory is not read or written.

Further, the idle time setting register 40 is
It may be a register writable by the central processing unit, or may be a fixed value set by hardware.

(Embodiment 2) Next, an example of a backup memory in an information processing apparatus according to another embodiment of the present invention will be described.
This will be described with reference to the block diagram of the backup memory shown in FIG.

In this embodiment, the non-volatile memory 9A includes
A multiport memory having two or more systems of at least one of a data bus, an address bus, and a control signal is used.

Reference numeral 60 denotes a circuit equivalent to the memory control unit 10, a memory read control unit for generating a memory read control signal, 61 a memory control signal, 62 a data bus including redundant data, and 63 an error detection unit. An error detection unit, which is the same circuit as 25, and 64 is an error output. The address bus 14, the memory control signal 20, and the data bus 24 form a first bus, and the dummy read address bus 36, the memory control signal 61, and the data bus 62 form a second bus. Is possible.

First, the normal read / write operation is the same as the operation described in the block diagram of the conventional backup memory described in FIG. 13, and the memory is read / written from / to the first bus.

Next, regarding the operation during dummy read,
The following operations are performed from the second bus.

The dummy read request signal generator 30 outputs a pulse signal to the dummy read request signal 35 to request the memory read controller 60 to read the memory and increment the address counter 32. The memory read control unit 60 generates a memory read control signal, and the counter output from the address counter 32 to the dummy read address bus 36 becomes an address for the nonvolatile memory 9. As a result, the data in the non-volatile memory 9A is output to the data bus 62, the error detection unit 63 performs an error check, and when an error is detected, "1" is output to the error output 64.

By repeating the above operation, the non-volatile memory 9A is checked for errors in the data in the entire memory space.

If an error is detected, the data is written again. If the error still occurs, the backup memory 8 can be replaced. No data is lost once the error is detected, improving reliability.

(Third Embodiment) Next, an example of a backup memory in an information processing apparatus according to still another embodiment of the present invention will be described with reference to the block diagram of the backup memory shown in FIG.

In the case of this embodiment, as the non-volatile memory 9B, an image memory having a serial data bus in addition to a normal data bus and capable of serially reading data is used.

Reference numeral 70 is a serial data bus, 71 is a serial-parallel converter for converting serial data into parallel data, and 72 is a parallel data bus.

First, the normal read / write operation is the same as the block diagram of the backup memory described with reference to FIG.

Next, the operation during dummy read will be described.

Similar to the operation in the block diagram of the backup memory described with reference to FIG. 2, first, the memory read request signal for dummy read is output in response to the read / write request signal 34. Further, the dummy read address is output to the address bus 37. The memory control unit 10 outputs a serial read control signal to the non-volatile memory 9B as the memory control signal 20, and as a result, serial data is output to the serial data bus 70. The data is converted into parallel data by the serial / parallel conversion unit 71, and an error check is performed by the error detection unit 63. Then, when an error is detected, “1” is output to the error output 64.

By repeating the above operation, the non-volatile memory 9B is checked for errors in the data in the entire memory space.

If an error is detected, the data is written again. If the error still occurs, the backup memory 8 can be replaced. No data is lost once the error is detected, improving reliability.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

In the information processing apparatus of the present invention, the non-volatile memory 9 may be a memory that holds data without adding a power supply voltage, a memory that holds data simply by adding a power supply voltage, or a dynamic RAM (hereinafter, referred to as "memory"). DRA
A device requiring refresh control, such as M), can be used. Since the DRAM stores data in a capacitor, refresh control is periodically performed to charge the capacitor and hold the data. However, since the refresh control can be substituted by the read operation, the dummy read may be performed by the circuit of the dummy read control unit of the present invention, and the dummy read may function as the refresh control.

In the above description of the embodiments, the backup memory is given as an example of the memory that does not need to be read frequently, but a memory that loses data when the power is turned off or a memory that does not perform double writing. Etc., it can be applied to any information processing apparatus having a memory that holds data in a format in which redundant data such as parity or ECC is added. In this case, if a dummy read control means is added, it is possible to detect an error early.

In the above description of the embodiment, as an example, the hardware circuit is provided to perform the dummy read to improve the reliability, but the software regularly reads the backup memory to detect an error. You may detect. For example, at night, a program that reads the backup memory may be added, or a program that detects the idle period of writing to the backup memory with software and reads the data in the backup memory during that period to check for errors. May be added.

[0081]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

According to the information processing apparatus of the present invention, in a memory in which data to which redundant data for error control is added is written and read, the access frequency is relatively low, such as backup data, Even if there is an abnormality in the data that does not need to be read frequently, it is possible to detect errors early and improve the reliability of the data.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an example of the configuration of an information processing apparatus that is an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of the configuration of the backup memory.

FIG. 3 is a first diagram showing an example of a configuration of a dummy read request signal generation unit that constitutes the backup memory illustrated in FIG.
It is a block diagram of.

FIG. 4 is a block diagram showing an example of a configuration of a pulse signal generation unit that constitutes the backup memory illustrated in FIG.

FIG. 5 is a block diagram showing an example of a configuration of a clear signal generation unit that constitutes the backup memory illustrated in FIG.

FIG. 6 is a first diagram showing an example of the operation of a dummy read request signal generation unit that forms the backup memory illustrated in FIG.
6 is a timing chart of FIG.

FIG. 7 is a second diagram showing an example of the configuration of a dummy read request signal generation unit that constitutes the backup memory illustrated in FIG.
It is a block diagram of.

8 is a block diagram showing an example of a configuration of a load signal generation unit that constitutes the dummy read request signal generation unit illustrated in FIG. 7. FIG.

FIG. 9 is a second timing chart showing an example of the operation of the dummy read request signal generation section exemplified in FIG.

FIG. 10 is a block diagram showing an example of a configuration of a backup memory in an information processing apparatus which is another embodiment of the present invention.

FIG. 11 is a block diagram showing an example of a configuration of a backup memory in an information processing apparatus which is another embodiment of the present invention.

FIG. 12 is a schematic block diagram of a conventional information processing device.

FIG. 13 is a block diagram showing an example of a conventional backup memory.

[Explanation of symbols]

 1 Central Processing Unit 2 Disk Unit 3 Disk Controller 5 Central Processing Unit Interface 6 Disk Unit Interface 7 Cache Memory 8 Backup Memory 9 Nonvolatile Memory 9A Nonvolatile Memory 9B Nonvolatile Memory 10 Memory Controller 11 Redundant Data Processor (Error Control Means ) 12 bus 13 control signal line 14 address bus 15 data bus 16 dummy read control section (dummy read control means) 20 memory control signal 21 data buffer 22 data buffer 23 redundant data generation section 24 data bus 25 error detection section 26 error signal 30 Dummy read request signal generation unit 31 Arbitration unit 32 Address counter 33 Selector 34 Read / write request signal 35 Dummy read request signal 36 Dummy read address buffer 37 Address bus 40 Idle time setting register 41 Counter 42 Comparison circuit 43 Pulse signal generation unit 44 Clear signal generation unit 45 Idle time output 46 Counter output 47 Comparison output 48 Clear signal 49 Clock signal 50 Write signal 52 Down counter 53 Load signal generation Section 54 load signal 60 memory read control section 61 memory control signal 62 data bus 63 error detection section 64 error output 70 serial data bus 71 serial-parallel conversion section 72 parallel data bus

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Susumu Onodera 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Hitachi Imaging Information Systems Co., Ltd.

Claims (1)

[Claims] 1. An information processing apparatus comprising: a memory; and an error control means for writing and reading data in which redundant data for error control is added to and read from the memory. In addition to the control, the information processing apparatus is provided with a dummy read control unit that controls reading of the data from the memory.