WO2012141161A1

WO2012141161A1 - Semiconductor memory circuit, method for operating semiconductor memory circuit, and method for designing semiconductor memory circuit

Info

Publication number: WO2012141161A1
Application number: PCT/JP2012/059746
Authority: WO
Inventors: 順也柴崎; 高橋　弘行
Original assignee: ルネサスエレクトロニクス株式会社
Priority date: 2011-04-12
Filing date: 2012-04-10
Publication date: 2012-10-18

Abstract

This semiconductor memory circuit is equipped with: a memory core that holds data; a peripheral circuit part which, when a read request has been issued, reads the data to be read from the memory core and performs data processing on the data that has been read from the memory core, outputting the result as output data to an external device, and which, when a write request has been issued, obtains input data from the external device and performs data processing on the input data, which is then written to the memory core as write data; and a control circuit that controls the operation of the peripheral circuit part such that the reading of data or the writing of data between the peripheral circuit part and the memory core is performed during a first period, and the data processing in the peripheral circuit part is executed in a second period. The control circuit controls the operation of the memory core such that a refresh operation is performed during the second period.

Description

Semiconductor memory circuit, semiconductor memory circuit operating method, and semiconductor memory circuit design method

The present invention relates to a semiconductor memory circuit, a method for operating the semiconductor memory circuit, and a method for designing the semiconductor memory circuit.

In a semiconductor memory circuit such as DRAM (Dynamic Random Access Memory), data is held in a memory core. In such a semiconductor memory circuit, a refresh operation for the memory core is performed in order to prevent data loss.

As a semiconductor memory circuit in which the refresh operation is devised, a semiconductor memory circuit using a Hidden-Refresh system has been put into practical use. In this semiconductor memory circuit, a refresh command is issued inside the semiconductor memory circuit. There is no need to provide a refresh command from the external device to the semiconductor memory circuit, and there is no need to develop a controller for controlling the refresh operation. It is possible to prevent an increase in test cost and a decrease in yield required for developing a controller for refresh control. However, in this semiconductor memory circuit, a read request or write request given from an external device may conflict with an internally issued refresh command. When a collision occurs, the refresh command needs to be executed after the read request or write request is completed.

On the other hand, the late write method is known as a method of writing data to the memory core. In a semiconductor memory circuit using the late write method, when a write request is issued, write data and a write address given from an external device are stored in a register provided in the semiconductor memory circuit. The stored data is written to the memory core when the next write request is issued. Therefore, when a write request is issued, data write to the memory cell can be started without waiting for the write data and write address given from the external device to be completely taken in, and the memory access operation can be performed. Speed can be increased.

A semiconductor memory circuit combining a Hidden-Refresh method and a late write method is disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2003-196975). In Patent Document 1, when a refresh request signal collides with a read request or a write request, the execution of the refresh operation is delayed until the read operation or late write write operation of the memory cell with respect to the conflicted read request or write request is completed. Is described.

By the way, in a semiconductor memory circuit, predetermined processing may be performed on write data or read data. For example, the semiconductor memory circuit may be provided with ECC (Error Correcting Circuit). The ECC generates parity data from the write data, and writes the write data and parity data to the memory core. The ECC reads data and parity data from the memory core, restores the read data based on the parity bit, and outputs it as output data.

As a technology related to ECC, there is a semiconductor integrated circuit device described in Patent Document 2 (Japanese Patent Laid-Open No. 2005-209316). In this semiconductor integrated circuit device, a memory cell coupled to the first word line and one of the parity bit bit line pair, a memory cell coupled to the second word line and the other of the parity bit bit line, A data line connected to the bit line; and a logic correction circuit connected to the data line. The logic correction circuit inverts the logic of the data read from the data line based on the logic of the address and inverts the logic of the data to be written to the data line.

JP 2003-196975 A JP 2005-209316 A

In the semiconductor memory circuit described in Patent Document 1, the execution of the refresh operation is delayed until the read operation or late write write operation of the memory cell in response to the conflicting read request or write request is completed. When a complete random access operation is realized like an SRAM, the time required for writing or reading is expressed by the following Equation 1.
(Equation 1); operation cycle time = (read or write operation time) + (refresh operation time)
That is, two cycles (a cycle required for reading or writing and a cycle required for refresh operation) are required.

Here, a case where data processing such as ECC is further performed in the semiconductor memory circuit disclosed in Patent Document 1 will be considered. When a write request is issued, the previous write data stored in the register is written to the memory core after data processing such as ECC processing is performed. If one cycle is used for data processing, the effective write cycle shown in Equation 1 increases to three cycles. The operation when a read request is issued is the same, and one cycle is spent for the restoration process, and the effective read cycle is three cycles. Therefore, when data processing such as ECC processing is performed, the system performance deteriorates by 50%.

Therefore, an object of the present invention is to provide a semiconductor memory circuit, a method for operating the semiconductor memory circuit, and a method for designing the semiconductor memory circuit, which can reduce the time required for writing or reading data.

A semiconductor memory circuit according to the present invention includes a memory core that holds data, and when a read request is issued, reads the read data from the memory core, performs data processing on the read data, and outputs the read data to an external device. Output, when a write request is issued, obtain input data from an external device, perform data processing on the input data, and write to the memory core as write data; and in the first period, Control that controls the operation of the peripheral circuit unit so that data is read or written between the peripheral circuit unit and the memory core, and data processing in the peripheral circuit unit is executed in the second period. Circuit. The control circuit controls the operation of the memory core so that a refresh operation is performed in the second period.

According to the present invention, data is written or read between the peripheral circuit portion and the memory core in the first period. In the second period, data processing is performed in the peripheral circuit portion, and further, a refresh operation of the memory core is performed. That is, the data processing in the peripheral circuit unit and the refresh operation of the memory core are performed in parallel. Therefore, the time spent for writing or reading data can be reduced.

According to the semiconductor memory circuit operating method of the present invention, when the memory core holds data, and when a read request is issued, the peripheral circuit unit reads the read data from the memory core, and A step of performing processing and outputting the output data to an external device, and when a write request is issued, the peripheral circuit unit obtains input data from the external device, performs data processing on the input data, and writes data In the first period, data is read or written between the peripheral circuit unit and the memory core, and data processing in the peripheral circuit unit is executed in the second period. A step of controlling the operation of the peripheral circuit section, and a refresh operation in the second period. As is performed, and a step of controlling the operation of the memory core.

A semiconductor memory circuit design method according to the present invention includes a memory core that holds data, and when a read request is issued, reads the read data from the memory core, performs data processing on the read data, and outputs the data as output data. A peripheral circuit unit that outputs to an external device and obtains input data from the external device when a write request is issued, performs data processing on the input data, and writes the data as write data to the memory core; and a first period The operation of the peripheral circuit unit is controlled such that data is read or written between the peripheral circuit unit and the memory core, and data processing in the peripheral circuit unit is executed in the second period. A method for designing a semiconductor memory circuit including a control circuit. In this design method, a computer generates core macro data indicating a wiring pattern in the memory core, and a computer generates dedicated control macro data indicating a wiring pattern in the peripheral circuit unit and the control circuit; And a computer determining layout of wiring patterns in the semiconductor memory circuit based on the core macro data and the dedicated control macro data, and generating layout data.

According to the present invention, there are provided a semiconductor memory circuit, a semiconductor memory circuit operating method, and a semiconductor memory circuit designing method capable of reducing the time required for writing or reading data.

1 is a circuit diagram schematically showing a semiconductor memory circuit according to a first embodiment. FIG. FIG. 3 is an explanatory diagram for explaining a schematic operation of the semiconductor memory circuit according to the first embodiment. It is a timing chart which shows an example of normal read-out processing operation. 6 is a timing chart illustrating an example of a write processing operation. 6 is a timing chart illustrating an example of an operation during Hit-Read. It is a figure which shows schematically the operating method of the semiconductor memory circuit in 2nd Embodiment. FIG. 6 is a block diagram schematically showing a semiconductor memory circuit according to a third embodiment. 10 is a schematic diagram illustrating an operation method of a semiconductor memory circuit according to a third embodiment. FIG. It is the schematic which shows an example of a structure of a data bus drive circuit. FIG. 10 is a block diagram schematically showing a semiconductor memory circuit according to a fourth embodiment. It is the schematic which shows the design apparatus which concerns on 5th Embodiment. It is a conceptual diagram which shows exclusive control macro data and memory core macro data.

The inventors of the present application focused on the fact that the refresh operation occupies the memory core, but is a circuit operation unrelated to the peripheral circuit (data input / output circuit to bus system circuit). That is, if data processing such as ECC processing can be performed in the peripheral circuit while the refresh operation is performed in the memory core, it is possible to improve reliability and reduce power without degrading cycle performance.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit diagram schematically showing a semiconductor memory circuit 1 according to the present embodiment. As shown in FIG. 1, the semiconductor memory circuit 1 includes a memory core 2, a peripheral circuit unit 5, a control circuit 4, a memory core control circuit 3, a row address generation counter circuit 13, a late write register 6, a HIT determination circuit 7, Synchronizing registers 17-1 to 17-5 and an internal drive buffer 18 are provided.

The memory core 2 is a part that holds data, and includes a memory cell array, a word line selection circuit XD, sense amplifiers SA and SAp, and a column selection circuit YD. The memory cell array includes a region CEL for storing normal data and a region CELp for storing parity data by ECC processing. A word line WL extending along the X direction is arranged so as to penetrate both the region CEL and the region CELp. The word line WL is connected to the word line selection circuit XD. The sense amplifiers SA and SAp are arranged on the column (Y) side of the memory cell array. The column selection circuit YD is arranged on the Y side of the sense amplifiers SA and SAp. Each memory cell included in the region CEL and the region CELp is connected to the column selection circuit YD via a memory cell transistor, a bit line, and a sense amplifier SA or SAp. The column selection circuit YD is connected to the peripheral circuit 5.

The internal drive buffer 18 is connected to the external clock signal input terminal 24, and generates an internal clock signal based on the external clock signal CLK input from the external clock signal input terminal 24. The internal clock signal is supplied to the synchronization registers 17-1 to 17-5 and the control circuit 4.

The synchronization registers 17-1 to 17-5 have a function of inputting and outputting signals between the external device and the semiconductor memory circuit 1. Synchronization registers 17-1 to 17-5 input / output signals in synchronization with the internal clock signal. The synchronization register 17-1 is connected to the address signal input terminal 19, acquires an address signal from the external device via the address signal input terminal 19, and supplies it to the late write register 6. The address signal is a signal indicating an access destination address at the time of writing or reading. The synchronization register 17-2 is connected to the timer signal input terminal 19. A timer signal for time measurement in the refresh cycle is input from the timer signal input terminal 19. The time measurement timer signal is supplied to the control circuit 4 via the synchronization register 17-2. The synchronization register 17-3 is connected to the command signal input terminal 21. A command signal indicating a read request or a write request is input from the command signal input terminal 21. The command signal is supplied to the control circuit 4 via the synchronization register 17-3. The synchronization register 17-4 is connected to the data output terminal 22. The synchronization register 17-4 acquires the output data from the peripheral circuit 5 and outputs it through the data output terminal 22. The synchronization register 17-5 is connected to the data input terminal 23. The synchronization register 17-5 acquires input data from the data input terminal 23 and supplies it to the peripheral circuit unit 5.

Next, the peripheral circuit unit 5 will be described.

The peripheral circuit unit 5 is a part that performs data processing on read data or write data. The peripheral circuit unit 5 includes an input / output data control circuit 12, an ECC 11, a write data register 10, a data bus 9, and a data bus drive circuit 8.

The input / output data control circuit 12 is a part that controls data input / output. When a write request is issued, the input / output data control circuit 12 acquires input data via the synchronization register 17-5 and supplies it to the ECC 11. Further, when a read request is issued, the input / output data control circuit 12 acquires output data from the ECC 11 and outputs it via the synchronization register 17-4.

The ECC 11 is a part that performs ECC processing as data processing. When a write request is issued, the ECC 11 acquires input data, performs ECC processing (encoding processing) on the input data, and generates parity data. The ECC 11 stores input data and parity data in the write data register 10 as write data. When a read request is issued, the ECC 11 acquires data read from the memory core 2 via the data bus 9. The read data includes read data and parity data. The ECC 11 restores the output data based on the parity data and supplies it to the input / output control circuit 12.

The write data register 10 is a part for storing the write data captured when the previous write request is issued. In the write data register 10, the ECC 11 stores the write data captured when the previous write request is issued.

The data bus drive circuit 8 is a circuit that drives the data bus 9. The data bus 9 is connected to the ECC 11, the write data register 10, and the memory core 2. When a read request is issued, the data bus drive circuit 8 drives the data bus 9 to transmit the data sent to the data bus 9.

Subsequently, the late write register 6 will be described. The late write register 6 stores an address signal taken in via the synchronization register 17-1. Here, the late write register 6 stores the address signal captured when the previous write request is issued until the next write request is issued. When a read request is issued, the late transistor 6 fetches an address signal via the synchronization register 17-1, and sends the fetched address signal to the HIT determination circuit 7 together with the address signal at the previous write request. Notice.

The HIT determination circuit 7 has a function of determining whether a normal read operation or a read process by HIT-Read is performed when a read request is issued. HIT-Read is a process for outputting data stored in the write data register 10 instead of outputting data read from the memory core 2. As described above, the write data captured when the previous write request is issued is stored in the write data register 10 until the next write request is issued. Therefore, when the access destination address at the time of the read request matches the write address specified at the time of the previous write request, the desired data is not output even if the data is read from the memory core 2. In order to output desired data, it is necessary to output data stored in the write data register 10. Therefore, the HIT determination circuit 7 determines whether or not the previous write address received from the late write register 6 matches the current read address, and notifies the control circuit 4 of the determination result. If they match, read processing by HIT-Read is performed, and the previous write data stored in the write data register 10 is output via the data bus 9, ECC 11, and input / output control circuit 12. . On the other hand, if they do not match, read processing is performed by normal operation, and the data stored in the memory core 2 is output via the peripheral circuit 5.

The row address generation counter circuit 13 is a circuit that generates a refresh target address signal. The refresh target address signal indicates a row address to be refreshed.

The memory core control circuit 3 is a circuit that controls the operation of the memory core 2. The memory core control circuit 3 includes a multiplexer 14, a row control circuit 15, and a column control circuit 16. The multiplexer 14 acquires an address signal from the late write register 6 and supplies it to the row control circuit 15 when data is read from or written to the memory core. Further, the multiplexer 14 acquires a refresh target row address signal from the row address generation counter circuit 13 and supplies it to the row control circuit 15 during the refresh operation. When the row control circuit 15 obtains the address signal via the multiplexer 14, the row control circuit 15 generates the row address signal RA and the sense enable signal SE, and supplies them to the row selection circuit XD and the sense amplifiers SA and SAp of the memory core 3. The column control circuit 16 acquires an address signal from the late write register 6 when reading or writing data to the memory core, generates a column address signal CA based on the acquired address signal, and generates the memory core 2 To the column selection circuit YD. During the refresh operation, the column control circuit 16 does not generate a column address signal.

During the refresh operation, the memory core control circuit 3 reads the data stored at the refresh target row address in the memory cell array to the sense amplifiers SA and SAp, amplifies the sense amplifiers SA and SAp, and restores the data to the memory cell array. . On the other hand, at the time of reading, data stored at a specified address in the memory cell array is sent to the data bus 9 via the sense amplifier and column selection circuit YD. At the time of writing, data sent from the data bus 9 to the column selection circuit YD is written to a specified address via the sense amplifier.

The control circuit 4 is a circuit that controls operations of the peripheral circuit 5, the memory core control circuit 3, and the late write register 6. When the control circuit 4 acquires the command signal via the synchronization register 17-3, the control circuit 4 controls the operations of the peripheral circuit 5 and the memory core control circuit 3 so that the reading process or the writing process is performed based on the command signal. To do. If the command signal is a signal indicating a read request, the control circuit 4 performs normal reading processing or reading processing by HIT-Read based on the determination notification received from the HIT determination circuit 7. To decide. The control circuit 4 has a function of issuing a refresh command based on the internal clock signal supplied from the internal buffer 18 and the time measurement timer signal supplied from the synchronization register 17-2. . When the refresh command is issued, the control circuit 4 controls the operation of the memory core control circuit 3 so that the refresh operation is executed. Further, at the end of the refresh operation, the control circuit 4 accesses the row address generation counter 13 and counts up the row address to be refreshed.

Subsequently, an operation method of the semiconductor memory circuit 1 according to the present embodiment will be described.

FIG. 2 is an explanatory diagram for explaining a schematic operation of the semiconductor memory circuit 1 according to the present embodiment. FIG. 2 shows an operation during a normal read process and an operation during a write process. The operation shown in FIG. 2 is realized by the control circuit 4.

As shown in FIG. 2, when a read request is issued as a command signal, the control circuit 4 reads data from the memory core 2 to the peripheral circuit unit 5 in the first period. In the second period, the ECC processing of the read data is executed in the ECC 11 in the peripheral circuit unit 5. Here, when the refresh command is issued in the control circuit 4 immediately before the command signal is input, the control circuit 4 performs the operation of the memory core control circuit 3 so that the refresh operation is executed in the second period. Control. Since the ECC process and the refresh operation are executed in parallel, the time required for reading data does not increase despite the ECC process.

On the other hand, when a write request is issued as a command signal, the control circuit 4 writes data from the peripheral circuit unit 5 to the memory core 2 in the first period. Specifically, data at the time of the previous write request stored in the write data register 10 is written into the memory core 2. In the second period, ECC processing is performed on the data input by the current write request, and the processed data is stored in the write data register 10 as write data. When the refresh command is issued in the control circuit 4 immediately before the command signal is input, the control circuit 4 controls the operation of the memory core control circuit 3 so that the refresh operation is executed in the second period. That is, even when a write request is issued, the ECC process and the refresh operation are executed in parallel. Therefore, the time required for data writing does not increase despite the ECC processing being performed.

When read processing by Hit-Read is performed, the data stored in the write data register 10 is sent to the data bus 9 as described above, via the ECC 11 and the input / output control circuit 12. Is output. For this reason, the read processing by Hit-Read is not related to the operation in the memory core 2. Therefore, when performing a read process using Hit-Read, the execution timing of the refresh operation is not limited.

Further, according to this embodiment, since the late write method is adopted, the configuration of the control circuit 4 is not complicated. This point will be described below.

When the late write method is not adopted, the data captured when the write request is issued is subjected to ECC processing and immediately written to the memory core 2. That is, when a write request is issued, ECC processing is performed first, and then data is written to the memory core 2. On the other hand, when a read request is issued, data is first read from the memory core 2 to the peripheral circuit unit 5, and then ECC processing is performed. That is, the order in which the ECC processing is performed is reversed between the writing processing and the reading processing. As a result, the control circuit 4 needs to realize a complicated function, and the configuration of the control circuit 4 becomes complicated. On the other hand, in this embodiment, since the late write method is adopted, the data at the time of the previous write request subjected to the ECC processing is stored in the write data register 10. Therefore, when a write request is issued, data can be written to the memory core 4 first, and thereafter, ECC processing can be performed on the data captured by the current write request. The order in which ECC processing is performed does not change between the read processing and the write processing. Therefore, functions necessary for the control circuit 4 can be simplified, and the configuration of the control circuit 4 can be simplified.

Subsequently, an operation method of the semiconductor memory circuit 1 according to the present embodiment will be described in detail.

First, the normal reading process will be described. FIG. 3 is a timing chart showing an example of a normal read processing operation. FIG. 3 shows an internal clock signal CLK, an address signal ADD, a command signal COMM, an internal timer (timer) based on a measurement timer signal, a refresh target address signal AFC, a row address signal RA, a sense enable signal, and a word line signal (SE). WL), column address signal CA, data held by the data bus 9 (DBUS), data held by the ECC 11 (ECC), data at the previous write request held by the late write register, data held by the write data register A time change of the (WD register), the output data Dout, and the input data Din is shown. FIG. 3 shows a time change from the first clock cycle to the third clock cycle.

In the example shown in FIG. 3, immediately before the first clock cycle, a signal indicating the address A1 is issued as the address signal ADD, and a signal RE indicating a read request is issued as the command signal COMM. Also, immediately before the first clock cycle, a refresh command is issued in the control circuit 4 by the timer. The late write register 6 stores a signal indicating the address A0 as the address of the write data when the previous write request is issued.

In the first clock cycle, the address signal ADD and the command signal COMM are taken into the late write register 6 and the control circuit 4, respectively, at the timing when the internal clock signal rises. The address signal (A1) taken into the late write register 6 is notified to the HIT determination circuit 7 together with the address signal (A0) at the time of the previous write request issuance. The HIT determination circuit 7 compares the address signal (A1) with the address signal (A0) and notifies the control circuit 4 of the comparison result. Since the address signal (A1) does not match the address signal (A0), the control circuit 4 executes a normal read process.

The control circuit 4 reads data from the memory core 2 to the data bus 9 in the first clock cycle. That is, in the first clock cycle, the row address RA signal is activated based on the address signal A1, the word line is selected by the word line signal WL, and data is read from the bit line to the sense amplifiers SA and SAp. When the sense enable signal SE is activated, the data read from the Bit line is amplified by the sense amplifier SA. Further, when the column selection signal CA is activated, a column is selected, and read data Q0E is read from the sense amplifiers SA and SAp to the data bus 9. The read data Q0E also includes ECC parity data.

Subsequently, in the second clock cycle, the data Q0E read to the data bus 9 is transmitted to the ECC 11. In the ECC 11, error correction processing is performed on the read data Q0E, and output data Q0 is generated.

On the other hand, the control circuit 4 performs the refresh operation of the memory core 2 in synchronization with the internal clock signal in the second clock cycle. That is, in the second clock cycle, the row address signal RA is activated (CA is inactivated), and the Word line and the sense amplifier SA are selected based on the refresh target address AFC1. As a result, data is restored between the memory cell, the bit line, and the sense amplifiers SA and SAp. When the refresh operation is completed, the control circuit 4 returns the timer to OFF and counts up the refresh target address to AFC2.

The output data Q0 generated by the ECC 11 is output via the input / output control circuit 12 (Dout) in the third clock cycle.

As described above, at the time of normal reading, data is read from the memory core 2 to the peripheral circuit unit 5 (data bus 9) in the first clock cycle, and the refresh operation and ECC processing are performed in the second clock cycle. .

Next, the writing process will be described. FIG. 4 is a timing chart showing an example of the write processing operation. FIG. 4 shows temporal changes of each signal and data as in FIG. FIG. 4 shows a time change from the first clock cycle to the fourth clock cycle.

In the example shown in FIG. 4, immediately before the first clock cycle, a signal WE indicating a write request is provided as a command signal, a signal indicating an address A2 is provided as an address signal ADD, and D2 is provided as input data. The write data register 10 stores data D0E as data at the time of the previous write request. The late write register 6 stores a signal indicating the address A0 as a write address at the previous write request. Also, immediately before the first clock cycle, a refresh command is issued based on a timer.

When the internal clock signal CLK rises in the first clock cycle, the command signal WE is taken into the control circuit 4. The write data stored in the write data register 10 is written into the memory core 2 by the control circuit 4. That is, the row address signal RA, the sense enable signal SE, and the column selection signal CA are activated based on the previous write address A0 taken in the late write register 6, and the data D0E stored in the write data register 10 is activated. Are written to the memory core 2 via the data bus 9. Further, the current write address A2 is taken into the late write register 6. The input data D2 is supplied to the ECC 11 via the input / output control circuit 12.

Note that the refresh operation is not executed in the first clock cycle.

Subsequently, in the second clock cycle, the ECC 11 performs ECC processing on the input data D2, and the processed data is stored in the write data register 10 as write data D2E. Further, the control circuit 4 executes the refresh operation in synchronization with the internal clock signal CLK in the second clock cycle. That is, based on the refresh address AFC2, the row address signals RA and SE are activated (CA is deactivated), and the data stored in the memory cell is refreshed. After completing the refresh operation, the control circuit 4 returns the timer request to off and counts up the refresh target address to AFC3.

In the example shown in FIG. 4, a signal WE indicating a write request is issued as a command signal also in the subsequent third clock cycle. The write address is A3 and the input data is D3. In this case, the data D2E stored in the write data register 10 is written to the memory core 2 in the third clock cycle. That is, the row address signal RA, the sense enable signal SE, and the column selection signal CA are activated based on the address A2 fetched in the first clock cycle, and the data D2E fetched in the write data register 10 is changed to the data bus. 9 to the memory core 2. The address A3 is taken into the late write register 6. The input data D3 is supplied to the ECC 11 via the input / output control circuit 12, is encoded by the ECC 11, and is taken into the write data register 10 as write data D3E in the fourth clock cycle.

Subsequently, a reading process by Hit-Read will be described. FIG. 5 is a timing chart showing an example of the operation during Hit-Read. FIG. 5 shows temporal changes in the signal and data from the first clock cycle to the third clock cycle.

In the example shown in FIG. 5, immediately before the first clock cycle, a command signal RE indicating a read request and an address signal indicating a read address A0 are given. The late write register stores a signal indicating A0 as a write address at the time of the previous write request. The write data register 10 stores data D0E. Also, immediately before the first clock cycle, a refresh command is issued based on a timer.

At the rise of the internal clock signal CLK in the first clock cycle, the address signal A0 is taken into the late write register 6 and the command signal RE is taken into the control circuit 4. The late write register 6 notifies the HIT determination circuit 7 of the fetched address signal A0 and the write address signal A0 at the previous write request. The HIT determination circuit 7 determines whether or not these signals match, and notifies the control circuit 4 of the determination result. Since these signals match, the control circuit 4 performs a read process by Hit-Read. That is, the write data D0E stored in the write data register 10 is sent to the data bus 9 as read data Q0E.

In the second clock cycle, data Q0E is sent from the data bus 9 to the ECC 11. In the ECC 11, error correction processing is performed on the data Q0E, and output data Q0 is generated. The control circuit 4 performs a refresh operation of the memory core 2 in the second clock cycle. The output data Q0 is output via the input / output control circuit 12 in the next third clock cycle. In the case of read processing by Hit-Read, there is no problem even if the refresh operation is executed in the first clock cycle.

As described above, according to the present embodiment, even if a refresh command is issued when a command signal is issued, the refresh operation is executed after the data writing or reading to the memory core 2 is completed. Random access can be realized.

Further, while the data processing (ECC processing) is being performed in the peripheral circuit unit 5, the refresh operation of the memory core 2 is executed. Therefore, the ECC function can be mounted in the semiconductor memory circuit 1 without causing a cycle time overhead.

In addition, since the late write method is employed, data is read or written first between the memory core 2 and the peripheral circuit unit 5 at the time of reading or writing, and then the peripheral circuit unit 5 is used later. ECC processing can be performed in It is not necessary to change the order in which the ECC processing is performed between the reading processing and the writing processing, and a complicated function is not required for the control circuit 4. Therefore, the control circuit 4 can be designed by utilizing the conventional timing design assets.

(Second Embodiment)
Next, the second embodiment will be described. FIG. 6 is a diagram schematically showing an operation method of the semiconductor memory circuit 1 in the present embodiment. In the first embodiment, data is read from or written to the memory core 2 in the first clock cycle, and ECC processing and a refresh operation are performed in the second clock cycle. That is, the ECC process and the refresh operation are executed in synchronization with the clock signal. On the other hand, in this embodiment, when the reading or writing of data with respect to the memory core 2 is completed, the ECC processing and the refresh operation are continuously performed regardless of the clock signal. About another point, since the structure similar to 1st Embodiment is employable, detailed description is abbreviate | omitted.

As shown in FIG. 6, during normal read processing, when data is read from the memory core 2 to the peripheral circuit unit 5 in the first period, the control circuit 4 detects that fact. Then, after the data is read, the control circuit 4 starts the operation in the second period regardless of the timing of the internal clock signal, and performs the ECC process and the refresh operation. In addition, when data is written from the peripheral circuit unit 5 to the memory core 2 in the first period during the writing process, the control circuit 4 detects that fact. Then, after data is written to the memory core 2, the operation in the second period is started regardless of the timing of the internal clock signal, and the ECC process and the refresh operation are performed. Note that the memory core 2 is inactive at the time of read processing by Hit-Read, and therefore does not affect the refresh operation. Therefore, there is no problem even if the refresh operation and the read operation overlap in timing.

According to the present embodiment, the circuit operation (ECC processing and refresh operation) in the second period is started regardless of the clock signal. Therefore, the waiting time until the clock signal rises can be eliminated, and the data reading or writing speed can be further increased.

The control circuit 4 can detect the end of reading or writing of data with respect to the memory core 2 by monitoring the row address signal RA, for example.

(Third embodiment)
Subsequently, a third embodiment will be described. FIG. 7 is a block diagram schematically showing the semiconductor memory circuit 1 according to the present embodiment. As shown in FIG. 7, in this embodiment, the peripheral circuit unit 5 is not provided with the ECC 11, and the data bus 9 is connected to the input / output control circuit 12. Further, in the memory core 2, no ECC processing area CELp is provided in the memory cell array. Other points are the same as those in the above-described embodiment.

FIG. 8 is a schematic diagram showing an operation method of the semiconductor memory circuit 1 according to the present embodiment.

During normal read processing, data is read from the memory core 2 to the data bus 9 in the first period. The read data is transmitted through the data bus 9 in the second period and output via the input / output control circuit 12. Here, when a refresh command has been issued, the control circuit 4 performs a refresh operation in the second period. As in the second embodiment, the control circuit 4 detects that data reading from the memory core 2 to the data bus 9 is completed, and performs the operation in the second period regardless of the clock signal. Start continuously.

On the other hand, at the time of the writing process, the data given at the time of the previous writing process is written from the write data register 10 to the memory core 2 via the data bus 9 in the first period. Data given by the current writing process is transmitted to the data bus 9 and written to the write data register 10 in the second period. When the refresh command has been issued, the control circuit 4 performs a refresh operation in the second period. Similar to the second embodiment, when the control circuit 4 detects that the data writing to the memory core 2 has been completed, the control circuit 4 continuously starts the operation in the second period regardless of the clock signal.

According to the present embodiment, the data transmission process on the data bus 9 and the refresh operation are executed in parallel. Therefore, as in the above-described embodiment, the time required for data writing or reading can be shortened.

In this embodiment, since the data transmission process and the refresh operation are executed in parallel, it is easy to introduce a circuit for reducing the power of data transfer in the data bus 9. This point will be described below.

In recent system LSIs, the scale of logic circuits is increasing in order to improve system performance. Along with this, the memory has also been increased in capacity. Here, a semiconductor memory circuit such as a DRAM may be built in the system LSI. In recent system LSIs, power reduction is a major issue. Therefore, when built in a system LSI, a low power supply voltage and a low current are also strongly required for the semiconductor memory circuit. When the semiconductor memory circuit is built in the system LSI, an interface circuit with the outside of the chip is not necessary. As a result, the semiconductor memory circuit often has a multi-bit data specification. Further, the progress of lowering the power supply voltage due to the miniaturization of the transistors is preceded by the logic LSI than the single memory product. The reduction of the power supply voltage due to the miniaturization of the transistor tends to be strict for the stability of the data retention of the memory cell (soft error, memory cell hold characteristic fluctuation, etc.). From these viewpoints, the semiconductor integrated circuit 1 is also required to have low power.

In order to realize low power in the semiconductor memory circuit 1, it is conceivable to introduce a low current technology in the data bus drive circuit 8. However, when a current reduction technique is introduced into the data bus drive circuit 8, generally, the data transfer speed on the data bus 9 is reduced. As a result, for example, at the time of write processing, the timing at which data is sent from the data bus 9 to the memory core 2 is delayed, the timing at which the column activation signal CA is activated is also delayed, and the timing at which the word line selection is completed is also delayed. . That is, the entire writing operation is delayed, and the time required for writing data becomes long. In addition, the activation timing of the memory core 2 may be different between the writing process and the reading process, and needs to be individually controlled. As a result, the design of the control circuit 4 becomes complicated and the area increases. Even when the memory core 2 is divided into a plurality of banks and a bank configuration is employed in which each bank can be accessed individually, access to a specific bank may continue, and the same problem arises.

On the other hand, according to the present embodiment, since the driving process of the data bus 9 is executed in parallel with the refresh operation, even if some time is spent on the data transmission process in the data bus 9, The overall operating time is not significantly affected. Therefore, it becomes easy to introduce a technique for reducing the power of the driving process of the data bus 9.

In order to reduce the drive processing of the data bus 9, for example, it is conceivable to devise the configuration of the data bus drive circuit 8. FIG. 9 is a schematic diagram showing an example of the configuration of the data bus drive circuit 8. In the example shown in FIG. 9, the data bus drive circuit 8 includes a data encoding circuit 25 and a low amplitude circuit 26. The data encoding circuit encodes data transmitted through the data bus 9 so that the number of data transition bits is reduced. The amplitude reducing circuit 26 has a dedicated driver / receiver and drives the data bus 9 by a low amplitude operation.

In addition, as a technique for driving the data bus 9 with low power, a technique for reducing the size of a transistor used in the data bus drive circuit 8, a technique for reducing the bus wiring width in the data bus 9, a technique for introducing a repeater, A technique for reducing the appearance of the driving load by hierarchizing the bus signal lines in the data bus 9, and a technique for transferring multiple bits of data by making the bus in the data bus 9 multi-level, Etc.

The bus drive current is the most power consuming part of the semiconductor memory circuit 1. Therefore, by introducing a technique for driving the data bus 9 with low power, the semiconductor memory circuit 1 can be effectively reduced in power. Furthermore, part of the low power technology has an effect of reducing peak current. Therefore, it is effective in reducing noise. Low noise suppresses fluctuations in the power line. As a result, the operation margin of the sense amplifier SA in the memory core 2 can be expanded, and problems due to noise interference with other circuits adjacent to the semiconductor memory circuit 1 can be prevented. Conventionally, as a countermeasure against power increase and noise, a stabilization capacitor (decoupling capacitor) has been inserted between power supplies in the semiconductor memory circuit 1. Further, in order to reduce the power supply wiring resistance, the wiring width is set large, and a metal layer is added as necessary. Further, a process for reducing the power line inductance of the package has been performed. According to the present embodiment, low power and low noise are realized, so that the cost required for the techniques employed for reducing the power and noise can be reduced.

(Fourth embodiment)
Subsequently, a fourth embodiment will be described. FIG. 10 is a block diagram schematically showing the semiconductor memory circuit 1 according to the present embodiment. As shown in FIG. 10, in this embodiment, a serial / parallel conversion circuit 28 is used instead of the ECC 11. In the memory cell array, the region CELp is not provided. About another point, since the structure similar to 1st Embodiment is employable, detailed description is abbreviate | omitted.

In the semiconductor memory circuit 1 according to the present embodiment, serial data is input from an external device by a burst operation using a plurality of clock cycles during a write process. The input serial data is supplied to the serial / parallel conversion circuit 28 via the input / output control circuit 12, converted into parallel data by the serial / parallel conversion circuit 28, and stored in the write data register 10. The parallel data stored in the write data register 10 is written into the memory core 2 in the next write process. On the other hand, during normal read processing, parallel data is read from the memory core 2 to the serial / parallel conversion circuit 28. The parallel conversion circuit 28 converts the read parallel data into serial data and outputs the serial data via the input / output control circuit 12.

Here, in this embodiment, as in the first embodiment, during the write process, the parallel data generated at the time of the previous write request is written from the write data register 10 to the memory core 2 in the first period. It is. In the second period, the serial data captured by the current burst operation is converted into parallel data, and a refresh operation is performed.

On the other hand, during normal read processing, parallel data is read from the memory core 2 to the serial / parallel conversion circuit 28 in the first period. Then, in the second period, the conversion process in the serial / parallel conversion circuit 28 and the refresh operation are executed.

That is, according to the present embodiment, the serial data and parallel data conversion process is executed in parallel with the refresh operation. Therefore, as in the above-described embodiment, the time required for writing or reading data can be shortened.

Note that the burst length at the time of input / output may be changed to be longer. Further, the CLK cycle used when serially inputting / outputting burst data may be changed so as to be faster. Then, a write process, a read process, and a refresh operation may be executed corresponding to multiple cycles of two cycles or more. Further, input / output data may be input / output using both the rise edge and the fall edge in the clock signal. Further, the clock signal for the memory core 2 and the clock signal used in the synchronization registers 17-1 to 17-5 may be provided separately.

(Fifth embodiment)
Subsequently, a fifth embodiment will be described. In the present embodiment, a design apparatus for the semiconductor memory circuit 1 according to the first embodiment will be described. FIG. 11 is a schematic diagram showing the design apparatus 27 according to the present embodiment. The design device 27 (DRAM design device) according to the present embodiment generates semiconductor memory circuit data based on the dedicated control macro data and the memory core macro data. The design device 27 is realized by the CPU executing a design program stored in a ROM (Read Only Memory) or the like.

FIG. 12 is a conceptual diagram showing dedicated control macro data and memory core macro data. As shown in FIG. 12, the memory core 2 portion of the semiconductor memory circuit 1 is defined as a memory core macro. The memory core macro data is data indicating a wiring pattern in the memory core. Further, in the semiconductor memory circuit 1, portions other than the memory core macro (peripheral circuit unit 5, control circuit 4, HIT determination circuit 7, late write register 6, row address generation counter circuit 13, memory core control circuit 3, synchronization register 17-1 to 17-5) are defined as dedicated control macros. The dedicated control macro data is data indicating a wiring pattern in the dedicated control macro.

In this embodiment, the semiconductor memory circuit 1 is defined in the Wrapper at a higher level than the dedicated control macro and the memory core macro. That is, the design device 27 determines the overall wiring pattern of the semiconductor memory circuit 1 by determining the connection relationship between the dedicated control macro and the memory core macro.

Thereby, the design data of the existing memory core 2 part can be used as it is, and the semiconductor memory circuit 1 can be efficiently developed by designing only the dedicated control macro part. When the semiconductor memory circuit 1 is a built-in macro mounted inside the system LSI, dedicated control macro data can be generated using an automatic design environment in the same way as other logic units, further reducing the design TAT. can do. In addition, since the dedicated control macro portion is made into a soft macro, the degree of layout freedom is increased, and the area required for the entire chip can be reduced.

Claims

A memory core that holds data,
When a read request is issued, read data is read from the memory core, data processing is performed on the read data, and output as output data to an external device. When a write request is issued, input data is received from the external device. A peripheral circuit unit that performs data processing on the input data and writes the data as write data to the memory core;
Data is read or written between the peripheral circuit portion and the memory core in the first period, and data processing in the peripheral circuit portion is executed in the second period. A control circuit for controlling the operation;
Comprising
The control circuit is a semiconductor memory circuit that controls the operation of the memory core so that a refresh operation is performed in the second period.
A semiconductor memory circuit according to claim 1,
The peripheral circuit unit includes a write data register that stores write data generated when a previous write request is issued,
When a write request is issued, the control circuit writes the previous write data from the write data register to the memory core in the first period, and the current write data is written to the write data in the second period. A semiconductor memory circuit for controlling the operation of the peripheral circuit unit so as to be stored in a register.
A semiconductor memory circuit according to claim 1 or 2,
The peripheral circuit unit includes an ECC processing circuit that performs an encoding process on the input data to generate the write data, and performs a restoration process on the read data to generate the output data. ,
The control circuit is a semiconductor memory circuit that controls the operation of the ECC processing circuit so that the encoding process or the restoration process is executed in the second period.
A semiconductor memory circuit according to any one of claims 1 to 3,
The peripheral circuit unit generates the write data by converting the input data into parallel data when the input data is serial data, and outputs the read data when the read data is parallel data. A serial / parallel conversion circuit that generates the output data by converting the data into serial data;
The semiconductor memory circuit that controls the operation of the serial / parallel conversion circuit so that the conversion process is performed in the second period.
A semiconductor memory circuit according to claim 2,
The peripheral circuit section is
A data bus connected to the memory core;
A data bus driving circuit for driving the data bus,
When a read request is issued, the control circuit sends the read data from the memory core to the data bus in the first period, and the read data transmits the data bus in the second period. And a semiconductor memory circuit for controlling the operation of the peripheral circuit section.
A semiconductor memory circuit according to claim 5, comprising:
The write data register is connected to the data bus;
When a write request is issued, the control circuit writes the previous write data from the write data register to the memory core via the data bus in the first period, and the current period in the second period. A semiconductor memory circuit for controlling the operation of the peripheral circuit section so that the write data of the memory is written to the write data register.
A semiconductor memory circuit according to claim 5 or 6,
The semiconductor integrated circuit including a data encoding circuit, wherein the data bus driving circuit encodes data sent to the data bus so that the number of transition bits is reduced.
A semiconductor memory circuit according to any one of claims 5 to 7,
The data bus drive circuit includes a low amplitude circuit that drives the data bus by a low amplitude operation.
Semiconductor integrated circuit.
A semiconductor memory circuit according to any one of claims 1 to 8,
The control circuit is a semiconductor memory circuit configured to switch between an operation in the first period and an operation in the second period based on a reference clock signal supplied from an external device.
A semiconductor memory circuit according to any one of claims 1 to 8,
The control circuit detects that data reading or writing to the memory core is completed, and switches the operation in the first period and the operation in the second period based on the detection result. circuit.
A memory core holding data; and
When a read request is issued, the peripheral circuit unit reads the read data from the memory core, performs data processing on the read data, and outputs to the external device as output data;
When a write request is issued, the peripheral circuit unit obtains input data from an external device, performs data processing on the input data, and writes the write data to the memory core;
Data is read or written between the peripheral circuit portion and the memory core in the first period, and data processing in the peripheral circuit portion is executed in the second period. Controlling the operation;
Controlling the operation of the memory core so that a refresh operation is performed in the second period;
A method for operating a semiconductor memory circuit comprising:
When a read request is issued with a memory core that holds data, read data is read from the memory core, data processing is performed on the read data, and output as output data to an external device, and a write request is issued A peripheral circuit unit that obtains input data from an external device, performs data processing on the input data, and writes the input data to the memory core as write data; and in the first period, the peripheral circuit unit and the memory core Of a semiconductor memory circuit including a control circuit that controls the operation of the peripheral circuit unit so that data is read or written between them and data processing in the peripheral circuit unit is executed in the second period A design method,
A computer generating core macro data indicating a wiring pattern in the memory core;
A computer generating dedicated control macro data indicating a wiring pattern in the peripheral circuit section and the control circuit;
A computer determining layout of wiring patterns in the semiconductor memory circuit based on the core macro data and the dedicated control macro data, and generating layout data;
A method for designing a semiconductor memory circuit comprising: