JP2000030455A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To pre-charge accurately internal data bus lines to the same voltage level and to read out data accurately at high speed. SOLUTION: The same power source voltage as the power source Vccsa given to a sense amplifier circuit 4a is given to the internal data bus lines I/O, I/O* via (p) channel MOS transistors PQa, PQb. Thereby, pre-charge voltage of the internal data bus lines can be made to a sense power source voltage level, and the internal data bus lines can be accurately pre-charged to a sense power source voltage level via a pre-charge circuit even at the time of decreasing of the sense power source voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to power supply voltage allocation for a peripheral circuit coupled to an internal data bus.

[0002]

2. Description of the Related Art FIG. 14 schematically shows a structure of a main part of a conventional semiconductor memory device. FIG. 14 schematically shows a configuration of a memory array and peripheral circuits related to data reading.

In FIG. 14, in a memory cell array MA, memory cells MC are arranged in a matrix, word lines WL are provided corresponding to each row of memory cells MC, and corresponding to each column of memory cells MC. Bit line pair BLP is provided. FIG. 14 representatively shows one word line WL and one bit line pair BLP. Bit line pair B
LP is a bit line B for transmitting complementary data signals.
L and / BL. The memory cell MC is connected to the word line W
It is arranged corresponding to the intersection between L and one of bit lines BL and / BL. In FIG. 14, memory cells MC are arranged at intersections of word lines WL and bit lines BL. The memory cell MC includes a capacitor MQ for storing information and a memory capacitor M in response to a signal potential on the word line WL.
Access transistor MT including an n-channel MOS transistor connecting Q to corresponding bit line BL is included.

For each bit line BLP, there is provided a sense amplifier 102 activated according to the voltage on sense drive lines 101p and 101n and differentially amplifying the voltages of bit lines BL and / BL. Sense drive line 10
1p and 101n have sense amplifier activation signal / S
Internal power supply voltage Vccs and ground voltage Vs are applied to sense drive lines 101p and 101n in response to EN and SEN.
A sense amplifier activating circuit 103 transmitting s is provided. Sense amplifier activating circuit 103 is turned on in response to activation of sense amplifier activating signal / SEN, and conducts to transmit internal power supply voltage Vccs onto sense drive line 101p, and sense amplifier activating signal SEN Becomes conductive in response to the activation of
n channel MOS transmitting s to sense drive line 101n
The transistor 103b is included.

Further, as a peripheral circuit for reading data, it operates using internal power supply voltage Vccp as an operating power supply voltage, decodes internal column address signal Adc, and sets column select line CSL corresponding to the addressed column to a column select line CSL. A column selection signal generation circuit 104 driven to a selected state and a bit line pair are provided corresponding to each of the bit line pairs. The column selection signal generation circuit 104 is turned on when a column selection signal from column selection signal generation circuit 104 is activated, and the corresponding bit line pair BLP is internally provided. Column select gate 105 connected to data bus IOP and internal power supply voltage Vccp operate as one operation power supply voltage to operate, and precharge instruction signal IO
The precharge control circuit 106 for generating the EQ, and conducting in response to activation of the IO line precharge instruction signal IOEQ from the precharge control circuit 106, and the internal data bus lines I / O and I / O of the internal data bus IOP. A precharge circuit 107 for precharging O * to the level of internal power supply voltage Vccp, and a memory cell operating with internal power supply voltage Vccp as one operation power supply voltage, activated at the time of data reading, and read onto internal data bus IOP Preamplifier 108 for amplifying data to generate internal read data RD
Is provided.

Column select gate 105 includes transfer gates 105a and 105 provided between bit lines BL and / BL and internal data bus lines I / O and I / O *.
5b. IO line precharge circuit 107 is rendered conductive when IO line precharge instructing signal IOEQ is activated, and provides internal power supply voltage V on internal data bus lines I / O and I / O *.
n channel MOS transistor 107 transmitting ccp
a and 107b. Next, the operation of the semiconductor memory device shown in FIG. 14 will be described with reference to a signal waveform diagram shown in FIG.

First, when a memory cycle starts, a word line selecting circuit (not shown) drives a word line WL arranged corresponding to an addressed row to a selected state in accordance with an internal row address signal, and its voltage level is increased. To rise. As the voltage of selected word line WL rises, access transistor MT included in memory cell MC connected to selected word line WL is turned on, and corresponding memory capacitor MQ is connected to corresponding bit line BL (or / BL). . According to the amount of charge stored in the memory capacitor MQ,
The bit line BL (or / B) connected to the selected memory cell
The voltage of L) changes. In FIG. 15, bit line B in the case where selected memory cell MC stores H-level information
The signal waveforms of L and / BL are shown as an example. Bit line / BL (BL) forming a pair holds a precharge voltage level of a predetermined intermediate voltage level since the selected memory cell is not connected.

When the voltage difference between bit lines BL and / BL is sufficiently enlarged, sense amplifier activation signals SEN and / SEN are driven to an active state at a predetermined timing, and ground voltage is applied to sense drive lines 101n and 101p, respectively. Vss and internal power supply voltage Vccs are transmitted, and sense amplifier 102 is activated. Thereby, the bit line B
L and / BL are driven to internal power supply voltage Vccs and ground voltage Vss levels according to the storage information of the memory cell.

When the sensing operation is completed, a so-called "column interlock" period is completed, and a column selecting operation becomes possible. At the time of the column selection operation, first, precharge control circuit 106 sets IO line precharge instruction signal IOEQ to an inactive state of L level, and IO line precharge circuit 1
07 is deactivated. IO line precharge circuit 107
Are n channel MOS transistors 107a and 107
7b, and IO line precharge instruction signal IOEQ from precharge control circuit 106 is at the level of internal power supply voltage Vccp when activated. IO line precharge circuit 107 also receives internal power supply voltage Vccp. Therefore, internal data bus lines I / O and I / O * are in a floating state at a voltage level of voltage Vccp-Vth. Here, Vth indicates a threshold voltage of n-channel MOS transistors 107a and 107b included in IO line precharge circuit 107.

Next, column select signal generating circuit 104 is activated, decodes applied column address signal Adc, and drives column select line CSL corresponding to the selected column to a selected state. Thereby, column select gate 105 (transfer gates 105a and 105b) is turned on, and bit lines BL and / BL corresponding to the selected column are connected to internal data bus lines I / O and I / O *, respectively. Then
Preamplifier 108 is activated by preamplifier activation signal PAE, and amplifies memory cell data read onto internal data bus IOP to generate internal read data RD. This internal read data RD is output to the outside via an output circuit (not shown).

The internal power supply voltage Vccs is equal to the internal power supply voltage Vcc.
The voltage level is lower than ccp. This is because the power supply voltage Vccs is applied to the memory cell capacitor MQ to prevent the insulating film of the memory cell capacitor from being broken. The selected word line WL is driven to a voltage level that is usually about 1.5 times the internal power supply voltage Vccs. Therefore, internal power supply voltage Vc
By lowering cs, a high voltage is prevented from being applied to the gate insulating film of the access transistor of the selected memory cell, and the reliability of the element is assured. On the other hand, in the peripheral circuit, internal power supply voltage V
An internal power supply voltage Vccp at a voltage level higher than ccs is applied to operate peripheral circuits at high speed.

[0012]

SUMMARY OF THE INVENTION By using an n-channel MOS transistor as a precharge transistor for precharging an internal data bus line, the voltage amplitude of the internal data bus line is reduced and high-speed access is realized. . That is, the internal data bus line I / O
And the precharge voltage level of I / O *
By setting to cp-Vth, the voltage amplitude of the internal data bus line during data writing and reading is reduced as much as possible. In addition, by forming as much as possible in the same substrate region as the n-channel MOS transistor in the memory cell array portion, it is possible to eliminate the need for a region such as PN isolation.

However, when the voltage level of the internal power supply voltage (hereinafter referred to as the peripheral power supply voltage) Vccp applied to the peripheral circuit decreases, the precharge control circuit 106
However, since the peripheral power supply voltage Vccp operates using the operation power supply voltage, the H level of the precharge instruction signal IOEQ also decreases accordingly. In this case, the following problem occurs.

FIG. 16 is a diagram for explaining a problem when the peripheral power supply voltage drops. When IO line precharge instructing signal IOEQ attains an L level, a column selecting operation is performed, a selected bit line pair is connected to internal data bus lines I / O and I / O *, and memory cell data is transferred to internal data bus line I / O *. / O and I / O *. One of internal data bus lines I / O and I / O * is supplied by sense amplifier 102 to an internal power supply voltage (hereinafter referred to as a sense power supply voltage) Vcc transmitted by the sense amplifier onto a bit line.
Driven to s level. On the other hand, the voltage level of the other internal data bus line decreases. The voltage drop amount of the internal data bus line at the time of data reading is determined by the discharge capability of the sense amplifier provided for the selected bit line pair,
The sense amplifier is merely required to charge and discharge the parasitic capacitance of the corresponding bit line pair, has a reduced current driving capability, and has a voltage level of an internal data bus line to which L level data is transmitted. Decreases slowly.

Preamplifier activation signal PAE is activated at a predetermined timing after the column selection operation is performed. Normally, preamplifier activation signal PAE is activated with a change point of the column address signal as a trigger. Therefore, during normal operation, internal data bus line I
When the voltage difference between / O and I / O * is voltage V1, preamplifier activation signal PAE is activated.

Thereafter, when the voltage level of peripheral power supply voltage Vccp decreases, IO line precharge instructing signal IOE
The H level of Q becomes lower than a predetermined voltage level. When the voltage level of peripheral power supply voltage Vccp is lower than the voltages on internal data bus lines I / O and I / O *, the voltage level of precharge instructing signal IOEQ also changes to the level of internal data bus line I / O. And the voltage level on I / O * is lower than that on precharge transistor 1
07a and 107b are turned off. This is because the nodes receiving peripheral power supply voltage Vccp are connected to precharge n-channel MOS transistors 107a and 107b.
And the gate and source voltages of these precharging n-channel MOS transistors 107a and 107b are equal. Therefore,
In this state, internal data bus lines I / O and I
/ O * cannot be completely precharged to the same voltage level, and holds a voltage level corresponding to the memory cell data read in the previous cycle, and in that state, it becomes a floating state.

In this state, when the next memory cell selection operation is performed, a new selection is made from the voltage levels of internal data bus lines I / O and I / O * corresponding to the previous memory cell data. Voltage levels of internal data bus lines I / O and I / O * change according to data of the memory cells. When data opposite to that of the previous cycle is read, the voltage levels of internal data bus lines I / O and I / O * change in the opposite direction, so that the voltage level corresponding to the data of the newly selected memory cell is obtained. , It takes a long time for internal data bus lines I / O and I / O * to arrive. On the other hand, preamplifier activation signal PAE is activated at a predetermined timing. Therefore, when preamplifier activation signal PAE is activated, internal data bus lines I / O and I / O
If the voltage difference on O * is the voltage V2, the preamplifier 10
No. 8 cannot accurately amplify the memory cell data and cannot correctly read the memory cell data.

Column select signal generating circuit 104 drives a column select signal corresponding to a selected column to the level of peripheral power supply voltage Vccp using peripheral power supply voltage Vccp as an operation power supply voltage. The current driving capability of sense amplifier 102 is relatively small. Therefore, this peripheral power supply voltage V
When the voltage level of ccp is higher than sense power supply voltage Vccs, the conductance of the column select gate connected to the bit line at the ground voltage level sharply increases, while the column connected to the bit line at the level of sense power supply voltage Vccs is increased. The conductance of the select gate does not increase very rapidly (because the gate-source voltage is not so high). Therefore, an internal data bus line having a large load capacitance is suddenly connected to the sense node in sense amplifier 102, and the data stored in sense amplifier 102 may be reversed regardless of the precharge voltage level of the internal data bus line. Conceivable. In this case, accurate reading of data from the memory cell cannot be performed, and the memory cell data is destroyed.

Further, in the stress acceleration mode in the conventional final test before shipping, the peripheral power supply voltage Vccp and the sense power supply voltage Vccs are both changed in voltage level in accordance with the external power supply voltage. Therefore, the influence of the voltage level of the column selection signal on the data held in the sense amplifier of the selected column cannot be measured, and there has been a problem that accurate reading of data cannot be sufficiently ensured.

An object of the present invention is to provide a semiconductor memory device capable of accurately reading data without being affected by a peripheral power supply voltage.

Another object of the present invention is to provide a semiconductor memory device capable of reading data without destruction of selected memory cell data.

Yet another object of the present invention is to provide a semiconductor memory device capable of accurately precharging an internal data bus to a predetermined voltage level without being affected by a peripheral power supply voltage.

Still another object of the present invention is to provide a semiconductor memory device that can accurately and stably hold data in a sense amplifier.

[0024]

According to a first aspect of the present invention, a semiconductor memory device is provided corresponding to a plurality of memory cells arranged in a matrix and a column of the memory cells, and corresponds to a memory cell corresponding to an activated state. A plurality of sense amplifiers for driving a column to a first power supply voltage or ground voltage level in accordance with data of a selected memory cell; an internal data bus for transmitting / receiving data to / from the selected memory cell; A precharge circuit for precharging to a power supply voltage level of 1 and a peripheral circuit which operates by receiving a second power supply voltage equal to or higher than the first power supply voltage as an operation power supply and performs at least an operation related to memory cell selection Prepare.

In a semiconductor memory device according to a second aspect, the peripheral circuit of the first aspect operates by receiving the second power supply voltage as an operation power supply voltage, decodes a given internal column address signal, and specifies an address. A column decode circuit for generating a column designating signal for designating the specified column, and a third column for the addressed column in accordance with the column designating signal from the column decode circuit.
And a column selection drive circuit for generating a column selection signal at the power supply voltage level of The selected column is coupled to an internal data bus via a column selection gate according to the column selection signal.

According to a third aspect of the present invention, in the semiconductor memory device, the peripheral circuit of the first aspect operates by receiving the second power supply voltage as an operation power supply voltage, and amplifies data on the internal data bus line when activated. Including circuits.

In a semiconductor memory device according to a fourth aspect, the third power supply voltage of the second aspect is at the same voltage level as the first power supply voltage.

According to a fifth aspect of the present invention, the third power supply voltage of the second aspect is at a voltage level between the first and second power supply voltages.

In a semiconductor memory device according to a sixth aspect, the second power supply voltage of the first or second aspect is at the same voltage level as an externally applied power supply voltage.

According to a seventh aspect of the present invention, the second power supply voltage and the third power supply voltage of the second aspect have the same voltage level.

According to an eighth aspect of the present invention, there is provided a semiconductor memory device according to the second aspect, further comprising a first power supply line transmitting an external power supply voltage, and a first power supply receiving the voltage of the first power supply line. A first internal voltage generating circuit for generating a voltage and applying the generated voltage to the sense amplifier and the precharge circuit; and a first internal voltage generating circuit coupled to the first power supply line, and a voltage higher than the first power supply voltage based on the voltage on the first power supply line. A second internal voltage generating means for generating two power supply voltages, and a means for supplying one of the output voltages of the first power supply line and the second internal voltage generating circuit to the column decode circuit.

According to a ninth aspect of the present invention, the selection means of the eighth aspect also supplies the selected voltage to the column selection drive circuit.

A semiconductor memory device according to a tenth aspect of the present invention is the semiconductor memory device according to the eighth aspect, further comprising a third power supply voltage generated from the external power supply voltage and coupled to the first power supply line. And a third voltage generating circuit for applying the voltage to the third voltage generator. The third power supply voltage generation circuit is provided separately from the first internal voltage generation circuit.

The semiconductor memory device according to claim 11 is the device according to claim 2, further comprising means for setting the power supply voltage of the column selection drive circuit to the external power supply voltage level in response to the test mode instruction.

The precharge voltage of the internal data bus line is
By setting the sense power supply voltage level, the internal data bus line can be accurately precharged to a predetermined voltage level without being affected by the peripheral power supply voltage.

In the test mode, by setting the peripheral power supply voltage to the external power supply voltage level, it is possible to test the dependency of the stability of the data held by the sense amplifier on the peripheral power supply voltage.

Further, by setting the voltage level of the column selection signal to a voltage level lower than the sense power supply voltage level or the peripheral power supply voltage, it is possible to prevent data inversion of the sense amplifier from occurring.

[0038]

[First Embodiment] FIG. 1 schematically shows a whole structure of a semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, the semiconductor memory device includes a memory cell array 1 having a plurality of memory cells arranged in a matrix, an address input buffer 2 for receiving an external address signal AD and generating an internal address signal, and an address input buffer. A row selection circuit 3 for decoding an internal row address signal from memory cell array 2 to drive an addressed row of memory cell array 1 to a selected state, and provided for each column of memory cell array 1 for activation. , A sense amplifier band 4 including a plurality of sense amplifiers for detecting and amplifying memory cell data on a column and an internal column address signal from address input buffer 2 are decoded to specify an addressed column of memory cell array 1. A column decode circuit 5 for generating a column designating signal, and a column designating signal from the column decode circuit 5 A column selection line drive circuit 6 for driving a column selection line for selecting a column of the memory cell array 1 to a selected state, and a column selection line drive circuit 6 provided corresponding to each column of the memory cell array 1. According to the signal, the selected column is connected to the internal data bus 8
Column select gate group 7 including a plurality of column select gates coupled to
And a write / read circuit 10 for writing / reading internal data to / from internal data bus 8, and an input / output circuit 11 for inputting / outputting external data DQ.

Internal data bus 8 is provided with an IO line precharge circuit 9 for precharging internal data bus 8 to a predetermined voltage level when activated.

The semiconductor memory device further includes a control circuit 12 for generating an internal control signal according to external signal EXS.
And an internal power supply circuit 13 for receiving an external power supply voltage extVcc via power supply line 20 to generate internal power supply voltage Vccsa, and an internal power supply circuit 14 for generating internal power supply voltage Vccpa from the power supply voltage on power supply line 20. Including. An external power supply voltage extVcc is transmitted to the inside of the circuit via power supply line 20 as external power supply voltage Vex.

Internal power supply voltage Vc from internal power supply circuit 13
csa is applied to sense amplifier band 4 and IO line precharge circuit 9. Internal power supply voltage Vccpa from internal power supply circuit 14 is applied to column select line drive circuit 6. When the external power supply voltage Vex is applied to the peripheral circuits, that is, the address input buffer 2, the row selection circuit 3, the column decode circuit 5,
Write / read circuit 10, input / output circuit 11, and control circuit 1
2 as an operating power supply voltage.

By applying internal power supply voltage Vccsa having the same voltage level as power supply voltage Vccsa applied to sense amplifier band 4 to IO line precharge circuit 9, internal data bus 8 is provided with a variation in power supply voltage applied to the peripheral circuits. , And is stably precharged to a predetermined voltage level. By applying internal power supply voltage Vccpa different from external power supply voltage Vex applied to column decode circuit 5 to column select line drive circuit 6, it is possible to prevent the sense amplifier data from fluctuating when a column is selected (when the column select gate is conductive). Can be prevented. In addition, sense amplifier band 4
Internal power supply circuit 13 for generating internal power supply voltage Vccsa and internal power supply circuit 14 for generating internal power supply voltage Vccpa applied to column select line drive circuit 6 are separately provided, so that internal power supply voltage Vcc during sense operation is provided.
Even if sa is consumed and its voltage level decreases, the column selecting operation can be performed accurately and at high speed.

FIG. 2 is a diagram showing an example of the configuration of internal power supply circuits 13 and 14 shown in FIG. 2, internal power supply circuit 13 for generating internal power supply voltage Vccsa and internal power supply circuit 14 for generating internal power supply voltage Vccpa
Since both have the same configuration, FIG. 2 representatively shows the configuration of one internal power supply circuit. In FIG.
The internal power supply circuit is connected to the internal power supply voltage Vc on the internal power supply line 21.
c (Vccsa, Vccpa) and a current drive transistor 23 composed of a comparator 22 for comparing the reference voltage Vref and a p-channel MOS transistor for supplying a current from the power supply line 20 to the internal power supply line 21 in accordance with an output signal of the comparator 22 including. Internal power supply voltage Vcc is equal to reference voltage Vr
When it is higher than ef, the output signal of the comparator 22 becomes H level, and the current drive transistor 23 is turned off. On the other hand, the internal power supply voltage Vcc is equal to the reference voltage Vref.
If the voltage is lower than Vcc, the output signal of the comparator 22 drops to a low level corresponding to the difference between the voltages Vcc and Vref, the conductance of the current drive transistor 23 increases, and the current flows from the power supply line 20 to the internal power supply line 21. To increase the voltage level of internal power supply voltage Vcc. Therefore, in the configuration of the internal power supply circuit shown in FIG. 2, internal power supply voltage Vcc is equal to the voltage level of reference voltage Vref. The configuration of the internal power supply circuit shown in FIG. 2 is merely an example, and a configuration in which internal power supply voltage Vcc is level-shifted and reference voltage Vref is compared with the level-shifted internal power supply voltage may be used. Good.

FIG. 3 is a diagram showing a configuration related to a 1-bit data read section of the semiconductor memory device shown in FIG. FIG. 3 shows one bit line pair.

Sense amplifier group 7 includes a sense amplifier circuit 7a provided for bit lines BL and / BL. Sense amplifier circuit 7a is activated when sense power supply voltage Vccsa is applied on sense drive line 101p, and is cross-coupled to drive the higher potential bit line of bit lines BL and / BL to the level of sense power supply voltage Vccsa. Cross-coupled p-channel MOS transistor and a cross-coupled n-channel which is activated when a ground voltage is transmitted onto sense drive line 101n, and discharges a low potential bit line of bit lines BL and / BL to the ground voltage level. MOS
Including transistors. Sense drive line 101p is provided with a p-channel MOS transistor 103b which conducts when sense amplifier activation signal / SEN is activated and transmits sense power supply voltage Vccsa to sense drive line 101p.
The sense drive line 101n includes a sense amplifier activation signal S
N channel MOS transistor 1 which conducts in response to activation of EN and transmits the ground voltage to sense drive line 101n
03a is provided. Since sense amplifier circuit 7a uses sense power supply voltage Vccsa as one operation power supply voltage, the amplitude of bit lines BL and / BL is Vccsa.

Column decode circuit 5 includes a NAND type decode circuit 5a for decoding a given address signal to generate a column designation signal. This NAND type decoding circuit 5
a operates using the external power supply voltage Vex as one operation power supply voltage.

The column selection line drive circuit 6 uses the NAND
Provided corresponding to type decode circuit 5a, operates using internal power supply voltage Vccsp as one operation power supply voltage,
Inverts the output signal of pattern decode circuit 5a to column select line CS.
CMOS inverter circuit 6 transmitting a column selection signal on L
a.

Column select gate group 7 is provided for bit lines BL and / BL, is rendered conductive when a column select signal on column select line CSL is activated, and connects bit lines BL and / BL to internal data bus line I. Includes column select gate 7a connected to / O and I / O *. Column select gate 7a includes a transfer gate whose gate is connected to column select line CSL.

IO line precharge circuit 9 includes a precharge circuit 9a provided for internal data bus lines I / O and I / O *. This precharge circuit 9a
Conducting in response to activation of precharge instructing signal / IOEQ, causing internal power supply voltage Vccsa to be applied to internal data bus line I /
P-channel MOS for transmitting to O and I / O * respectively
Includes transistors PQa and PQb. p channel M
By using the OS transistor as an internal data bus line precharge element, even if the internal power supply voltage Vc
Even if csa drops, p-channel MOS transistors PQa and PQb for precharging maintain the on state, and accurately internal data bus lines I / O and I / O *
Can be precharged to the internal power supply voltage Vccsa level.

Write / read circuit 10 includes a preamplifier 10a for amplifying complementary data on internal data bus lines I / O and I / O *. Preamplifier 10a includes n-channel MOS transistors NQa and NQb forming a comparison stage for comparing internal data bus lines I / O and I / O *,
A p-channel MOS transistor P forming a current mirror stage for supplying a current from power supply line 20 to these comparison stages
Qc and PQd, and an n-channel MOS transistor NQc which conducts in response to activation of preamplifier activation signal PAE and forms a current path between MOS transistors NQa and NQb and a ground node. The external power supply voltage Ve is supplied to the preamplifier 10a as an operation power supply voltage.
x is provided to guarantee a high-speed amplification operation and realize high-speed data reading.

Internal data line precharge instruction signal / IO
The EQ is generated from a drive circuit 12a included in the control circuit 12 shown in FIG. Drive circuit 12a operates using external power supply voltage Vex as one operation power supply voltage, and activates an internal column selection operation.
S, internal data line precharge instructing signal / IOE
Generate Q. Column select operation instructing signal φCAS is generated, for example, in accordance with column address strobe signal / CAS in a standard DRAM.

Preamplifier activation signal PAE is generated from driver 12b included in control circuit 12 shown in FIG. Driver 12b operates using external power supply voltage Vex as one operation power supply voltage, and generates control signal φATD generated based on a signal for detecting a change in a column address signal.
To generate a preamplifier activation signal PAE. Next, the operation of the configuration shown in FIG. 3 will be described with reference to a signal waveform diagram shown in FIG.

Internal data bus lines I / O and I / O *
Are precharged to the voltage level of internal power supply voltage Vccsa by IO line precharge circuit 9a. In this case, p-channel MOS transistors PQa and PQa
Since internal data bus lines I / O and I / O * are precharged using Qb, the voltage of internal power supply voltage Vccsa is not affected by the threshold voltages of MOS transistors PQa and PQb. Internal data bus lines I / O and I / O * are precharged to the level.

The memory cycle starts and the word line WL
(Not shown), the bit lines BL and / B
The memory cell data is read to L. In FIG.
A signal waveform when H level data is read is shown as an example.

After this word line is driven to the selected state,
At a predetermined timing, sense amplifier activation signals SEN and / SEN are driven to an active state, and sense drive line 1
Internal power supply voltage Vccsa and ground voltage are transmitted to 01p and 101n, respectively, and sense amplifier circuit 4a is activated. The voltage level of bit lines BL and / BL is set at internal power supply voltage Vccs according to the memory cell data.
After being driven to a and the ground voltage level by the sense amplifier circuit 4a, the column selection operation starts.

In this column selecting operation, first, internal data line precharge instructing signal / IOEQ rises from L level to the voltage level of external power supply voltage Vex, and p channel MOS transistor PQa included in precharge circuit 9a. And PQb are turned off. Internal data bus lines I / O and I / O * are connected to internal power supply voltage Vcc.
At the voltage level of sa, a floating state is set.

Next, the column decoding circuit 5 performs a decoding operation, and the output signal of the NAND type decoding circuit 5a becomes L
Level, and the output signal of the column selection drive circuit 6a becomes
Internal power supply voltage Vccsp rises to the voltage level, column select gate 7a conducts, and bit lines BL and / BL are coupled to internal data bus lines I / O and I / O *. Thereby, the voltages of internal data bus lines I / O and I / O * change according to the voltage levels of bit lines BL and / BL. The voltage level of the internal data bus line from which the H-level data is read out maintains the voltage level of internal power supply voltage Vccsa, and the voltage level of the internal data bus line receiving the L-level data gradually decreases (the driving power of the sense amplifier). Is relatively small). Then, at a predetermined timing, preamplifier activation signal PAE is activated, and the data on internal data bus lines I / O and I / O * are read to generate internal read data RD.

When the reading of the memory cell data is completed, the selected word line WL is driven to a non-selected state, and sense amplifier activation signals SEN and / SEN are also driven to a non-activated state, and bit lines BL and / BL are driven. Are precharged / equalized to an intermediate voltage level by a precharge / equalize circuit (not shown). Column selection line C
The signal on SL is also at L level, column selection gate 7a is turned off, and bit lines BL and / BL are separated from internal data bus lines I / O and I / O *. Then, precharge instruction signal / IOEQ is applied to external power supply voltage V
ex falls to the ground voltage level, p channel MOS transistors PQa and PQb included in precharge circuit 9a are turned on, and internal data bus lines I / O and I / O * are connected to internal power supply voltage Vccs.
Drive to the voltage level a.

FIG. 5 is a diagram showing a voltage change of the internal data bus line when the internal data bus line is precharged. In FIG. 5, when the internal data bus line is precharged, precharge instructing signal / IOEQ is in an active state at the level of ground voltage Vss, and p-channel MOS transistors PQa and PQb are on. Internal data bus line I / O
Has an internal power supply voltage Vc according to the selected memory cell data.
The csa level H level data is transmitted, while the internal data bus line I / O * is held at the voltage Vccsa-Δ according to the L level data.

Now, consider the case where the voltage level of internal power supply voltage Vccsa has decreased. When the voltage of internal power supply voltage Vccsa decreases, the voltage of the power supply node of precharge circuit 9a becomes lower than the voltage charged to the parasitic capacitance on internal data bus line I / O, so that p-channel MOS transistor PQa A node connected to the power supply serves as a source, and a current flows from the internal data bus line I / O to the power supply node. The internal data bus line I / O has an internal power supply voltage Vc
It is precharged to the voltage level of csa. On the other hand, internal data bus line I / O * has its voltage Vccsa
The path through which the current flows differs depending on the difference between -Δ and the reduced voltage level of internal power supply voltage Vccsa. When the reduced voltage of internal power supply voltage Vccsa of the power supply node is higher than voltage Vccsa-Δ of internal data bus line I / O *, the internal data bus line I / O is supplied from the power supply node via p-channel MOS transistor PQb. A current flows through O *,
Internal data bus line I / O * is connected to internal power supply voltage Vccsa
Is precharged to a voltage level of On the other hand, when the reduced voltage level of internal power supply voltage Vccsa is lower than voltage Vccsa-Δ of internal data bus line I / O *, current flows from internal data bus line I / O * to the power supply node, The voltage level of internal data bus line I / O * lowers and becomes equal to the voltage level of internal power supply voltage Vccsa. Therefore, in any case, even if the voltage level of internal power supply voltage Vccsa decreases due to a sensing operation or the like, both internal data bus lines I / O and I / O * are precharged to the voltage level of internal power supply voltage Vccsa. And maintain the same voltage level. Thus, internal data bus lines I / O and I / O * can be accurately precharged to the same voltage level without being affected by a decrease in internal power supply voltage Vccsa.

FIG. 6 is a diagram showing a voltage change of the internal data bus line at the time of data writing / reading. In FIG. 6, at the time of data writing, internal data bus line I / O
And I / O * are driven from precharged internal power supply voltage Vccsa to the ground voltage level. H
The internal data bus line receiving the level data may be at either the internal power supply voltage Vccsa or the external power supply voltage Vex. When writing L level data,
The amplitude of the internal data bus line receiving the L level data is larger than the signal amplitude of the internal data bus line receiving the H level data. This is because complementary internal data is generated by a write driver (not shown) and transmitted to internal data bus lines I / O and I / O *. After the completion of writing, the internal data bus line is precharged to the level of internal power supply voltage Vccsa in response to activation of precharge instruction signal / IOEQ. Therefore, the maximum amplitude at the time of data writing of this internal data bus line is Vccsa, and the
The amplitude can be smaller than cp-Vth, and a high-speed precharge operation can be performed. Also, at the time of writing, the amplitude is set to the level of internal power supply voltage Vccsa, so that L-level data can be transmitted at a higher speed than before (because the amplitude is smaller), and high-speed writing is realized. . Thus, not only the writing time but also the precharge time can be shortened, and the transition from writing to reading can be performed at a high speed.

As shown in FIG. 3, the column selection signal is
Voltage level of voltage Vccsp and external power supply voltage Ve
The voltage level is lower than x. As a result, the conductance of the column select gate 7a is prevented from sharply decreasing, the sense amplifier circuit 4a can prevent the held data from being disturbed, and the sense amplifier circuit 4a is Data can be stored in the In the first embodiment, external power supply voltage Vex is, for example, 2.5 V ± 0.25 V, internal power supply voltage Vccsa is 2.0 V, and internal power supply voltage Vccsp is about 2.2 V. is there. Internal power supply voltage Vc
By setting csp to be higher than internal power supply voltage Vccsa, column select gate 7a is sufficiently turned on, so that bit lines BL and / BL and internal data bus line I / O can be driven at high speed.
And data transfer to / from I / O *.

Internal power supply voltage Vccsp and internal power supply voltage V
ccsa may be the same voltage level. The transfer gate (included in column select gate 7a) provided for bit line BL driven to the H level has the same internal power supply voltage Vcc as the voltage level of the internal data bus line.
Since it is at the sa level, the off state is maintained, and no charge transfer occurs. Therefore, there is no need to consider the problem of the threshold voltage. It suffices to simply transfer charges between the bit line driven to L level and the internal data bus line and lower the voltage level of the internal data bus line. At the time of data writing, a threshold voltage loss occurs in the column selection gate. However, since the sense amplifier circuit 4a has a smaller driving force than the write drive circuit and can sufficiently reverse the latch state, a particular problem occurs. Absent. Therefore, internal power supply voltage Vccsp may have a voltage level equal to or higher than internal power supply voltage Vccsa.

As described above, according to the first embodiment of the present invention, since the precharge voltage of the internal data bus line is set to the same voltage level as the power supply voltage of the sense amplifier, internal power supply voltage fluctuations Even if this occurs, the internal data bus lines can be accurately precharged to the same voltage level.

The precharge voltage of the internal data bus line is the lowest voltage level of the power supply voltage generated inside the semiconductor memory device, and the amplitude at the time of data writing can be minimized. Data writing and precharge / equalization after completion of writing can be performed at high speed.

Further, since the voltage level of the active state of the column selection line is lower than the external power supply voltage and higher than the sense power supply voltage, the conductance of the column selection gate rapidly changes, and a large load is rapidly connected to the sense amplifier. As a result, the data held in the sense amplifier circuit can be prevented from being destroyed.

[Second Embodiment] FIG. 7 schematically shows an entire configuration of a semiconductor memory device according to a second embodiment of the present invention. In FIG. 7, external power supply voltage extV
cc via power supply line 20 to receive internal power supply voltage Vccs.
a, and receives an external power supply voltage extVcc on power supply line 20 to receive peripheral power supply voltage Vcc.
An internal power supply circuit 30 for generating p is provided. Peripheral power supply voltage Vccp from internal power supply circuit 30 is supplied to peripheral circuits, that is, address input buffer 2, row selection circuit 3, column selection line drive circuit 6, column decode circuit 5, write / read circuit 10, and input / output circuit 11. Given. Sense power supply voltage Vccsa from internal power supply circuit 13 is applied to sense amplifier band 4 and IO line precharge circuit 9. Therefore, the configuration shown in FIG. 7 differs from the configuration of the first embodiment in that peripheral power supply voltage Vc is used instead of external power supply voltage Vex.
cp is used, and peripheral power supply voltage Vccp is also applied to column select line drive circuit 6. Other configurations are the same as those shown in FIG. 1. Corresponding portions have the same reference characters allotted, and detailed description thereof will not be repeated.

In the structure shown in FIG. 7, the precharge voltage of internal data bus 8 is at the same voltage level as sense power supply voltage Vccsa applied to sense amplifier band 4. Therefore, even when sense power supply voltage Vccsa varies, internal data bus line 8 (internal data bus lines I / O and I / O
*) Can be precharged to a predetermined voltage level.

FIG. 8 is a diagram showing in more detail the structure of the main part of the semiconductor memory device shown in FIG. In the configuration shown in FIG. 8, column select line drive circuit 6a supplies peripheral power supply voltage Vccp to another peripheral circuit, ie, preamplifier 10a.
a, drive circuits 12a and 12b, and NAND type decode circuit 5a. The other configuration is the same as the configuration shown in FIG.

As is apparent from the configuration shown in FIG. 8, p channel MOS transistors PQa and PQb included in IO line precharge circuit 9a receive sense power supply voltage Vc when precharge instructing signal / IOEQ is activated.
csa is transmitted to internal data bus lines I / O and I / O *. Bit lines BL and / BL are driven to a sense power supply voltage Vccsa and a ground voltage level by sense amplifier circuit 4a. Therefore, even if the voltage level of sense power supply voltage Vccsa decreases, precharge p-channel MOS transistors PQa and PQb
, The internal data bus lines I / O and I / O * are surely precharged to the same voltage level in order to maintain the ON state.

Since the amplitudes of internal data bus lines I / O and I / O * are reduced, as in the first embodiment,
High-speed data writing and high-speed precharge can be realized.

In the second embodiment, column select line drive circuit 6 for generating a column select signal receives peripheral power supply voltage Vccp as one operation power supply voltage. However, also in the second embodiment, a configuration in which another internal power supply circuit is provided and power supply voltage Vccpa for driving the column selection line is separately generated may be used. In this case, data destruction of the sense amplifier at the time of column selection can be reliably prevented.

When external power supply voltage extVcc is, for example, 3.3 V, the internal power supply voltage is, for example, 2.5 V
By generating the peripheral power supply voltage Vccp of V, low power consumption and high-speed operation are ensured.
By generating an even lower voltage of 2.0 V as ccsa, low power consumption and breakage of the gate insulating film and the capacitor insulating film of the memory cell can be prevented.

As described above, according to the second embodiment of the present invention, the precharge voltage of the internal data bus line is set to the same voltage level as the sense power supply voltage. Thus, the internal data bus lines can be reliably precharged to the same voltage level, and accurate internal data reading, high-speed writing and precharging can be realized.

[Third Embodiment] FIG. 9 schematically shows a whole structure of a semiconductor memory device according to a third embodiment of the present invention. In the semiconductor memory device shown in FIG. 9, three internal power supply circuits 13 coupled to power supply line 20;
14 and 30 are provided. From the external power supply voltage extVcc on the power supply line 20, the internal power supply circuit 13
V sense power supply voltage Vccsa is generated and applied to sense amplifier band 4 and IO line precharge circuit 9. The internal power supply circuit 14 is connected to an external power supply voltage ex on the power supply line 20.
An internal power supply voltage Vccpa of about 2.2 V (may be 2.0 V) is generated from tVcc, and column select line drive circuit 6
Give to. The internal power supply circuit 30 converts the external power supply voltage extVcc on the power supply line 20 to an internal power supply voltage Vc of about 2.5V.
The cpa is generated and provided to other peripheral circuits, that is, the address input buffer 2, the row selection circuit 3, the column decode circuit 5, the write / read circuit 10, the input / output circuit 11, and the control circuit 12.

In the configuration shown in FIG. 9, low power consumption and high speed operation are realized by operating the peripheral circuits with internal power supply voltage Vccp from internal power supply circuit 30. Also, the internal power supply voltage Vc from the internal power supply circuit 14 is used.
By applying cpa to column select line drive circuit 6,
The amplitude of the column selection line is reduced, and high-speed column selection, low power consumption, and prevention of destruction of data held in the sense amplifier circuit during column selection can be realized. Further, by supplying sense power supply voltage Vccsa from internal power supply circuit 13 to sense amplifier band 4 and IO line precharge circuit 9, low power consumption due to reduction of bit line amplitude, reduction of gate insulating film of memory cell and capacitor insulating film are achieved. Prevention of destruction and accurate precharge of internal data bus lines to the same potential can be realized.

The other structure is the same as that of the second embodiment, and the same portions are denoted by the same reference numerals and detailed description thereof will not be repeated.

In the first to third embodiments, the input / output circuit 11 is supplied with the peripheral power supply voltage Vccp or the external power supply voltage Vex. In this input / output circuit 11, a high voltage Vpp may be separately applied to its input stage (to compensate for the threshold voltage loss of the output stage).

As described above, according to the third embodiment of the present invention, three types of internal power supply voltages are generated, the lowest internal power supply voltage is applied to the sense amplifier band and the internal data bus line precharge circuit. Since the internal power supply voltage is low to drive the column select lines and the remaining highest internal power supply voltage is used to drive the peripheral circuits, it operates at high speed with low power consumption and accurately connects the internal data bus lines. A semiconductor memory device that can be precharged and that can prevent the data held in the sense amplifier from being destroyed when a column is selected can be obtained.

[Fourth Embodiment] FIG. 10 is a diagram schematically showing a configuration of a main portion of a semiconductor memory device according to a fourth embodiment of the present invention. FIG. 10 shows a configuration of a portion for generating an internal power supply voltage. In FIG. 10, an internal power supply circuit 13 for generating a sense power supply voltage Vccsa from an external power supply voltage extVcc on a power supply line 20 is provided.
An internal power supply circuit for generating an internal power supply voltage from the external power supply voltage extVcc on the power supply line 20;
An internal power supply circuit 30 for generating ccp, an external power supply voltage extVcc on the power supply line 20, an output voltage of the internal power supply circuit 14, and one of the internal power supply voltages from the internal power supply circuit 30 are selected and supplied to the column selection line drive circuit. Given peripheral power supply voltage V
an optional voltage selector 35 for generating ccp and an optional voltage selector for selecting one of the output voltage of the internal power supply circuit 30 and the external power supply voltage extVcc (Vex) on the power supply line 20 to generate the peripheral power supply voltage Vccp for the peripheral circuit 36 are provided.

Optional voltage selectors 35 and 36
Are each formed of, for example, a mask wiring, and the selection path is determined by the mask wiring according to the voltage level of external power supply voltage extVcc. For example, when external power supply voltage extVcc is 3.3 V, 2.0 V sense power supply voltage Vccsa is generated by internal power supply circuit 13 and applied to a sense amplifier band and an IO line precharge circuit. The voltage is generated by the internal power supply circuit 30 and applied to the column selection line drive circuit and the peripheral circuits in common. In this case, the internal power supply voltage of about 2.2 V from the internal power supply circuit 14 can be selected for the column select line drive circuit and applied to the column select line drive circuit.

When the external power supply voltage extVcc is 2.5
In the case of V, a sense power supply voltage Vccsa of about 2.0 V is generated by the internal power supply circuit 13 and the external power supply voltage ext
Vcc can be selected as an internal power supply voltage applied to the column select line drive circuit and peripheral circuits. Also in this case, the external power supply voltage (about 2.5 V)
And a voltage of about 2.2 V from the internal power supply circuit 14 can be applied to the column selection line drive circuit (column selection driver).

Therefore, by providing optional voltage selectors 35 and 36, a plurality of internal power supply arrangements can be realized from one chip, and it is necessary to change the layout of the internal circuit according to the type of power supply arrangement. In addition, the design becomes easy, the manufacturing process can be unified, the product cost is reduced, and the product management is also easy.

When the output voltages of internal power supply circuits 14 and / or 30 are not selected by option voltage selectors 35 and 36, the connection between internal power supply circuits 14 and 30 and power supply line 20 is cut off, and internal power supply Circuits 14 and / or 30 may be disabled. Alternatively, the internal power supply circuit 14 and / or
Alternatively, 30 may be set to be inactive at all times (this is realized by a bonding option or mask wiring). When mask wiring is not used as option voltage selectors 35 and 36, C
The MOS transfer gate may be used as a selection gate for voltage selection (in this case, the control signal needs to be at the highest external power supply voltage level).

As described above, according to the fourth embodiment of the present invention, a plurality of internal power supply circuits are prepared in advance, and the internal power supply voltage is selected according to the power supply arrangement actually used internally. Therefore, one chip can cope with a plurality of power supply arrangements, the product cost can be reduced, and the manufacturing process and management can be simplified.

[Fifth Embodiment] FIG. 11 shows a structure of a main portion of a semiconductor memory device according to a fifth embodiment of the present invention. In FIG. 11, external power supply voltage extVcc
, Two internal power supply voltages Vccsa and Vccp are generated. Sense power supply voltage Vccsa is applied to a sense amplifier band and an internal data bus line (IO line) precharge circuit, and peripheral power supply voltage Vccp is commonly applied to peripheral circuits including a column select line drive circuit.

In FIG. 11, internal power supply circuit 13 includes power supply voltage Vccsa on internal power supply line 13a and reference voltage Vr
efs, and a p-channel MOS transistor 13c for supplying a current from the power supply line 20 to the internal power supply line 13a in accordance with an output signal of the comparator 13b.
Internal power supply circuit 13 for generating sense power supply voltage Vccsa
Generates an internal power supply voltage Vccsa at a constant voltage level independent of external power supply voltage extVcc (or Vex) (when the external power supply voltage is equal to or higher than the constant voltage level).

Internal power supply circuit 30 compares peripheral power supply voltage Vccp on internal power supply line 30a with reference voltage Vrefp, and supplies a current from power supply line 20 to internal power supply line 30a in accordance with an output signal of comparator 30b. When the test mode instruction signal ZTEST is activated (L level), the power supply line 2
0 and an internal power supply line 30a are electrically connected to each other by a p-channel MOS transistor 30d;
A p-channel MOS transistor 30e which conducts when TEST is activated and sets the output node of comparator 30b to the level of external power supply voltage extVcc is included.

In the configuration of internal power supply circuit 30,
When test mode instruction signal ZTEST is activated, MOS transistors 30e and 30d are turned on, and peripheral power supply voltage Vccp on internal power supply line 30a attains the level of external power supply voltage extVcc. At this time, the gate voltage of p channel MOS transistor 30c attains the level of external power supply voltage extVcc, and is turned off.
Comparator 30b outputs an external power supply voltage extV
Fixed to cc level. At this time, a configuration may be used in which comparator 30b is driven to an inactive state when test mode instruction signal ZTEST is activated (this test mode instruction signal ZTES is connected in series with the current source transistor).
This configuration is realized by connecting a MOS transistor which is turned off when T is activated.)

In FIG. 11, in the test mode, sense power supply voltage Vccsa is set to a constant voltage level (reference voltage Vrefs level), and peripheral power supply voltage Vcsa is set.
By changing cp in accordance with the external power supply voltage extVcc, not only a voltage stress acceleration test of peripheral circuits but also various timing margins and a sense amplifier stability test (address noise test) can be performed as described below.

In the normal operation mode, test mode instructing signal ZTEST is at the H level of an inactive state, and internal power supply circuit 30 generates peripheral power supply voltage Vccp according to reference voltage Vrefp, and applies the same to peripheral circuits. Internal power supply circuit 13 also generates sense power supply voltage Vccsa according to reference voltage Vrefs, and applies the same to sense amplifier band and IO line precharge circuit.

In the test mode, test mode instruction signal ZTEST is driven to an active L level. Thereby, peripheral power supply voltage Vccp output from internal power supply circuit 30 becomes equal to external power supply voltage extVcc. On the other hand, sense power supply voltage Vccsa has a constant voltage level because internal power supply circuit 13 operates independently of test mode instruction signal ZTEST.

Therefore, as shown in FIG. 12, in the test mode, by changing the voltage level of external power supply voltage extVcc, a difference occurs between the peripheral power supply voltage Vccp and the sense power supply voltage Vccsa.
Peripheral power supply voltage Vccp is applied to a peripheral circuit, and performs a memory cell selecting operation and a data write / read operation. Therefore, by changing the voltage level of peripheral power supply voltage Vccp, the operation speed of the peripheral circuit can be changed, and the operation speed of the circuit related to the memory cell selection operation can be changed. On the other hand, sense power supply voltage Vccsa is at a constant voltage level,
The sense amplifier operates at a constant speed.

Therefore, as shown in FIG. 13, word line WL is driven to the selected state, and bit lines BL and / or
The time elapsed from the read of the memory cell data to BL to the activation of the sense amplifier is determined by the external power supply voltage extV
By changing the peripheral power supply voltage Vccp according to cc, it can be changed. Thus, it is possible to detect a sense timing margin as to whether or not the sense amplifier circuit can perform an accurate data sensing operation. For example, when the sense timing margin is small, when the word line selection timing is delayed, since a sufficient voltage difference is not generated between bit lines BL and / BL, an accurate sensing operation cannot be performed.

The peripheral power supply voltage Vccp is also supplied to a column selection line drive circuit that drives a column selection line.
Therefore, the amplitude of the column select signal on column select line CSL is also controlled by external power supply voltage ext via peripheral power supply voltage Vccp.
It can be changed according to Vcc. This allows
It is possible to test the stability of the data held in the sense amplifier circuit when selecting a column. In a test called an address noise test, data of which logic is known in advance is written into a memory cell, then a sense operation is performed, latched by a sense amplifier circuit, and then a column select operation is performed to read out the memory cell data. It is determined whether the logic of the memory cell data is the same as the logic of the written data. The stability of the data holding characteristics of the sense amplifier circuit can be tested based on the determination result of the logic match / mismatch of the write and read data.

In the fifth embodiment, peripheral power supply voltage Vccp is commonly applied to both the peripheral circuit and the column select line drive circuit. However, when a power supply voltage (Vccpa) different from that of the remaining peripheral circuits is applied to column select line drive circuit, power supply voltage applied to the column select line drive circuit in accordance with activation of test mode instruction signal ZTEST (Vccpa) may be configured to change according to external power supply voltage extVcc. The configuration in this case is easily realized simply by making the configuration of the internal power supply circuit for generating the power supply voltage (Vccpa) applied to the column selection line drive circuit the same as that of internal power supply circuit 30 shown in FIG. You. Only the power supply voltage of the column selection line drive circuit may be changed during this test mode.

As described above, according to the fifth embodiment of the present invention, the internal power supply voltage level applied to the peripheral circuit is set to the same voltage level as the external power supply voltage level in accordance with the test mode instruction signal, and sense power supply voltage is applied. Since the voltage level is constant, it is possible to easily test the sense timing margin and the stability of data holding of the sense amplifier circuit.

[Other Application Examples] If the semiconductor memory device is a semiconductor memory device that generates an internal power supply voltage and has a sense amplifier circuit, it is synchronized with a standard DRAM (Dynamic Random Access Memory) and a clock signal. The present invention is applicable to any of the synchronous dynamic random access memories that operate in the following manner.

The specific values of the internal power supply voltage and the external power supply voltage are arbitrary, and may be appropriately determined according to the power supply voltage in a system actually used.

The test mode instruction signal in the fifth embodiment is generated simply by a combination of a plurality of external control signals. This test mode is used to test the stability of data held by the sense amplifier when the peripheral power supply voltage is accelerated, which is called an “address noise” test, in a final test before product shipment. However, this test may be performed in a test step in which AC characteristics such as a sense margin are specified at a wafer level.

[0101]

As described above, according to the present invention, a semiconductor memory device capable of reading data accurately and stably can be realized.

That is, according to the first aspect of the present invention,
Since the internal data bus line is configured to be precharged to the same voltage level as the sense power supply voltage, even when the peripheral power supply voltage and the sense power supply voltage fluctuate, the internal data bus line is accurately precharged to the same voltage level. It can be charged, and stable data reading can be guaranteed.

According to the second aspect of the present invention, the power supply voltage of the circuit for driving the column selection line is set to a voltage level equal to or lower than the power supply voltage of the circuit for driving the column selection line. Thus, it is possible to prevent the sense amplifier from being suddenly connected to the internal data bus line having a large load, thereby preventing the data held by the sense amplifier from being destroyed.

According to the third aspect of the present invention, since the preamplifier for amplifying data on the internal data bus line is driven by the peripheral power supply voltage, data can be read at high speed.

According to the fourth aspect of the present invention, since the column selection signal amplitude is at the same voltage level as the sense power supply voltage, the amplitude of the column selection signal can be reduced, and the sense amplifier circuit at the time of column selection can be reduced. Destruction of retained data can be prevented.

According to the fifth aspect of the present invention, since the column selection signal amplitude is maintained at a voltage level between the power supply voltage of the sense amplifier and the power supply voltage of the column decode circuit, the sense power supply circuit and the peripheral power supply circuit , A column selection signal of a certain level can be stably generated without being affected by the above, and the destruction of data held in the sense amplifier circuit at the time of column selection can be prevented.

According to the invention of claim 6, since the external power supply voltage is applied to the column decode circuit, the column decode operation can be performed at high speed.

According to the seventh aspect of the present invention, since the operating power supply voltages of the column decode circuit and the column select line drive circuit are at the same voltage level, the power supply arrangement is simplified.

According to the eighth aspect of the present invention, the power supply voltage applied to the peripheral circuit is configured to select one of the output voltage of the internal power supply circuit and the external power supply voltage. , The product cost is reduced, and the manufacturing process and management are simplified.

According to the ninth aspect of the present invention, since the selection voltage is also applied to the column selection signal drive circuit, these column-related circuits can be operated at the same power supply voltage. It is possible to prevent the occurrence of timing mismatch due to the voltage difference.

According to the tenth aspect of the present invention, a third internal power supply voltage generating circuit different from the sense power supply voltage is provided, and an output voltage from the third power supply voltage generating circuit is used for driving a column selection line. Since it is used, a column selection signal can be generated stably without being affected by the sense power supply circuit.

According to the eleventh aspect of the present invention, in the test mode, an external power supply voltage is applied to the column selection line drive circuit. On the other hand, since the sense power supply voltage is constant, the sense It is possible to test the margin and the stability of data holding of the sense amplifier circuit during the column selection operation.

[Brief description of the drawings]

FIG. 1 schematically shows an entire configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a configuration of an internal power supply circuit illustrated in FIG. 1;

FIG. 3 is a diagram more specifically showing a configuration of a main part of the semiconductor memory device shown in FIG. 1;

FIG. 4 is a signal waveform diagram showing an operation of the configuration shown in FIG.

5 is a diagram showing an operation of the IO line precharge circuit shown in FIG.

6 is a signal waveform diagram representing an operation of the IO line precharge circuit shown in FIG.

FIG. 7 schematically shows an entire configuration of a semiconductor memory device according to a second embodiment of the present invention.

8 is a diagram more specifically showing a configuration of a main part of the semiconductor memory device shown in FIG. 7;

FIG. 9 schematically shows an entire configuration of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 10 schematically shows a structure of a main part of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 11 shows a structure of a main part of a semiconductor memory device according to a fifth embodiment of the present invention.

12 is a diagram showing a change in output voltage of the internal power supply circuit shown in FIG.

FIG. 13 is a signal waveform diagram representing an operation of a main part of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 14 is a diagram schematically showing a configuration of a main part of a conventional semiconductor memory device.

15 is a signal waveform diagram representing an operation of the semiconductor memory device shown in FIG.

FIG. 16 is a diagram illustrating a problem of a conventional semiconductor memory device.

[Explanation of symbols]

1 memory cell array, 2 address input buffers, 3
Row select circuit, 4 sense amplifier band, 4a sense amplifier circuit, 5 decode circuit, 5a NAND type decode circuit, 6 column select line drive circuit, 6a column select line driver, 7 column select gate group, 7a column select gate, 8
Internal data bus, I / O, I / O * Internal data bus line, 9 IO line precharge circuit, 9a IO line precharge circuit, 10 write / read circuit, 10a preamplifier, 13, 14 Internal power supply circuit, 20 power supplies Line, 30
Internal power supply circuit, 35, 36 Optional voltage selector,
30e, 30d p-channel MOS transistor, PQ
a, PQb p-channel MOS transistor.

Claims (11)

[Claims] 1. A plurality of memory cells arranged in a matrix, arranged corresponding to each column, and set to a first power supply voltage or a ground voltage level according to memory cell data on a corresponding column when activated. A plurality of sense amplifiers for driving corresponding columns; an internal data bus for transmitting and receiving data to and from a selected memory cell of the plurality of memory cells; a first power supply coupled to the internal data bus for connecting the internal data bus to the first power supply A semiconductor comprising: a precharge circuit for precharging to a voltage level; and a peripheral circuit receiving at least a second power supply voltage as an operation power supply voltage and performing at least an operation of selecting a memory cell from the plurality of memory cells Storage device. 2. The peripheral circuit operates by receiving the second power supply voltage as an operation power supply voltage, decodes a given address signal, and generates a column designation signal designating an addressed column. A column decode circuit, and a column selection drive circuit receiving a third power supply voltage as an operation power supply voltage and generating a column selection signal for selecting an addressed column from the columns of the memory cells according to the column specification signal, 2. The semiconductor memory device according to claim 1, wherein the addressed column is coupled to said internal data bus via a column selection gate responsive to a column selection signal from said column selection drive circuit. 3. The peripheral circuit further includes a read amplifier circuit that receives the second power supply voltage as an operation power supply voltage and amplifies data on the internal data bus.
13. The semiconductor memory device according to claim 1. 4. The semiconductor memory device according to claim 2, wherein said third power supply voltage is at the same voltage level as said first power supply voltage. 5. The semiconductor memory device according to claim 2, wherein said third power supply voltage is at a voltage level between said first and second power supply voltages. 6. The semiconductor memory device according to claim 1, wherein said second power supply voltage has the same voltage level as an externally applied power supply voltage. 7. The semiconductor memory device according to claim 2, wherein said third power supply voltage is at the same voltage level as said second power supply voltage. 8. A first power supply line for receiving and transmitting an external power supply voltage, coupled to the first power supply line, generating the first power supply voltage from the external power supply voltage to generate the first power supply voltage, A first internal voltage generation circuit applied to a charge circuit; and a second circuit for generating a second voltage higher in voltage level than the first power supply voltage from a voltage on the first power supply line when activated.
3. The semiconductor memory device according to claim 2, further comprising: an internal voltage generation circuit, and a selection unit that supplies one of a voltage on the first power supply line and an output voltage of the second internal voltage generation circuit to the column decode circuit. 9. The semiconductor memory device according to claim 8, wherein said selecting means also applies said selected power supply voltage to said column selection drive circuit. 10. A circuit separate from the first internal voltage generating circuit, coupled to the first power supply line, for generating the third power supply voltage from the external power supply voltage and applying the third power supply voltage to the column selection drive circuit 9. The semiconductor memory device according to claim 8, further comprising a third internal voltage generation circuit provided. 11. The semiconductor memory device according to claim 2, further comprising: means for setting a power supply voltage of said column select drive circuit to an external power supply voltage level in response to a test mode instruction.