JP2004134069A - Semiconductor memory device having partial activation structure and enabling page mode operation, and method for operating the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device having a partial activation structure and enabling page mode operation, and a method for operating the same. <P>SOLUTION: A memory cell array is divided to two or more column blocks. The column block is selected in response to a column block selection address. A row decoder (including a word line driver) and a column decoder select a word line and a column line within the selected column block in response to a row address and a column address, respectively. A row address comparator receives a currently inputted row address (described as a first row address) and compares the same with a previously inputted row address (described as a second row address). A precharge circuit automatically deactivates the word line activated after a prescribed time from the input of an activation command, i.e., precharges the word line but if the first and second row addresses are the same as a result of the comparison by the comparator, the circuit shuts off the precharging for the activated word line. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a semiconductor memory device, and more particularly, to implementation of a page mode in a semiconductor memory device having a partially activated structure.

Recently, in the case of a memory device, especially a DRAM, an increase in power consumption due to an increase in operation speed has been raised as a major problem. Generally, in most semiconductor memory devices, there is a trade-off between operation speed and power consumption, so that it is the most difficult and important to properly adjust the two characteristics during the development process. .
In order to solve the above problems, recently, efforts have been made to reduce the memory cell array current in order to simultaneously improve the operation speed and the power consumption. For example, a semiconductor memory device employs a partial activation structure in which a column block in which data is read or written is known in advance when a memory cell is activated and only a corresponding column block is activated. A typical case is FCRAM developed by Fujitsu. The structure and operation of the FCRAM are described in detail in Patent Document 1.

FIGS. 1.A to 1.C illustrate a hierarchical memory structure of a semiconductor memory device that enables partial activation of a block of memory cells according to the related art.
As shown in FIG. 1.A, the semiconductor memory device 10 includes a plurality of memory banks 10A, 10B, 10C, and 10D. Each memory bank represents, for example, the memory logic of the PC, and each bank may be configured with one or more memory modules (eg, DIMM, SIMM). Each of the memory banks 10A, 10B, 10C, and 10D is logically divided into a number of memory cell array blocks. For example, as exemplarily shown in FIG. 1.B, the memory bank 10A includes four memory cell array blocks 100a, 100b, 100c, and 100d.

Each of the memory cell array blocks 100a, 100b, 100c, and 100d is logically divided into a number of sub memory cell array blocks (or column blocks), and each sub memory cell array block is controlled by an associated control circuit. For example, as exemplarily shown in FIG. 1.C, the memory cell array block 100a includes four sub memory cell array blocks 101, 102, 103 and 104. The memory cell array block 100a further includes a number of sub-word line drivers 105, 106, 107, 108, each sub-word line driver being associated with one of the sub-memory cell array blocks 101, 102, 103, 104.

{Each sub-word line driver 105, 106, 107, 108 activates the corresponding sub-word line WL1, WL2, WL3, WL4 of the corresponding column block. That is, the word lines of the memory block 100a are formed on the memory block 100a using the entire word line structure, and such word lines are activated by a row decoder based on an input row address (word line address). You. The sub-word lines are formed on the corresponding column blocks, and the sub-word line drivers 105, 106, 107, and 108 control activation of the corresponding sub-word lines. For example, as shown in FIG. 1.C, when a row address and a column block selection address are input to a memory device, an entire word line corresponding to the input row address is activated by a row decoder. . The input column block selection address uses one of the column blocks 101, 102, 103, and 104 for activation, and the corresponding sub-word line drivers 105, 106, 107, and 108 are activated (overall). Activate the corresponding sub-word line having the same address as the word line.

The memory configuration shown in FIGS. 1.A to 1.C provides a partially activated semiconductor memory device such as FCRAM which can be activated using a column block address CBA to perform a data access or refresh operation. One of the sub memory cell array blocks 101, 102, 103, 104 that can be used for the operation. That is, in the example shown in FIG. 1.C, the memory cell array block 100a includes four hub memory blocks 101, 102, 103, and 104, and the 2-bit CBA is one of four column blocks (sub-memory blocks). , So that those skilled in the art can design the memory configuration above or below the column blocks that can each be addressed by a given column block select address.

In order to perform a memory access operation using the memory configuration shown in FIGS. 1.A to 1.C, one of the memory banks 10A, 10B, 10C, and 10D is initialized in response to a predetermined bank address. And the memory cell array blocks 100a, 100b, 100c, and 100d in the selected memory bank are selected in response to a predetermined address (for example, a row address or another address according to an address structure). Next, the row address RA and the column block selection address CBA are input to activate the entire word line (depending on the decoding result of the input row address of the row decoder), and the selected memory cell array (by the input CBA) is activated. Activate the column block of the block. Next, only the sub-word lines of the selected column block (having the same address as the activated overall word line) are activated by the corresponding sub-word line driver.

For example, in the example of FIG. 1C, if the column block selection address is “00”, the corresponding word line WL1 of the first column block 101 among the entire word lines corresponding to the row address becomes “column block selection address”. If it is “01”, the corresponding word line WL2 of the second column block 102 is, if the column block selection address is “10”, the corresponding word line WL3 of the third column block 103 is, and the column block selection address is “11”. If so, the corresponding word line WL4 of the fourth column block 104 is activated. Therefore, only 1/4 of the memory cells having the same row address are activated. Data is input / output to / from the activated column block. Then, the activated column block is automatically deactivated, that is, precharged after a predetermined time.

The FCRAM uses a partial activation function to reduce current consumption, improve memory cell array operation characteristics, and improve access speed. When tRAC = 22 ns and tRC = 25 ns, the performance improvement of tRAC 10% and tRC 50% as compared with a normal DRAM is realized.
However, in the case of a memory device that operates in the partial activation mode such as an FCRAM, there are some restrictions as compared with a normal DRAM, and one of them is a page that is handled in a general operation mode in a normal DRAM. It is difficult to implement the mode.

The page mode is an operation mode in which after inputting a row X address once, data is input / output to / from an arbitrary memory cell of the entire memory cells having the same row address only by converting the column Y address. The page mode is an operation mode generally employed in a normal DRAM.
However, in the case of a DRAM operating in the partial activation mode, it is difficult to implement the page mode. This is because memory cells connected to the same row address are divided into column blocks and controlled by an arbitrary number n of column block selection addresses that are input together when the row address is input. That is, when the number of column block selection addresses is two, memory cells having the same row address are activated in four units by the column block selection address.

For the above reason, in the case of a DRAM operating in the partial activation mode in which the number of bits of the column block selection address is n and data is input / output to an arbitrary memory cell among all memory cells connected to the same row address. To output, a maximum of ²ⁿ row address inputs are required.
In particular, in the case of FCRAM, the same row address can be further applied after a predetermined time (tRC = active restore time + row precharge time) after inputting an arbitrary row address. It has a structure in which a recharge operation occurs. Therefore, an FCRAM having n column block selection addresses requires a data input / output time for inputting / outputting data to / from an arbitrary memory cell among all the memory cells having the same row address. , A time of at most tRC * ²ⁿ is required.

FIG. 2 is an operation timing diagram of a semiconductor memory device having a partially activated structure according to the related art.
Referring to FIG. 2, a row address X is input together with an active command ACT in synchronization with a clock CLK. At this time, the column block selection address CB1 is also input. The first column block 101 is selected by the column block selection address CB1, and the word line WL1 corresponding to the row address X input in the first column block 101 is activated. If the column address Y is input together with the read command / RD in the next clock cycle C2, one column corresponding to the column address is selected, and an intersection between the activated word line WL1 and the selected column line is obtained. Data is output from a certain memory cell. Since the burst length is 4, four data DQ are continuously output by one read command / RD.

(4) Row precharge starts automatically about three clock cycles after the time C1 at which the active command ACT is applied. When the row precharge starts, the activated word line WL1 is deactivated. At the clock cycle C6 at the end of the row precharge, the next row address X is input together with the column block selection address CB2. That is, in the related art, since the row precharge is automatically performed after a predetermined time after the application of the active command ACT, the next active command ACT may be applied only when the row precharge ends. The time from when the active command ACT is applied to when the next active command ACT is applied is referred to as tRC. The corresponding word line WL2 in the second column block 102 is activated in response to the row address X and the column block selection address CB2 input in the clock cycle C6. Since the row precharge automatically starts three clock cycles after the application of the active command ACT, the next active command ACT and the row address X and the column block selection address CB3 correspond to the row precharge of the activated word line WL2. It may be applied in the clock cycle C11 at the end point.

As described above, in the conventional semiconductor memory device, even if the next row address is the same as the previous row address, the next row address must be input at an interval of tRC. Therefore, when memory cells having the same row address are continuously accessed, the data input / output speed is low.
Therefore, like the FCRAM, the memory cell operates in the partial activation mode having a partial activation structure, that is, n column selection addresses, and is automatically pre-set after a lapse of a predetermined time after a row address is input (at the time of applying an active command). In the case of a DRAM having a charged operation structure, the data input / output speed for an arbitrary row address is increased, but the data input / output speed for the same row address is rather increased. Therefore, it is necessary to improve the data input / output time for an arbitrary memory cell among all the memory cells having the same row address in the DRAM having the above structure.
Korean Patent Publication No. 2000-0017520

Therefore, the technical problem to be solved by the present invention is to improve the operation speed by increasing the data input / output speed for a memory cell that can be specified to the same X (row) address in a semiconductor device having a partially activated structure. To provide a semiconductor memory device.
Another technical problem to be solved by the present invention is to provide a method of operating a semiconductor memory device that increases the data input / output speed for a memory cell that can be designated by the same X (row) address in a semiconductor device having a partially activated structure. To provide.

One aspect of the present invention for achieving the technical object includes a memory cell array divided into a plurality of column blocks, and one of the plurality of column blocks is responsive to a column block selection address input together with a row address. The present invention relates to a semiconductor memory device for selecting a column block and activating a word line corresponding to the row address in the selected column block. A semiconductor memory device according to an aspect of the present invention includes a row address comparator for comparing an input row address (hereinafter, referred to as a first row address) with a previously input row address (hereinafter, referred to as a second row address). And a precharge control circuit for suspending precharge of the activated word line in response to the second row address when the first row address and the second row address match.

According to another aspect of the present invention, there is provided a memory cell array divided into a plurality of column blocks, wherein the memory cells are selected in response to a predetermined column block selection address among word lines having the same row address. And a semiconductor memory device having a partially activated structure in which only a word line of a column block is activated.

A semiconductor memory device according to another aspect of the present invention includes a column decoder for activating a corresponding word line of a selected column block in response to a row address (hereinafter, referred to as a first row address) input when an active command is applied. A word line driver, a column decoder for selecting a column line in which data is input / output in the selected column block in response to a column address, a first row address and a previously input row address (hereinafter, referred to as a first row address). If the two signals are different, the activated word line is automatically deactivated a predetermined time after the application of the active command, and the two signals are the same. For example, a precharge circuit is provided for maintaining the activated word line in an activated state.

According to another aspect of the present invention, there is provided a semiconductor memory device including a memory cell array divided into two or more column blocks, wherein the column blocks are selected in response to a column block selection address. A memory cell array, a row decoder and a word line driver for activating a corresponding word line in the selected column block in response to a row address, and a memory cell array in the selected column block in response to a column address. A column decoder for selecting a column line to which data is input / output, receiving the row address (hereinafter, referred to as a first row address) and comparing the received row address with a previously input row address (hereinafter, referred to as a second row address); A row address comparator to be activated and the activation after a predetermined time after the application of the active command. A pre-charge circuit for automatically pre-charging the selected word line, wherein the pre-charge circuit is activated if the first and second row addresses are the same as a result of the comparison by the row address comparator. The precharge of the word line is cut off.

According to another aspect of the present invention, there is provided a memory cell array divided into a plurality of column blocks, wherein the plurality of column blocks are responsive to a column block selection address input together with a row address. The present invention relates to a method of operating a semiconductor memory device in which one column block is selected and a word line corresponding to the row address is activated in the selected column block.

An operation method of a semiconductor memory device according to an aspect of the present invention includes the steps of: (a) comparing an input row address (hereinafter, referred to as a first row address) with a previously input row address (hereinafter, referred to as a second row address); And (b) suspending precharging of a word line corresponding to the second row address if the first row address and the second row address match.
According to another aspect of the present invention, there is provided a memory cell array divided into two or more column blocks and responding to a predetermined column block selection address among word lines having the same row address. And a method of operating a semiconductor memory device having a partially activated structure in which only a word line of a selected column block is activated.

According to another aspect of the present invention, there is provided a method of operating a semiconductor memory device, comprising the steps of: (a) responding to an input row address (hereinafter referred to as a first row address) when an active command is applied; Activating a line, (b) selecting a column line to which data is input / output in the selected column block in response to a column address, and (c) previously inputting the first row address. And (d) comparing the first and second row addresses with each other if the first and second row addresses are different. (E) comparing the step (c) with the step (c) in which the activated word line is automatically deactivated after a lapse of time, and if the first and second row addresses are the same. Comprises a step of maintaining the activated word line to the active state.

According to the present invention, a page mode can be implemented in a semiconductor memory device having a partially activated structure. Therefore, the data input / output speed for the memory cells having the same row address is increased.

According to the present invention, a page mode can be realized even in a semiconductor memory device having a partially activated structure. Therefore, the data input / output speed with respect to the memory cells having the same row address is increased. Therefore, the operation speed of the semiconductor memory device is improved.

For a full understanding of the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be had to the drawings, and to the drawings, which illustrate preferred embodiments of the present invention. .
Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the drawings. The same reference numerals shown in each drawing indicate the same members.

FIG. 3 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention. 1, the semiconductor memory device includes a memory cell array 100, peripheral circuits 110 to 196 for inputting / outputting data to / from the memory cell array 100, a row X address comparator 200, and a command shifter 300. The memory cell array 100 includes a plurality of memory cells arranged in a matrix of rows and columns. The memory cell array 100 is divided into two or more column blocks so as to be partially activated, as described in detail with reference to FIG. 1.C.

A signal input from the outside and a signal output to the outside are input / output via a buffer. The clock signals CK and / CK are transmitted to each internal block via the DLL and the clock buffer 110.
The command decoder 120 receives the external command signals / CS and FN, decodes them, and generates commands such as an active command, a read command / RD, and a write command / WR. The command generated by the command decoder 120 is input to the control signal generator 150 via the command shifter 300. The command shifter 300 shifts the write command / WR by a predetermined clock cycle. The detailed configuration and operation of the command shifter 300 will be described later.

The control signal generator 150 includes an active control signal generator 152, a precharge control signal generator 154, and a data input / output control signal generator 156, and generates an appropriate control signal for another memory device block. More specifically, active control signal generating section 152 outputs a control signal to active control circuit 192 to control the active operation, and precharge control signal generating section 154 includes precharge enable signal PRECH_EN in precharge control circuit 194. The control signal is output to control the precharge operation, and the data input / output control signal generator 156 outputs a control signal to the data input / output control circuit 196 to control the data input / output operation.

(4) The externally applied address signals A0 to A14, BA0, and BA1 are input to the row decoder 160 and the column decoder 170 via the address buffer 130 and the address latch 140. The row decoder 160 includes a word line driver (not shown), and decodes a row X address to select and activate a corresponding row line (word line) of the memory cell array 100. The column decoder decodes a column Y address and selects a column line of the memory cell array 100 to which data is input / output.

Data input through the data input / output pins DQ [0: m] is stored in the memory cell array 100 via the DQ buffer 180. Data read by the memory cell array 100 is also output to the outside via the data input / output pins DQ [0: m] via the DQ buffer 180.
On the other hand, the row address signal input from the outside is input not only to the row decoder 160 via the address buffer 130 but also to the row address comparator 200. The row address comparator 200 compares an input row address (hereinafter, referred to as a first row address) with an already stored row address (hereinafter, referred to as a second row address). When the first row address is a currently input row address, the second row address is a row address input before the first row address is input.

When the first and second row addresses match, the row address comparator 200 suspends or shuts off the inactivation (precharge) of the corresponding word line of the activated column block in response to the first row address. Of the page mode flag / PM_FLAG. If the page mode flag / PM_FLAG output from the row address comparator 200 is at a predetermined logic level, it means that precharge is interrupted / cut off.

The precharge control circuit 194 determines whether to perform a precharge operation in response to the page mode flag / PM_FLAG output from the row address comparator 200 as well as the precharge enable signal PRECH_EN output from the precharge control signal generator 154. Control. More specifically, if the same row address is input again before the activated column block is precharged, the inactivation point of the previously activated column block is applied next. It is extended to the inactivation point based on the row address.
On the other hand, if the row address comparator 200 determines that the first and second row addresses are different, the previous column block activated by the second row address is automatically precharged after a predetermined time after data input / output. Is done. The detailed configuration and operation of the precharge control circuit 194 will be described later.

By operating the semiconductor memory device as described above, the page mode can be realized by inputting the same row address before the precharge by the previous active command ACT starts. That is, if the same row address is applied, the activation period of the selected column block is extended, so that a function similar to the page mode in which data can be sequentially input / output from a plurality of columns for the same row address is realized. .
At this time, if the row addresses that are successively input are the same, the column blocks have nothing to do with the same. Therefore, a page mode operation can be performed on all memory cells having the same row address.

FIG. 4 is an operation timing diagram of a semiconductor memory device according to an embodiment of the present invention. The operation of the semiconductor memory device according to one embodiment of the present invention will be described in comparison with the operation of the conventional semiconductor memory device with reference to FIG.
Referring to FIG. 4, the row address X1 is input together with the active command ACT in synchronization with the clock CLK. At this time, the column block selection address CB1 is also input. In this embodiment, it is assumed that the row addresses X1, X2, X3, and X4 input together with the four active commands ACT are all the same.

(1) The first column block (101 in FIG. 1.C) is selected by the input column block selection address CB1, and the word line WL1 corresponding to the input row address X1 is activated. If the column address Y1 is input in the next clock cycle C2, one column corresponding to the column address Y1 is selected, and the memory cell at the intersection of the activated word line WL1 and the selected column line is selected. Data is output. Also in this case, since the burst length is 4, four data DQs are continuously output by one read command / RD.

(4) After the column address Y1 is input, the row address X2 and the column block selection address CB2 are input in the next clock cycle C3. The corresponding word line WL2 of the second column block (102 in FIG. 1.C) is activated in response to the row address X2 and the column block selection address CB2. The input row address X2 is input to the row address comparator 200 via the address buffer 130.

The row address comparator 200 compares the currently input row address (first address) X2 with the previously input row address (second address) X1. Here, since it is assumed that the row addresses X1 and X2 are the same, the row address comparator 200 sets the low-level page mode flag / PM_FLAG for cutting off the precharge to the previously activated word line WL1. generate. Then, the precharge for the word line WL1 is suspended, and the word line WL1 maintains an activated state. When the column address Y2 is input in the C4 clock cycle, four data DQ are continuously output in response to the input.

If the row address X3 and the column selection block address CB3 are input together with the third active command ACT in the clock cycle C5, an operation similar to the above operation is performed. Also, when the row address X4 and the column selection block address CB4 are input together with the fourth active command ACT in the C7 clock cycle, an operation similar to the above operation is performed.

The active command ACT is not applied in the C9 clock cycle. Accordingly, the row address comparator 200 determines that the current row address is different from the previous row address X4 and outputs a high-level page mode flag / PM_FLAG. Then, the precharge control circuit 194 of FIG. 3 precharges the activated word lines WL1, WL2, WL3, and WL4 in response to the high-level page mode flag / PM_FLAG.
As described above, according to the present invention, if the previously input row address is the same as the next input row address, the previously activated word line is maintained in the active state to thereby maintain the same row address. Data can be read separately for each address in a column block or continuously in the same column block.

FIG. 5 is an operation timing diagram of a semiconductor memory device according to another embodiment of the present invention. In this embodiment, a data write operation will be described as an example.
A semiconductor memory device according to another embodiment of the present invention performs an operation similar to a write operation of an FCRAM developed by Fujitsu using a write buffer. More specifically, when a write command is issued to the same bank, the write operation is not performed immediately, but the write command that was input before the next write command is executed. That is, if a write command is applied, the address and data input at this time are temporarily stored in a write buffer, and if a next write command for the same bank is input, the address and data correspond to the address stored in the write buffer. Write the data in the write buffer to the memory cell. Therefore, the word line corresponding to the row address input with the write command is not immediately activated, but is performed after the application of the next write command.

5. Referring to FIG. 5, the row address X1 is input together with the active command ACT in synchronization with the clock CLK. In FIG. 5, it is assumed that the row addresses X2, X3, and X4 are the same, and are not the same as X1 and X5. When the row address X1 is input, the column block selection address CB1 is also input. In the next clock cycle C2, the column address Y1 is input together with the write command / WR, and four data D1 are continuously input in two clock cycles after three clock cycles from the input of the column address Y1. The data D1 and the address are stored in a write buffer.

(4) The active command ACT is applied in the clock cycle C6, and the row address X2 and the column block selection address CB2 are input. The input row address X2 is input to the row address comparator 200 via the address buffer 130. The row address comparator 200 compares the currently input row address (first address) X2 with the previously input row address (second address) X1. Here, since it is assumed that the row addresses X1 and X2 are not the same, the row address comparator 200 generates a high-level page mode flag / PM_FLAG. That is, it is not the page mode.

(4) In the next clock cycle C7, the column address Y2 is input together with the write command / WR. Then, the corresponding word line WL1 of the first column block (101 in FIG. 1.C) is activated in response to the row address X1 and the column block selection address CB1 stored in the write buffer. One column corresponding to the column address Y1 is selected, and the data D1 is input to the memory cell at the intersection of the activated word line WL1 and the selected column line. Since the mode is not the page mode, precharge is performed on the previously activated word line WL1.

(4) In the clock cycle C8 following the input of the column address Y2, the active command ACT is applied again, and the row address X3 and the column block selection address CB3 are input. The row address comparator 200 compares whether the currently input row address X3 is the same as the previously input row address X2. Here, since it is assumed that the row addresses X2 and X3 are the same, the row address comparator 200 generates a low-level page mode flag / PM_FLAG indicating the page mode.

{} Then, in the next clock cycle C9, the column address Y3 is input together with the write command / WR. Then, the corresponding word line WL2 of the second column block (102 in FIG. 1.C) must be activated in response to the row address X2 and the column block selection address CB2 stored in the write buffer. The activation of the word line WL2 is delayed by a predetermined first delay time TD1 in order to sufficiently guarantee the operation of the converted word line WL1. When operating in the page mode, the active command application interval is narrower than in the normal mode (non-page mode), so that the activation of the next word line WL2 is performed in order to guarantee the operation of the previously activated word line WL1. Is delayed.

That is, in principle, after the column address Y3 is inputted in the clock cycle C9, the activation of the word line WL2 must be performed. In this case, however, a sufficient operation time for the word line WL1 is not guaranteed. In the embodiment, the activation of the word line WL2 is delayed by about three clock cycles. With the activation of the word line WL2, one column corresponding to the column address Y2 is selected, and the data D2 is input to the memory cell at the intersection of the activated word line WL2 and the selected column line.

Since the activation of the word line WL2 is delayed, the page mode flag / PM_FLAG, which is a signal for determining whether the word line WL2 is inactivated, must be generated with a delay. Preferably, in the write operation mode, the precharge control circuit (194 in FIG. 3) responds to the delayed page mode flag / D_PM by delaying the page mode flag / PM_FLAG by a predetermined clock cycle (second delay time). Control precharge. Therefore, the precharge for the word line WL2 is suspended, and the word line WL2 maintains the active state.

If the row address X4 and the column selection block address CB4 are input together with the active command ACT in the clock cycle C10, the row address X4 is the same as the previous row address X3, so that an operation similar to the above operation is performed.
Active command ACT is not applied in clock cycle C12. Accordingly, the row address comparator 200 determines that the current row address is different from the previous row address X4 and outputs a high-level page mode flag / PM_FLAG. Then, the precharge control circuit 194 of FIG. 3 precharges the activated word lines WL2, WL3, WL4 in response to the high-level page mode flag / PM_FLAG.

As described above, in another embodiment of the present invention, the write operation is performed after the next write command is applied. Accordingly, when operating in the page mode, the activation time of the next word line is delayed by the first delay time in order to guarantee the operation time for the previously activated word line. Since the activation time of the word line is delayed, the generation time of the signal for interrupting / suspending the precharge of the word line is also delayed.

Therefore, according to the present invention, data can be written in the page mode. That is, if the previously input row address is the same as the next input row address, the previously activated word line is maintained in an active state, so that the column block for the same row address is maintained. Can be written separately or continuously in the same column block.

FIG. 6 is a circuit diagram showing a specific example of the instruction shifter 300 shown in FIG. Referring to this, the command shifter 300 includes a clock shifter 310, NOR gates 321, 322, 323 and inverters 331, 332, 333. It is assumed that the page mode flag / PM_FLAG, the write command / WR, and the read command / RD input to the command shifter 300 are all activated at a low level.

(4) The NOR gate 321 receives the write command / WR and the page mode flag / PM_FLAG and performs a NOR operation. The NOR gate 322 receives the inverted signal of the write command / WR and the page mode flag / PM_FLAG and performs a NOR operation. Clock shifter 310 delays the output signal of NOR gate 321 by a first delay time. The NOR gate 323 and the inverter 333 output the logical sum of the output of the clock shifter 310, the output of the NOR gate 322, and the inverted signal of the read command / RD as the delay command S_CMD.

According to the command shifter 300 shown in FIG. 6, if the page mode flag / PM_FLAG is at a low level, the write command / WR is delayed by the clock shifter 310 by the first delay time. If the page mode flag / PM_FLAG is at a high level, the write command / WR is not delayed. On the other hand, the read command / RD is not delayed regardless of the page mode flag / PM_FLAG.

FIGS. 7 and 8 are circuit diagrams respectively showing specific examples of the row address comparator 200 and the precharge control circuit 194 shown in FIG.
Referring to FIG. 7, the row address comparator 200 includes three switches 211, 212, 213, two latch elements 221, 222, and a comparator 230.
The first to third switches 211 to 213 each include a transmission gate and an inverter, and are turned on / off in response to a clock / active signal CLK + ACT CMD. The clock / active signal CLK + ACT CMD is a signal generated in response to the clock CLK and the active command ACT.

The first and third switches 211 and 213 are turned on in response to a first logic level (here, high level) of the clock / active signal CLK + ACT CMD, and the second switch 212 is turned on in response to the second logic level of the clock / active signal CLK + ACT CMD. Turns on in response to a level (here, low level). Each of the first and second latches 221 and 222 includes two inverters.
The row address XADDR input through the address buffer 130 is input to one terminal of the comparator 230. At the same time, if the clock / active signal CLK + ACT CMD is at a high level, the first switch 211 is turned on, and the low address XADDR is input to the first latch 221.

The row address input to the first latch 221 is input to the second latch 222 when the clock / active signal CLK + ACT is low. The low address signal input to the second latch 222 is input to another terminal of the comparator 230 when the clock / active signal CLK + ACT @ CMD is at a high level. A row address directly input to one terminal of the comparator is called a first row address XADDR1, and a row address input to the other terminal of the comparator 230 via the latches 221 and 222 is called a second row address XADDR2. As described above, if the first row address XADDR1 is the currently input row address, the second row address XADDR2 is the previously input row address.

The comparator 230 compares the first row address XADDR1 with the second row address XADDR2, and if both signals match, sets the low-level page mode flag / PM_FLAG. The flag / PM_FLAG is output.
Referring to FIG. 8, the precharge control circuit 194 includes NOR gates 411 and 412, inverters 421 and 422, a NAND gate 431, a clock shifter 310, and a precharge control unit 440.

The NOR gate 411 and the inverter 421 output the logical sum of the page mode flag / PM_FLAG and the write command / WR. The clock shifter 310 shifts a logical sum signal of the page mode flag / PM_FLAG and the write command / WR by a second delay time. NOR gate 412 and inverter 422 output the logical sum of page mode flag / PM_FLAG and read command / RD.

The logical sum signal of the page mode flag / PM_FLAG and the read command / RD is different from the logical sum signal of the page mode flag / PM_FLAG and the write command / WR, and is input to the NAND gate 431 without passing through the clock shifter 310.
Therefore, the page mode flag / PM_FLAG activated at the low level is shifted by the second delay time during the write operation. On the other hand, the page mode flag / PM_FLAG is not shifted during the read operation.

The NAND gate 431 outputs a precharge control signal / PRECH_CS by multiplying the output signal of the clock shifter 310, the output signal of the inverter 422, and the precharge enable signal PRECH_EN by a NOT logic. The precharge enable signal PRECH_EN is a signal that is automatically enabled to a high level a predetermined time after the application of the active command ACT.

However, in the page mode in which the page mode flag / PM_FLAG is enabled at a low level, as shown in FIG. 6, due to the delay of the delay command S_CMD, the precharge signal PRECH_EN is also delayed by the first delay time. Is output. In the conventional semiconductor memory device, if the precharge enable signal PRECH_EN is enabled, the precharge is performed unconditionally.
The precharge control signal / PRECH_CS is input to the precharge control unit 440. The precharge controller 440 performs precharge in response to a low-level precharge control signal / PRECH_CS.

FIG. 9 is an operation waveform diagram of the circuits shown in FIGS. The operation of the row address comparator 200 and the precharge control circuit 194 shown in FIGS. 7 and 8 will now be described with reference to FIG.
Assume that the active command ACT is activated in every odd clock cycle C1, C3, C5, C7, C9. In addition, it is assumed that the row address XADDR of '0000' is input together with the first three active commands ACT, and the row address XADDR of 'FFFF' is input together with the last two active commands ACT.

{In response to the clock CLK and the active command ACT, the clock / active signal CLK + ACT} CMD goes high for a predetermined time. Therefore, clock / active signal CLK + ACT @ CMD also goes high every two clock cycles. The row address signal XADDR is input simultaneously with the activation of the active command ACT. The first row address XADDR1 directly input to one terminal of the comparator 230 is always the same as the externally input row address XADDR. Of course, a slight delay may occur until the row address XADDR is input to one terminal of the comparator.

The first row address XADDR1 of '0000' is input to one terminal of the comparator 230 together with the first active command ACT. When the clock / active signal CLK + ACT CMD goes high (H1 section) in response to the first active command ACT, the first and third switches 211 and 213 are turned on. Therefore, the signal XXXX stored in the second latch 222 is input to the other terminal of the comparator 230 as the second row address XADDR2. At this time, the signal in the second latch 222 is a predetermined initial signal XXXX. At the same time, the first row address XADDR1 of '0000' is input to the first latch 221.
When the clock / active signal CLK + ACT CMD goes low (L1 section), the first and third switches 211 and 213 are turned off and the switch 212 is turned on. Therefore, the signal 0000 in the first latch is input to the second latch 222.

In the C3 clock cycle, the second active command ACT and the row address XADDR of '0000' are input. In response to this, if the clock / active signal CLK + ACT CMD goes high again (H2 section), the first and third switches 211 and 213 are turned on. Therefore, the signal 0000 in the second latch is input to the comparator 230 as the second row address signal XADDR2.
At this time, since the first row address XADDR1 and the second row address XADDR2 are equal to '0000', the comparator 230 outputs a low-level page mode flag / PM_FLAG.
When the clock / active signal CLK + ACT CMD goes low again (L2 section), the second switch is turned on, and the signal 0000 from the first latch is input to the second latch 222.

As a result, the first to third switches 211 to 213 and the first and second latches 221 and 222 store the row address input at the time of the previous active command ACT, and then store the comparator at the time when the next active command ACT is applied. It serves to provide 230. Accordingly, the comparator 230 compares the row address (second row address) input during the previous active command ACT with the row address (first row address) input during the next active command ACT.

Therefore, since the second row address 0000 and the preceding (first) row address 0000 match, the page mode flag / PM_FLAG goes low, and the third row address 0000 and the preceding (second) row address 0000. Since 0000 also matches, the page mode flag / PM_FLAG is kept at low level. The fourth row address FFFF and the preceding (third) row address 0000 do not match, the page mode flag / PM_FLAG goes high, and the fifth row address FFFF and the preceding (fourth) row address Since FFFF further matches, the page mode flag / PM_FLAG further goes low.

On the other hand, the precharge enable signal PRECH_EN is enabled to a high level for a predetermined time about three clock cycles after the application of the active command ACT. Accordingly, the precharge enable signal PRECH_EN is enabled to a high level three times in response to the first to third active commands ACT. However, when the first and second precharge enable signals PRECH_EN are enabled to a high level, the page mode flag / PM_FLAG is at a low level, so that the precharge control signal / PRECH_CS becomes a high level and the precharge control circuit becomes high. 320 interrupts the precharge operation.

When the third precharge enable signal PRECH_EN is enabled to a high level, the page mode flag / PM_FLAG is at a high level, so that the precharge control signal / PRECH_CS goes to a low level, and the precharge control circuit 320 performs precharge. Enable.
As described above, according to the present invention, if the previous row address is compared with the next row address and they match, the precharge is cut off, so that the data input / output operation to the memory cell having the same row address can be performed quickly. it can.

FIG. 10 is a block diagram showing a memory system according to an embodiment of the present invention. The memory system 1000 includes a CPU 1001, a memory controller 1002, and a number of memory modules 1003. The CPU may be a microprocessor unit MPU or a network processor unit NPU. Each memory module 1003 includes a number of semiconductor memory devices 1004 such as FCRAMS.

The CPU 1001 is connected to a memory controller through a first bus system B1 (eg, control bus, data bus, address bus), and the memory controller 1002 is connected to a memory module through a second bus system B2 (control bus, data bus, address bus). 1003. In the example structure of FIG. 10, the CPU 1001 controls the memory controller 1002, and the memory controller 1002 controls the memories 1003 and 1004 (the CPU can directly control the memory without using a separate memory controller). ).

In the example shown in FIG. 10, each memory module 1003 can be represented, for example, in a memory bank, and each memory device 1004 of a given memory module 1003 can operate in the page mode of the present invention. In this case, each memory device 1004 can be logically divided into a plurality of column blocks to provide a partially activated structure, and is controlled as described above to provide a page mode operation. A control circuit for performing the page mode memory access may be located in the memory device 1004.
Preferably, a memory device of one memory module may have a x8 bit configuration, and a memory device of another memory module may have a x16 bit configuration. That is, another memory module can operate with another bit configuration.

A memory system according to another embodiment of the present invention may include one or more separate semiconductor memory devices (instead of the memory module having multiple memory devices shown in FIG. 10) and (without any memory controller). A) a central processing unit may be included; In this embodiment, the memory device is in direct communication with the central processing unit.
In yet another embodiment, a memory system according to the present invention includes one or more separate semiconductor memory devices in direct communication with a memory controller (instead of the memory module having multiple memory devices shown in FIG. 10). Can be made. In this embodiment, one memory device may have a x8 bit configuration and another memory device may have a x16 bit configuration.
According to the present invention, a page mode can be implemented even in a semiconductor memory device having a partially activated structure. Therefore, the data input / output speed with respect to the memory cells having the same row address is increased. Therefore, the operation speed of the semiconductor memory device is improved.

Although the present invention has been described with reference to the embodiment shown in the drawings, it is merely an example, and those skilled in the art may appreciate various modifications and equivalents. It can be understood that the embodiment of FIG. For example, in the present embodiment, when the page mode flag is at the low level, the precharge is described as being suspended, and the active level of the predetermined signal is set to the high level or the low level. It is also possible to determine with. Therefore, the true technical protection scope of the present invention should be determined by the technical idea of the appended claims.

The semiconductor memory device having the partial activation structure provided in the present embodiment and having improved data input / output speed can be used for a memory system of a digital camera, an MP3 player, and a computer device.

1 is a diagram illustrating a hierarchical memory structure of a semiconductor memory device that enables partial activation of a block of memory cells according to the related art. 1 is a diagram illustrating a hierarchical memory structure of a semiconductor memory device that enables partial activation of a block of memory cells according to the related art. 1 is a diagram illustrating a hierarchical memory structure of a semiconductor memory device that enables partial activation of a block of memory cells according to the related art. FIG. 4 is an operation timing diagram of a semiconductor memory device having a partially activated structure according to the related art. FIG. 2 is a block diagram illustrating a semiconductor memory device according to example embodiments. FIG. 4 is an operation timing diagram of a semiconductor memory device according to an embodiment of the present invention. FIG. 6 is an operation timing diagram of a semiconductor memory device according to another embodiment of the present invention. FIG. 4 is a circuit diagram illustrating an example of a command shifter illustrated in FIG. 3. FIG. 4 is a circuit diagram illustrating a specific example of a row address comparator and a specific example of a precharge control circuit illustrated in FIG. 3. FIG. 4 is a circuit diagram illustrating a specific example of a row address comparator and a specific example of a precharge control circuit illustrated in FIG. 3. FIG. 9 is an operation timing chart of the circuits shown in FIGS. 7 and 8. FIG. 2 is a block diagram illustrating a memory system according to an embodiment of the present invention.

Explanation of reference numerals

Reference Signs List 100 memory cell array 110 DLL and clock buffer
Reference Signs List 120 instruction word decoder 130 address buffer 140 address latch 150 control signal generator 152 active control signal generator 154 precharge control signal generator 156 data input / output control signal generator 160 row decoder 170 column decoder 180 DQ buffer 192 active control circuit 194 Precharge control circuit 196 Data input / output control circuit 200 Row address comparator 300 Command shifter CK CK / Clock signal / CS FN Command signal / WD Write command / RD Read command A0 to A14, BA0, BA1 Address signal / PM_FLAG Page mode flag

Claims (36)

Activating a first word line corresponding to a first address to perform a data access operation;
Receiving the second address after receiving the first address;
If the second address is the same as the first address, an activated state of the first word line corresponding to the first address while activating a second word line corresponding to the second address. Generate a page mode enable signal to maintain
Deactivating the first and second word lines in response to the page mode enable signal. The page mode enable signal generating step includes:
Storing the first address;
Comparing the second address with the first address using a comparator to determine whether the first address matches the second address;
2. The method of claim 1, further comprising outputting the page mode enable signal from the comparator when the first address and the second address match. The step of maintaining the first word line active includes:
2. The data access method of claim 1, further comprising suspending a precharge operation of the first word line having the same address while the page mode enable signal is activated. The data access operation is a write operation,
Generating a write command signal;
2. The method of claim 1, further comprising: delaying the write command signal by a predetermined first delay time. 5. The method of claim 4, further comprising: delaying the page mode enable signal by a predetermined second delay time to generate a delayed page mode enable signal. 6. The method of claim 5, wherein the delayed page mode enable signal suspends a precharge operation at least once. 2. The method of claim 1, wherein the first address includes a row address. The method of claim 7, wherein the first address includes a column block selection address. 9. The method of claim 8, wherein the column block selection address includes a column address or a row address. A memory cell array including a number of memory blocks;
An instruction decoder for decoding an instruction signal to perform a data access operation and outputting the decoded instruction signal;
A first address corresponding to the activated first word line is compared with a second address received after the first address, and if the first address matches the second address, a page mode enable signal is generated. An address comparator for
While a second word line corresponding to the second address is activated to perform a data access operation, a precharge operation of the activated first word line is suspended in response to the page mode enable signal. And a precharge control circuit for controlling a precharge operation. The address comparator comprises:
Means for storing the first address;
Means for comparing the second address to the first address to determine whether the first and second addresses match;
11. The semiconductor memory device according to claim 10, further comprising: means for outputting the page mode enable signal from the comparator when the first and second addresses match. The semiconductor memory device further includes an instruction shift circuit operatively connected to outputs of the instruction decoder and the address comparator,
11. The semiconductor according to claim 10, wherein the instruction shift circuit delays a write instruction signal output from the instruction decoder by a predetermined first delay time in response to the page mode enable signal output from the address comparator. Memory device. 11. The semiconductor memory device of claim 10, wherein the command shift circuit includes a clock shifter for delaying the write command signal, and the clock shifter includes a plurality of serially connected inverters. 13. The semiconductor memory device according to claim 12, wherein the command shift circuit includes a clock shifter for delaying the write command signal, and the clock shifter includes a plurality of serially connected flip-flops. 13. The semiconductor memory device according to claim 12, wherein the precharge control circuit delays the page mode enable signal by a predetermined second delay time to generate a delayed page mode enable signal in response to the write command signal. . 17. The semiconductor memory device of claim 15, wherein the delayed page mode enable signal suspends a precharge operation of the activated first word line. 11. The semiconductor memory device according to claim 10, wherein the memory cell array includes a partially activated structure, and each memory block is individually addressable by a block address including at least two or more column addresses. 18. The semiconductor memory device according to claim 17, wherein the data access operation includes a page mode operation in which data is accessed in one or more memory cells having the same row address in the same memory block or another memory block. 19. The semiconductor memory device according to claim 18, wherein the data is accessed using a burst mode. In memory systems,
A memory controller for generating a number of instruction and address signals;
A first memory module that receives the command and the address signal and includes a first memory device;
The first memory device includes:
A memory cell array logically divided by a number of memory blocks;
An instruction decoder for decoding the instruction signal to perform a data access operation and outputting the decoded instruction signal;
A first address corresponding to the activated first word line is compared with a second address received after the first address, and if the first address and the second address match, a page mode enable signal is output. An address comparator for generating;
While a second word line corresponding to the second address is activated to perform a data access operation, a precharge operation of the activated first word line is suspended in response to the page mode enable signal. And a precharge control circuit for controlling a precharge operation. The memory system includes a partial activation structure,
21. The memory system of claim 20, wherein each memory block of the first memory device is individually addressable by a block address. The memory system further includes a second memory module including a second memory device,
21. The memory system of claim 20, wherein the first memory device has a first bit configuration, the second memory device has a second bit configuration, and the first bit configuration and the second bit configuration are different. . In memory systems,
A memory controller for generating a number of instruction and address signals;
A first memory device for receiving the command and address signals,
The first memory device includes:
A memory cell array logically divided by a number of memory blocks;
An instruction decoder for decoding the instruction signal to perform a data access operation and outputting the decoded instruction signal;
A first address corresponding to the activated first word line is compared with a second address received after the first address, and if the first address matches the second address, a page mode enable signal is output. An address comparator for generating;
While a second word line corresponding to the second address is activated to perform a data access operation, a precharge operation of the activated first word line is suspended in response to the page mode enable signal. And a precharge control circuit for controlling a precharge operation. The memory system further includes a second memory device,
24. The memory system of claim 23, wherein the first memory device has a first bit configuration, and the second memory device has a second bit configuration. In memory systems,
A central processor unit for generating a number of instruction and address signals;
A first memory module that receives the command and the address signal and includes a first memory device;
The first memory device includes:
A memory cell array logically divided by a number of memory blocks;
An instruction decoder for decoding the instruction signal to perform a data access operation and outputting the decoded instruction signal;
A first address corresponding to the activated first word line is compared with a second address received after the first address, and if the first address matches the second address, a page mode enable signal is output. An address comparator for generating;
While a second word line corresponding to the second address is activated to perform a data access operation, a precharge operation of the activated first word line is suspended in response to the page mode enable signal. A precharge control circuit for controlling a precharge operation. 26. The memory system of claim 25, further comprising a second memory module including the second memory device. 27. The memory system of claim 26, wherein the first memory device has a first bit configuration, the second memory device has a second bit configuration, and the first bit configuration and the second bit configuration are different. . 26. The memory system according to claim 25, wherein the central processor unit is a network processor unit NPU. In memory systems,
A central processor unit for generating a number of instruction and address signals;
A first memory device receiving the command and address signal and having a first bit configuration;
The first memory device includes:
A memory cell array logically divided by a number of memory blocks;
An instruction decoder for decoding the instruction signal to perform a data access operation and outputting the decoded instruction signal;
A first address corresponding to the activated first word line is compared with a second address received after the first address, and if the first address matches the second address, a page mode enable signal is output. An address comparator for generating;
While a second word line corresponding to the second address is activated to perform a data access operation, a precharge operation of the activated first word line is suspended in response to the page mode enable signal. And a precharge control circuit for controlling a precharge operation. The memory system further includes a second memory device having a second bit configuration,
30. The memory system according to claim 29, wherein the first bit configuration is different from the second bit configuration. 30. The memory system according to claim 29, wherein the central processing unit is a network processing unit NPU. A memory device including a memory array divided into a plurality of memory blocks, the method comprising:
(A) inputting a first row address and a first memory block selection address;
(B) selecting a first memory block in the memory array corresponding to the first memory block selection address and performing the data access operation on the selected first memory block corresponding to the first row address; Activating a first word line of
(C) inputting a second row address and a second memory block selection address;
(D) comparing the second row address with the first row address, and if the second row address matches the first row address, a control signal for suspending precharging of the first word line. And selects a second column block in the memory array corresponding to the second column block selection address, and activates a second word line of the selected second column block corresponding to the second row address. Stage,
(E) while each successive input row address matches the last input row address, the previously activated word line having the same address starting from the first activated word line is deactivated. Maintaining the control signal in an enabled state to suspend the operation;
(F) if the consecutive input row addresses do not match the last input row address, disabling the control signal to deactivate any previous activated word lines having the same row address. Including data access methods. 33. The data access method according to claim 32, wherein the first selected memory block and the second selected memory block match. Inputting a first row address and a first memory block selection address includes inputting a first activation command in synchronization with the first row address and the first memory block selection address in a first clock cycle. ,
The data access method includes:
Inputting a first data access command in synchronization with a first column line address in a second clock cycle after the first clock cycle;
33. The data access method according to claim 32, further comprising: receiving a second activation command in synchronization with the second row address and the second memory block selection address in a third clock cycle after the second clock cycle. . The first data access command is a write command,
The method comprises:
A write command is delayed for a first predetermined period to delay activation of the first word line corresponding to the first row address, and a previously activated word having an address different from the first row address is delayed. 35. The data access method according to claim 34, further comprising enabling a precharge of a line. The method comprises:
36. The data access method according to claim 35, further comprising delaying the output of the control signal by a predetermined time by the delayed activation of the first word line.

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