CN100495568C - Method for accessing data and device and system for using the method - Google Patents

Method for accessing data and device and system for using the method Download PDF

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CN100495568C
CN100495568C CN 200310100727 CN200310100727A CN100495568C CN 100495568 C CN100495568 C CN 100495568C CN 200310100727 CN200310100727 CN 200310100727 CN 200310100727 A CN200310100727 A CN 200310100727A CN 100495568 C CN100495568 C CN 100495568C
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method
accessing
data
device
system
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CN1497607A (en )
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李润相
李祯培
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三星电子株式会社
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/10Decoders
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/12Group selection circuits, e.g. for memory block selections, chip selection, array selection

Abstract

一种具有部分激活构架的半导体存储器件,在以部分激活模式操作的同时提供有效的页面模式操作。 Activating the frame portion having a semiconductor memory device, while the mode of operation to partially activate a valid page mode operation. 控制电路和方法被用来启动具有部分激活构架的半导体存储器件(比如DRAM,FCRAM)中的页面模式操作(用于读写数据存取),从而提高当数据从具有相同字线地址的存储位置写/读时的数据存取速度。 The control circuit and method are used to start a semiconductor memory device (such as DRAM, FCRAM) having a partially activated in the page frame mode operation (access for reading and writing data) to improve from a storage location with the same address as the word line data write data access speed read /. 在一个方面,一种存取存储器中数据的方法包括:激活对应于第一地址的第一字线以执行数据存取操作;接收第一地址后的第二地址,如果第二地址与第一地址相同,生成页面模式标记信号,以便在激活对应于第二地址的第二字线的同时保持对应于第一地址的第一字线的已激活状态;并响应页面模式标记信号的禁止,去激活第一和第二字线。 In one aspect, a data memory access comprising: activating the first word line corresponding to the first address to perform data access operation; receiving a first address of the second address, a second address if the first the same address, the page mode flag signal generation, so as to maintain a first word line corresponding to the first address in the activated state while activating the second word line corresponding to the second address; page mode in response prohibition flag signal, to activating the first and second word lines.

Description

存取数据的方法以及使用该方法的器件和系统相关申请的交叉参考 The method of accessing data as well as the use of devices and systems CROSS REFERENCE TO RELATED APPLICATIONS method

本申请要求2002年10月10日于韩囯知识产权局提交的第2002-61042 号韩国专利申请的优先权,它在该申请中被作为参考文件引用。 This application claims priority No. 2002-61042 filed in the Korean Intellectual Property Office, 2002 October 10 Korean Patent Application, which is cited as a reference document in the application.

技术领域 FIELD

本发明涉及一种在具有部分激活结构的半导体存储装置中提供页面模式操作的电路和方法。 The present invention relates to a circuit and method for providing the page mode operation in a semiconductor memory device having a structure partially activated.

背景技术 Background technique

长期以来一直存在对半导体器件如DRAM (动态随机存取存储器)器件的需求,该器件提供了快速和有效的存储器存取操作(读写操作)。 Has long been a need exists for a semiconductor device such as a DRAM (Dynamic Random Access Memory) device, the device provides a fast and efficient memory access operation (write operation). 但是随着DRAM的存储器存取速度增加,功率耗散通常随之增加,这可能造成严重的问题。 But with the increase in DRAM memory access speed, power dissipation is typically increases, which may cause serious problems. 因此,当开发半导体存储器件时,操作速度和功率耗散是通常认为的折衷关系。 Thus, when developing a semiconductor memory device, the operation speed and power dissipation are generally considered the trade-off relationship. 某些控制功率耗散同时又提供高速操作的技术已经集中在减少存储单元阵列电流方面。 Certain control power dissipation while providing high-speed operation technologies have been focused on reducing the memory cell array current aspect. 例如,已经开发了具有部分激活结构的半导体存储装置,该半导体存储装置能够使多个存储单元阵列块的一个激活,以便在一个激活的存储块中执行存储器存取操作。 For example, semiconductor memory devices have been developed having a partially activated configuration, the plurality of semiconductor memory device capable of a memory cell array block activation, in order to perform a memory access operation on the activated memory block. 具有部分激活结构的半导体器件的一个例子是由富士通有限公司开发的FCRAM (快速循环随机存储存储器)。 Examples of a semiconductor device having a structure partially activated by Fujitsu Limited developed FCRAM (Fast Cycle Random Access Memory).

图1A至图1C示出现有技术的半导体存储器件的分级存储器结构,它能够部分激活存储单元的多个块。 1A to 1C art hierarchical memory structure illustrating a semiconductor memory device, it is possible to partially activate the plurality of blocks of memory cells. 如图1A所示,半导体存储器件(IO)包括多个存储体(10A、 IOB、 IOC、 IOD)。 1A, a semiconductor memory device (IO) comprises a plurality of memory banks (10A, IOB, IOC, IOD). 每个存储体例如代表PC中的存储器的一个逻辑单元;每个存储体可以由一个或多个存储模块(例如,DIMM (双列直插存储模块),SIMM(单列直插存储模块))组成。 Each memory bank such as one representative of the PC logic unit memory; each bank may be composed of one or more memory modules (e.g., DIMM (dual inline memory module), SIMM (single in-line memory module)) composed of . 每个存储体(IOA、 IOB、 IOC、 10D)在逻辑上还被分成多个存储单元阵列块。 Each bank (IOA, IOB, IOC, 10D) is further logically divided into a plurality of memory cell array blocks. 例如,如图IB 的示范性实施例所示,存储体(IOA)包括四个存储单元阵列块(100a、 100b、 100c、 lOOd)。 For example, FIG. IB exemplary embodiment illustrated, bank (IOAs) comprises four memory cell array blocks (100a, 100b, 100c, lOOd). 此外,每个存储单元块(100a、 100b、 100c、 100d)在逻辑上还被分成多个子存储单元阵列块(或列块),其中每个子存储单元阵列块由关联的控制电路控制。 Further, each memory cell block (100a, 100b, 100c, 100d) is further logically divided into a plurality of sub memory cell array block (or column block), where each sub memory cell array block controlled by an associated control circuit. 例如,如图1C的示范性实施例所示,存储单元阵列块(100a) 包括四个子存储单元阵列块(101、 102、 103、 104)。 For example, the exemplary embodiment illustrated in FIG. 1C, the memory cell array block (100a) comprises four sub-memory cell array blocks (101, 102, 103, 104). 存储单元阵列块(100a) 还包括多个子字线驱动器(105、 106、 107、 108),其中每个子字线驱动器与子存储单元阵列块(101、 102、 103、 104)之一相关联。 Memory cell array block (100a) further comprises one of a plurality of sub word line drivers (105, 106, 107, 108), wherein each of the sub-word line driver and the sub-memory cell array blocks (101, 102, 103, 104) is associated.

每个子字线驱动器(105、 106、 107、 108)激活相应的列块的相应子字线(WL1、 WL2、 WL3/WL4)。 Each sub-word line driver (105, 106, 107, 108) to activate the corresponding respective sub-word block column (WL1, WL2, WL3 / WL4). 具体地说,存储块(100a)的字线使用整体字线(global wordline)构架在存储块(100a)上形成,这种字线由一个行译码器根据输入行地址(字线地址)激活。 Specifically, the memory block (100a) using a whole word line word line (global wordline) formed on the memory block frame (100a), which the word line activated by the row decoder in accordance with an input row address (word line address) . 子字线在相应的列块上形成, 子字线驱动器(105、 106、 107、 108)控制相应的子字线的激活。 Sub word lines are formed on the corresponding column block, a sub word line drivers (105, 106, 107, 108) to control activation of the respective sub-word lines. 例如, 在一个图1C的示范性实施例中,当行地址和列块选择地址被输入到存储装置时,对应于输入行地址的整体字线被行译码器激活。 For example, in one exemplary embodiment of FIG. 1C, when the row address and column block select address is input to the storage means, the word line corresponding to the overall input row address is activated row decoder. 此外,输入列块选才奪地址;陂用来激活列块(101、 102、 103、 104)之一,4吏相应的子字线驱动器(105、 106、 107、 108)激活具有与已激活的(整体)字线相同地址的相应子字线。 Further, the input block is selected only capture column address; Pei to activate the column block (101, 102, 103, 104) one of the respective officials 4 sub-word line driver (105, 106, 107, 108) has activated activation the (overall) corresponding to the same sub-word line word line address.

图IA-C所示的存储器构架是存储器构架的一个实例,它可以用来提供部分激活半导体存储器件如FCRAM,从而可以使用例如列块地址(CBA) 激活子存储单元阵列块(101、 102、 103、 104)之一,以执行数据存取或者刷新操作。 The memory architecture shown in FIG. IA-C is an example of a memory architecture that can be used to provide a semiconductor memory device such as partially activate the FCRAM, so that the column may be used, for example, a block address (CBA) activator memory cell array block (101, 102, 103, one of 104), or data access to perform a refresh operation. 例如,在图1C的实例中,由于存储单元阵列块(100a)包括四个子存储块(101、 102、 103、 104),因此2比特CBA可以用来选择四个列块(子存储块)之一,尽管本领域熟练技术人员将容易理解,存储器构架可以采用由预定列块选择地址单独寻址的或多或少的列块来设计。 For example, in the example of FIG. 1C, since the memory cell array block (100a) includes four memory sub-blocks (101, 102, 103, 104), so 2 bits are used to select four CBA column block (sub memory block) of First, although the skilled artisan will readily appreciate, the memory architecture can be employed by the predetermined column block select address individually addressable column blocks to design more or less.

为了使用图1A-1C所示的存储器构架执行存储器存取操作,首先响应预定存储体(memory bank)地址选4奪存储体(10A、 10B、 10C、 10D)的一个,然后响应预定地址(例如,依赖于寻址方案的行地址或任何其它地址)选择已选择存储块内的存储单元阵列块(100a、 100b、 100c、 lOOd)。 To use shown in Figures 1A-1C memory architecture memory access operation performing, in response to a predetermined first memory bank (memory bank) address of a selected memory bank wins 4 (10A, 10B, 10C, 10D), and then in response to a predetermined address (e.g. , dependent on the addressing scheme of row address or any other address) to select the selected memory cell array blocks (100a within memory block, 100b, 100c, lOOd). 然后,输入行地址(RA)和列块选择地址(CBA),以激活整体字线(基于行译码器的输入行地址的译码结果)和激活已选择存储单元阵列块的列块(基于输入CBA)。 Then, the input row address (RA) and a column address selection block (the CBA), to activate the entire word line (row based on the decoding result of the input of the row address decoder), and activate the selected memory cell block column array block (based on enter CBA). 然后,仅由相应的子字线驱动器激活已选择列块的子字线(具有与激活的整体字线相同的地址)。 Then, only the selected sub-word block column corresponding sub-word line driver activated by (having the same activated wordline address overall). 例如,在图1C的示范性实施例中,当输入列块选择地址00时,根据 For example, in the exemplary embodiment of FIG. 1C, when the input 00 column block select address, in accordance with

输入的行地址激活对应于第一列块(101 )的子字线WL1。 Activation of the row address input corresponding to the first column block (101) sub-word line WL1. 当输入列块选择地址Ol时,对应于第二列块(102)的子字线WL2被激活。 When the input column block select address Ol, column blocks corresponding to a second (102) sub-word line WL2 is activated. 当输入列块选择地址10时,激活对应于第三列块(103 )的子字线WL3。 When the input address to select blocks 10, corresponding to the activation of the third column block (103) of the sub-word line WL3. 当输入列块选^棒地址11时,激活对应于第四列块(104)的子字线WL4。 When the input address column blocks selected from ^ rod 11, corresponding to the fourth column block activation (104) of the sub-word line WL4. 这样,i"又激活具有相同行地址的存储单元的四分之一。然后根据输入列线地址(column line address)向/从已激活列块输入/输出数据。此外,在一个预定时间量之后,使已激活列块的子字线自动去激活(不工作),即预充电。 Thus, i "a quarter turn activates memory cells in the same row address. Then the / column block input / output according to the input data from the activated column address lines (column line address). Further, after a predetermined amount of time the activated column block sub-word line is automatically deactivated (inactive), precharge.

FCRAM执行部分激活模式以减少电流消耗并改进存储速度。 Operative FCRAM active mode to reduce current consumption and improving memory speed. 在FCRAM中,tRAC (激活恢复时间)和tRC (行预充电时间)分别是22ns 和25ns,与传统的DRAM相比较,表现出tRAC和tRC分别改善了10%和50%。 In the FCRAM, tRAC (activation recovery time) and tRC (row precharge time) are respectively 22ns and 25ns, compared with the conventional DRAM, and exhibit tRAC tRC are improved by 10% and 50%.

与传统的DRAM相比,存在与按照部分激活模式操作DRAM器件相关联的某些问题。 Compared with the conventional DRAM, there are some problems associated with the operation of the DRAM device according to the active mode section. 例如,在部分激活模式的DRAM操作中,难于执行读/写数据的"页面模式,,操作。如本技术领域公知的那样,"页面模式"通常是指这样一种操作模式: 一旦输入行地址X后,仅改变列地址Y就可以向/从具有相同行地址X的多个存储单元输入/输出数据。传统的DRAM器件按"页面模式"操作以增加存储器存取速度,同时减少功率消耗。 For example, in a DRAM in an active mode operation part, is difficult to perform the read / write data ",, page mode operation as well known in the art as." Page Mode "generally refers to a mode of operation: Once the input row address after X, Y changing only the column address can be to / from a storage unit a plurality of input / output data having the same row address X traditional DRAM device press "page mode" to increase memory access speed while reducing power consumption.

页面模式操作难于在以部分激活模式操作的DRAM中实现,因为如结合图1C所述,连接相同行地址(整体字线地址)的存储单元选择性激活/ 控制是根据借助行地址输入的列块选择地址实现的。 Page mode operations in a DRAM difficult to implement in a partially activated mode of operation, since, as the connection with Figure 1C, the memory cell is selectively connected to the same row address (the whole word line address) activation / control means is a row address input column block select the address to achieve. 更具体地说,当具有n 比特列块选择地址的DRAM以部分激活模式操作时,必须输入最大达2n 倍数目的相同行地址,以便向/从相同行地址的所有列块中的存储单元输入/ 输出数据。 More specifically, when the n-bit DRAM having column block select address operation in the active mode section, up to the maximum 2n must be entered multiple purposes in the same row address, so that to / from the storage unit inputs the same row of all column blocks in the address / Output Data. 实际上,关于传统设计,当借助激活命令信号ACT输入一个给定行地址时,仅仅在预定时间(即,tRC)之后输入下一个地址(和激活命令ACT ),因为在自行地址输入起的预定时间之后自动执行行预充电操作。 In fact, on traditional designs, when activated by a command signal ACT given input row address, only the next address input (and active command ACT) at a predetermined time (i.e., tRC) then, because the self-address entered from the predetermined after the time-line precharge operation is automatically executed. 因此,由于FCRAM具有n比特列块选择地址,为了向/从所有列块中具有相同行地址的存单元输入/输出数据,因此存储器存取时间等于最大达tRCx2"的时间加数据输入/输出时间。下面结合图1C和图2以实例解释这些概念。 Accordingly, since the FCRAM having an n-bit column block select address, in order to / storage unit having the same row address input / output blocks of data from all columns, and thus memory access time equal to the maximum of tRCx2 "time plus the data input / output time below in conjunction with FIGS. 1C and example 2 to explain these concepts.

图2是说明具有上述部分激活构架的传统半导体存储器件的存储器存取操作的时序图。 FIG 2 is a timing chart of a conventional semiconductor memory device having the above-mentioned memory frame partially activated access operation instructions. 具体地说,图2的实例图示说明了具有图1C所示的部分 Specifically, the example of Figure 2 illustrates the portion shown in FIG. 1C having

激活结构的传统半导体器件的操作,其中使用脉冲串长度是4的脉冲串模式执行读操作。 Operation of a conventional semiconductor device structure of activation, in which the burst length is 4, the burst mode read operation. 在图2的实例中,每个输入行地址X被认为是相同的。 In the example of FIG. 2, each input row address X is considered to be the same. 参见图2,第一激活命令ACT、行地址X和列块选择地址CBI借助时钟周期Cl的时钟信号CLK同步输入。 Referring to Figure 2, a first active command ACT, row address X and the column Cl by CBI block select address period of the clock signal CLK to the clock synchronization input. 在响应时,第一列块(101 )被列块选择地址CBI选择,并且在第一列块(101 )中激活对应于输入行地址X的字线MLI。 In response, a first column block (101) is selected CBI column block select address, and activates a row address input corresponding to the word line X MLI in a first column block (101). 当在后续时钟周期C2输入读命令/RD和列地址Y时,选才奪对应于列地址Y的列,以便把存储单元输出的数据定位在已激活字线MLI和已选择列线的交集(交叉点)。 When the C2 input in a subsequent clock cycle read command / RD and the column address Y, before the election wins the corresponding column to a column address Y, to the data storage unit outputs positioned in the activated word line MLI, and the selected column lines of intersection ( intersection). 由于脉冲串长度是4,因此根据读命令/RD从输入列地址开始连续输出四个数据比特DQ。 Since the burst length is 4, so in accordance with the read command / RD start four successive data bits DQ output from the column address input.

在传统的设计中,当施加激活命令ACT时,在自时钟周期Cl起的约三个(3)周期之后自动开始行预充电。 In conventional designs, when applying the active command ACT, row precharge starts automatically after approximately three clock cycles from the starting Cl (3) cycles. 然后响应行预充电操作的开始,去激活已激活的子字线WLI。 Then the response start line precharge operation, deactivation of the activated sub-word line WLI. 在结束行预充电操作之后,在时钟周期C6处输入下一个激活命令ACT、行地址X和列块选择地址CB2。 After the end of the precharge operation line, at the input of the clock cycle C6 active command ACT, row address X and the column address selection block CB2. 由于在自激活命令ACT的输入起的预定时间量之后自动开始行预充电,因此当行预充电结束后可以施加随后的激活命令ACT。 Since the input from the activation command ACT row precharge begins automatically after a predetermined amount of time played, so when the end of the precharging may be applied subsequent to the active command ACT. 从激活命令ACT的输入到下一个激活命令ACT的时段被称之为tRC (行预充电时间)。 Period from the activation command ACT input to the next active command ACT is called tRC (row precharge time). 响应时钟周期C6处输入的行地址X和列块选^r地址CB2,激活第二列块(102 )中的相应字线WL2。 Clock cycle in response to input row address X is selected from C6 ^ r and the column address block CB2, activating the corresponding word line WL2 of the second column block (102). 然后,在时钟周期C9自动开始行预充电,预充电时间为自时钟周期C9的激活命令ACT的输入起的三个(3)时钟周期。 Then, at clock cycle starts automatically C9 line precharge, the precharge time from the clock cycle to activate C9 command input from the ACT of three (3) clock cycles. 因此,仅仅在激活子字线WL2的预充电操作结束时的时钟周期Cll处可以施加下一个激活命令ACT、行地址X和列块选4奪地址CB3。 Under Therefore, only the clock cycle when activated Cll at the end of sub-word line WL2 of the precharge operation can be applied to an active command ACT, row address X and the column block selection address wins 4 CB3. 所以,如上所述,在自命令输入开始的预定时间之后自动执行预充电操作的传统DRAM器件(比如FCRAM) 中,甚至当下一个行地址与在前输入的行地址相同时,也仅仅能够在时间量tRC之后输入行地址。 Therefore, as described above, the conventional DRAM device automatically performs a precharge operation after a predetermined time from the command input (such as the FCRAM), even in the next preceding row address and the row address inputs are the same, it is only possible time enter the amount of row address after tRC.

因此,尽管传统DRAM器件(比如FCRAM),其中在部分激活模式操作中n比特列块选择地址允许选择存储器的2。 Thus, although the conventional DRAM devices (such as the FCRAM), wherein the portion of the active mode n-bit column address selection block 2 allows selection of the memory operation. 列块中的一个,可以提高输入不同行地址时的存储器存取的I/O速度,但由于部分操作模式需求在自给定行地址的输入(即,激活命令的输入)起的预定时间之后执行预充电操作,因此当输入某些行地址时,该器件可以提供比其它传统半导体存储器 A column block, the memory access can be increased when the input row address different I / O speed, but because some operating mode demand from a given input row address (i.e., an activation command input) is performed after a predetermined time from a precharge operation, so that when certain input row address, the device may be provided other than the conventional semiconductor memory

件(例如,SDRAM, DDR, DRAM)慢的存储器存取速度。 Member (e.g., SDRAM, DDR, DRAM) memory access speed is slow. 所以,人们期望提供一种增加存储器存取的I/0速度的电路和方法,以便在为相同的在前和随后的行地址执行存储器存取时,增加具有部分激活 Therefore, it is desirable to provide a circuit and method for memory accesses I / 0 speed increases, so that when the front access to the same row address and the subsequent execution memory, having increased activation portion

构架的DRAM中的存储器存取的I/O速度。 Frame in DRAM memory access I / O speed. 发明内容 SUMMARY

本发明的目的是提供一种具有部分激活构架的半导体存储器件,该器件在以部分激活模式操作的同时提供有效的页面模式操作。 Object of the present invention is to provide a partially activated framework semiconductor memory device, while the device in a partially activated mode of operation to provide a valid page mode operation. 本发明还提供了控制电路和方法,能够在具有部分激活构架的半导体存储器件(比如DRAM、 FCRAM)中启动页面模式操作(用于读写数据存取),由此提高当数据从具有相同字线地址的存储位置写入/读出时的数据存取速度。 The present invention further provides a control circuit and method capable of activating the frame having a portion of a semiconductor memory (such as DRAM, FCRAM) start page mode operation (access for reading and writing data), thereby improving when the data word from the same write line address storage location of data access speed / reading.

在一个实施例中, 一种存取存储器件中数据的方法包括:激活对应于第一地址的第一字线,以执行数据存取操作;接收第一地址后的第二地址, 如果第二地址与第一地址相同,则生成页面模式标记信号,以保持对应于第一地址的第一字线的已激活状态,同时激活对应于第二地址的第二字线; 响应页面模式标记信号的禁止,去激活第一和第二字线。 In one embodiment, a data memory access device comprises: activating the first word line corresponding to the first address, to perform data access operation; and a second address receiving a first address, if the second the same address as the first address, the page mode flag signal is generated to remain activated and the first word line corresponding to the first address, while activating the second word line corresponding to a second address; page mode in response to the flag signal prohibited, deactivates the first and second word lines.

在另一个实施例中,半导体存储器件包括:包含多个存储块的存储单元阵列,命令译码器,用于对命令信号译码,以及输出已译码命令信号以 In another embodiment, a semiconductor memory device comprising: a memory cell array comprising a plurality of memory blocks, a command decoder for decoding command signals, and outputs the decoded command signal to

执行数据存取操作;行地址比较器,用于将对应于已激活第一字线的第一地址与第一地址之后接收的第二地址进行比较,如果第一地址与第二地址相同,则生成页面模式标记信号,如果第二地址与第一地址不同,则第一字线被预充电;预充电控制电路,用于控制预充电操作,其中预充电控制电路响应页面模式标记信号以防止已激活第一字线的预充电操作,同时激活对应于第二地址的第二字线以执行数据存取操作。 Performing the data access operation; a row address comparator for comparing the address corresponding to the second received after activation of the first address and the first address of the first word line are compared, if the first address and the second address are the same, then page mode flag generating signal, if the second address is different from the first address, the first word line is precharged; precharge control circuit for controlling the pre-charging operation, wherein the control circuit is responsive to a precharge signal to prevent the page mode flag has been inactivating the precharge operation of the first word line, while activating the second word line corresponding to a second address to perform data access operations.

最好是,存储单元阵列包括部分激活构架,其中每个存储块可由块地址单独寻址。 Preferably, activating the memory cell array comprises a frame portion, wherein each memory block may be individually addressable block address. 数据存取操作包括一个页面模式操作,其中对于一个或多个具有相同存储块或不同存储块中相同行地址的存储单元存取数据。 Data access operation comprises a page mode operation, wherein for the one or more memory cells having the same memory block or different blocks in the same row address memory access data. 数据可以使用脉沖串操作模式存取。 Data can be accessed using the burst mode of operation.

在另一个实施例中,行地址比较器包括:存储第一地址的装置;将第二地址与第一地址比较以确定第一和第二地址是否相同的装置;如果第一和第二地址相同则从比较器输出页面模式标记信号的装置。 Means for storing a first address; the first address and the second address to determine whether the same address of the first and second means; if the same first and second address: In another embodiment, the row address comparator comprising comparator means from the output signal of the mode flag page.

在另一个实施例中,半导体存储器件包括命令移位器电路,可操作地连接到命令译码器和行地址比较器的输出端,其中命令移位器将从命令译码器输出的写命令信号延迟预定的第一延迟时间。 In another embodiment, the semiconductor memory device includes a command shifter circuit, operatively connected to the output of the command decoder and a row address comparator, wherein the shifter command output from the command decoder write command delaying the first signal a predetermined delay time. 在一个实施例中,命令移位器电路包括延迟写命令信号的时钟移位器,该时钟移位器包括多个串联连接的反相器。 In one embodiment, the command shifter circuit includes a delay shift clock signal is a write command, a clock shifter comprises a plurality of serially connected inverters. 在另一个实施例中,命令移位器电路包括延迟写命令信号的时钟移位器,该时钟移位器包括多个串联连接的触发器。 In another embodiment, the command shifter circuit includes a delay shift clock signal is a write command, a clock shifter comprises a plurality of flip-flops connected in series.

在另一个实施例中,响应写命令信号,预充电控制电路将页面模式标记信号延迟预定的第二延迟时间,以生成已延迟页面模式标记信号。 In another embodiment, in response to a write command signal, the precharge control circuit page mode flag signal delay of a second predetermined delay time to generate a delayed page mode flag signal. 已延迟页面标记信号防止已激活字线的预充电操作。 Prevent delayed page flag signal is activated the word line precharge operation.

下面将说明本发明的这些和其它实施例、各方面、特点和优点,并使其从下面结合附图的优选实施例的详细说明中变得更加清楚。 These will be described and other embodiments of the present invention, aspects, features and advantages of the drawings and allowed to detailed description of preferred embodiments in conjunction with the following become apparent.

附图说明 BRIEF DESCRIPTION

图1A至图1C示出了已有技术的半导体存储器件的分级存储器结构, 1A to 1C shows a hierarchical memory structure of the semiconductor memory device of the prior art,

它能够部分激活存储单元的诸多块; It is possible to partially block the activation of many memory cells;

图2是说明具有部分激活构架的传统半导体存储器件的传统存储器存取操作的时序图; FIG 2 is a timing diagram illustrating a conventional memory having a conventional semiconductor memory device partially activated framework access operation;

图3示意地说明了本发明一个实施例的具有部分激活构架的半导体存储器件,它提供部分激活操作模式的有效页面模式操作; Figure 3 schematically illustrates a semiconductor memory device having a partially activated architecture embodiment of the present invention, it provides efficient page mode operation section active mode of operation;

图4是说明本发明一个实施例的存储器存取操作的示范性时序图,被实施于一个具有部分激活构架的半导体存储器件; FIG 4 is a timing diagram illustrating an exemplary embodiment of a memory access operation of the present invention, be implemented in a partially activated frame having a semiconductor memory device;

图5是说明本发明一个实施例的存储器存取操作的一个示范性时序图, 被实施于一个具有部分激活构架的半导体存储器件; FIG 5 is a diagram illustrating an embodiment of the present invention the memory access timing diagram of an exemplary operation, a partial activation is implemented in a semiconductor memory device having a frame;

图6是说明本发明一个实施例的命令移位器的电路图,该移位器最好实施于图3的器件; FIG 6 is a circuit diagram of a shifter commands embodiment of the present invention is preferably implemented in the shift device of Figure 3;

图7是说明本发明一个实施例的行地址比较器的电路图,该比较器最好实施于图3的器件; FIG 7 is a circuit diagram of a row address comparator of the embodiment of the present invention, the comparator is preferably implemented in the device of Figure 3;

图8是说明本发明一个实施例的预充电控制电路的电路图,该控制电路最好实施于图3的器件; FIG 8 is a circuit diagram illustrating an embodiment of the precharge control circuit of the embodiment of the present invention, the control circuit is preferably implemented in the device of Figure 3;

图9是说明图7和图8的行地址比较器和预充电控制电路的操作模式的示范性时序图; FIG 9 is a diagram illustrating the row address compare FIGS. 7 and 8 and a precharge timing chart of an exemplary mode of operation of the control circuit;

图10是说明可以实施本发明的存储系统的示意性方框图。 FIG 10 is a schematic block diagram of the storage system of the present invention may be implemented. 具体实施方式 detailed description

本发明是一种以部分激活操作模式提供有效页面操作的半导体存储器件。 The present invention is an operation to provide an effective portion of a page active mode of operation of the semiconductor memory device. 具体而言,本发明优选实施例的电路和方法基于提供改进的页面模式 Specifically, the circuit and method of the embodiment to provide an improved page mode based on the preferred embodiment of the present invention

操作和增加具有部分激活构架的半导体存储器件(比如DRAM、 FCRAM) 的数据存取速度的寻址方案和控制电路。 Handling and increased addressing scheme and control circuit of the semiconductor memory device (such as DRAM, FCRAM) having a frame portion activation data access speed.

图3是说明本发明一个实施例的具有部分激活构架的半导体存储器件的方框图,以部分激活操作模式提供有效页面模式操作。 FIG 3 is a block diagram of a semiconductor memory device having a partially activated architecture described embodiment of the present invention, there is provided a valid page mode to active mode of operation section. 参见图3,半导体存储器件包括:存储单元阵列(100);向/从存储单元阵列(100)输入/输出数据的多个外围电路(110至196);行地址比较器(200);命令移位器(300 )。 Referring to Figure 3, a semiconductor memory device comprising: a memory cell array (100); shift command; to / from a plurality of peripheral circuits (110-196) from a memory cell array (100) input / output transactions; row address comparator (200) bit (300). 为了说明目的,在整个下文的讨论中假定存储单元阵列(100)包括结合图1A、图1B、图1C讨论的阵列结构。 For purposes of illustration, assume that the entire memory cell array in the following discussion (100) include a combination of FIGS. 1A, 1B, the array structure of FIG. 1C discussed. 例如,假定存储单元阵列(100) 图示了存储体的存储块,并且被分成四个可被2比特CBA寻址的列块(101, 102, 103, 104),以执行如上所述的部分激活模式操作。 For example, assume that the memory cell array (100) illustrates a memory block of memory banks, and can be divided into four 2-bit addressing CBA column blocks (101, 102, 103, 104) to perform a portion as described above activation mode. 本领域熟练技术人员将容易地理解,也可以采用其它存储器构架实施本发明。 Those skilled in the art will readily be appreciated, the frame memory may be employed other embodiments of the present invention.

时钟信号CK和/CK参看经由用于同步操作的锁延迟环(DLL )和时钟緩冲电路(110)传送给半导体存储器件的每个功能块。 Clock signal CK and / CK via the reference for synchronization delay lock loop (DLL), and a clock buffer circuit (110) transmits to each function block of the semiconductor memory device. 命令译码器(120) 接收命令信号/CSh和FN (来自控制器和/或CPU),并对其译码以生成诸多命令,比如激活命令ACT、读命令/RD和写命令/WR。 A command decoder (120) receives a command signal / csh and FN (from controller and / or the CPU), and decodes it to generate a lot of commands, such as active command ACT, the read command / RD and a write command / WR. 激活命令ACT由不同电路如控制信号生成器(150)处理。 The active command ACT control signal generator (150) is processed by a different circuit. 命令译码器(120)所生成的读写命令由命令移位器(300)处理,它响应读命令/RD、写命令/WR和行地址比较器(200)所生成的页面模式标记信号(/PN—FLAG)生成到达控制信号生成器(150)的控制信号S一CMD。 A command decoder (120) generated by the write command shifter command (300) for, responsive to a read command / RD, a write command / WR and a row address comparator (200) the generated page mode flag signal ( / PN-FLAG) reaches the control signal generator generates (150) a control signal S CMD.

按照下面结合图5和图6的更详细说明,例如,在连续地将数据写入具有相同或不同列块(101、 102、 103、 104)的本发明的页面模式操作中, 考虑到写等待时间和一个或多个具有相同行地址的字线的延迟激活,命令移位器(300)将写命令/WR延迟预定时间TD1,从而确保具有不同行地址的在前激活字线的操作和预充电。 According to the more detailed description below in conjunction with FIGS. 5 and 6, for example, the data is written successively in the page mode of the present invention having the same or different column block (101, 102, 103, 104) operation in consideration of the write latency delay time or a plurality of word lines and having the same row address activation command shifter (300) a write command / WR predetermined time delay TD1, to ensure the operation and the pre-former having a different word line is activated a row address charge.

控制信号生成器(150)包括:激活控制信号生成单元(152),预充电控制信号生成单元(154),数据输入/输出控制信号生成单元(156)。 Control signal generator (150) comprising: activating a control signal generating unit (152), the precharge control signal generating means (154), the data input / output control signal generating means (156). 控制信号生成器(150)生成控制存储器存取操作的控制信号。 Control signal generator (150) generating a control signal for operating the memory access control. 具体地说,激活控制信号生成单元(152)输出控制信号给激活控制电路(192),以控制激活存储器存取操作。 Specifically, the activation control signal generating means (152) outputs a control signal to activate the control circuit (192) to control activation of the memory access operation. 预充电控制信号生成单元(154)向预充电控制电路(194)输出包括预充电启动信号PRECH一EN的控制信号,以控制预充电操作。 Precharge control signal generating unit (154) to the pre-charge control circuit (194) output comprises a precharge enable control signal EN is a signal PRECH to control the precharge operation. 数据输入/输出控制信号生成单元(156)向数据输入/输出控制电路(196)输出控制信号,以控制DQ緩存器(180)的输入/输出操作。 Data input / output control signal generating means (156) to the data input / output control circuit (196) outputs a control signal to control the DQ buffer (180) input / output operations.

多个地址信号(AO, Al, ...A14)和存储体地址信号(BAO和BA1 ) 例如从存储控制器或者CPU外部接收,它们经由地址緩存器(130 )和地址锁存器(140)分别输入到行译码器(160)和列译码器(170)。 A plurality of address signals (AO, Al, ... A14), and bank address signals (BAO and BAl) received from the memory controller, for example, or an external CPU, via which the address register (130) and an address latch (140) They are input to the row decoder (160) and a column decoder (170). 地址锁存器(140)在控制信号生成器(150)的控制下操作。 Address latch (140) operating under control of the control signal generator (150). 包括字线驱动器电路的行译码器(160 )对输入行地址X译码,并选择和激活存储单元阵列(100 ) 的对应字线(或整体字线)。 A word line driver circuit comprises a row decoder (160) decodes an input row address X, and select and activate memory cell array (100) of the corresponding word lines (word lines or whole). 列译码器(170)对输入列地址Y译码,并选择对应于地址Y的存储单元阵列(100)中一个列线,以输入和输出数据。 A column decoder (170) Y input column address decoder, Y address and select the corresponding memory cell array (100) in a column line to data input and output. 写入存储器的数据首先经过输入/输出插针DQ[O:m]输入,然后存入数据DQ 緩存器(180)。 First data into the memory via the input / output pin DQ [O: m] input and stored in the data DQ buffer (180). 从存储单元阵列(100)读出的数据首先被存入数据DQ缓存器(180),然后经过输入/输出插针DQ[0:m]输出。 From the memory cell array (100) is first read out data stored in the data DQ buffer (180), and then through the input / output pin DQ [0: m] output.

根据本发明, 一个从外部施加的行地址信号经由地址緩存器(130)输入到行地址比较器(200)和行译码器(160)。 According to the present invention, a row address signal applied from the outside via the address input buffer (130) to the row address comparator (200) and row decoder (160). 行地址比较器(200)比较目前输入的行地址(此后称之为"当前"行地址)与已存4诸的行地址(此后称之为"在前行地址,,)。这里,"当前,,行地址是指目前输入的行地址,"在前" 行地址是指在当前行地址之前输入的行地址。 Row address comparator (200) comparing the current input row address (hereinafter referred to as the "current" row address) and the row address stored in the various 4 (hereinafter referred to as "front row address ,,). Here, the" current ,, row address is the address of the current line of input, "previous" line address is the address entered row before the current row address.

当"当前,,和"在前,,行地址被确定为相同时,行地址比较器(200)生成一个页面模式标记信号(/PM—FLAG),该信号被输出到命令移位器(300 ) 和预充电控制电路(194)。 When the "current and ,," ,, previous row address is determined is the same, the row address comparator (200) generates a page mode flag signal (/ PM-FLAG) is, the command signal is output to the shifter (300 ) and a precharge control circuit (194). 页面模式标记信号(/PM一FLAG)触发"页面模式"存储器存取操作(用于按/WR或/RD指定,进行读操作或者写操作)。 Page mode flag signal (/ PM the FLAG a) trigger a "page mode" memory access operation (for press / WR or / RD specified, a read operation or write operation).

响应页面模式标记信号(/PM一FLAG),预充电控制电路(194)将阻断响应在前行地址而激活的字线的预充电操作。 Page mode in response to the flag signal (/ PM a FLAG), the precharge control circuit (194) in response to the block address of the preceding line precharge operation and the activated word line. 更具体地说,预充电控制电路(194)响应从行地址比较器(200)输出的页面模式标记信号/PM—FLAG 以及从预充电控制信号生成单元(154)输出的预充电启动信号PRECH_EN, 控制预充电操作。 More specifically, precharge control circuit (194) responsive to the output from the row address comparator (200) the page mode flag signal / PM-FLAG and the precharge control signal generating unit (154) precharge the output enable signal PRECH_EN, control precharge operation. 响应页面模式控制信号(/PM—FLAG),预充电控制电路(194)将中断预充电控制信号(/PRFCH-CS),即使预充电启动信号已经被启用,以便避免预充电操作。 In response to the page mode control signal (/ PM-FLAG), the precharge control circuit (194) interrupts the precharge control signal (/ PRFCH-CS), even if the precharge enable signal has been activated, so as to avoid the precharge operation. 因此,当在已激活列块(响应在前地址而激活)之间输入"当前,,行地址(与在前行地址相同)时,在前激活的列块的已激活字线的预充电操作被延迟到对应于下一个后续行地址的下一个预充电定时。显然相同的行地址可以被输入3次或者更多次,在此情况下将推迟预充电操作直至输入不同行地址。 Thus, when the "current ,, row address (the same as the previous row address) is activated when entering between column blocks (first address in response to activation), the first active word line activation block column precharge operation It is delayed until the next precharge timings corresponding to the next subsequent row address clearly the same row address can be entered three times or more, in which case the operation will be delayed until a pre-charge different input row address.

另一方面,当"当前,,地址不同于在前行地址(根据行地址比较器(200) 的比较结果确定)时,由在前行地址激活的在前列块的在前激活的字线, 在自数据的输入/输出起的一个预定时间后被自动预充电。 On the other hand, when the "current address is different from the preceding ,, a row address (row address is determined according to the comparison result of the comparator (200)), activated by the front row address of the preceding block forefront activated word line, automatic precharge after a predetermined time from the data input / output played.

因此,根据本发明,页面模式可以通过响应在前激活命令ACT,在开始预充电之前输入相同行地址来实现。 Thus, according to the present invention, the front page mode in response to the active command ACT, the same row address input before starting the precharge is achieved. 换言之,由于通过施加相同行地址扩展了已选择的第二列块的激活周期,因此有效地获得了页面模式功能, 从而可以向/从多个具有相同行地址的列连续输入/输出数据。 In other words, the row address is the same as the activation period of the second expansion block column selected by the application, and therefore efficiently obtained a page mode function, thereby to / continuous input / output data from a plurality of columns with the same row address.

不难理解,上述阻断预充电操作的处理是在页面模式操作期间读出数据或者向存储器写数据的时候执行的。 It will be appreciated, the above-described processing block precharge operation is performed during a page mode read data or write data to the memory operation time. 但是,除了阻断预充电操作之外, 图3的控制电路还在页面模式操作中当写数据到存储器时执行附加功能。 However, in addition to blocking than the precharge operation, the control circuit of Figure 3 also page mode operation when writing data to the memory perform additional functions. 例如,响应页面模式标记信号(/PM一FLAG),命令移位器(300)将写命令/WR有效延迟预定时间量TD1,以延迟控制信号S_CMD的输出,解决(account for)写等待和一个或多个具有相同行地址的字线的延迟激活,从而确保在前激活的具有不同行地址的字线的操作和预充电。 For example, the response page mode flag signal (/ PM a the FLAG), the shift command (300) the write command / WR predetermined amount of time effective to delay TD1, to the output delay control signal S_CMD solve (account for) and a write latency or activating a plurality of word line delay having the same row address, thereby ensuring that the former activated word lines having different row address and a precharge operation. 此外,延迟的信号S一CMD的输出造成预充电启动信号(PRECH一EN)被延迟。 Further, the output of a CMD signal S delayed start signal causes the precharge (a PRECH EN) is delayed. 此外,预充电控制电路(194)将页面模式标记信号(/PM一FLAG)延迟预定时间量TD2,以解决激活字线中的延迟TD1。 Further, the precharge control circuit (194) the page mode flag signal (/ PM the FLAG a) a predetermined amount of time delay TD2, TD1 to address the delay in the activation of the word line.

下面将参照图4和图5的示范性时序图更详细地说明本发明的示范性页面模式存储器存取操作(读写操作)。 FIG be described below with reference to an exemplary of the present invention, the page mode memory access operation (write operation) in more detail exemplary timing of FIG. 4 and FIG.

图4是说明本发明一个实施例的存储器存取操作的示范性时序图,该存储器存取操作被实施于具有部分激活构架的半导体存储器件。 FIG 4 is a timing diagram illustrating an exemplary embodiment of the memory access operation of the embodiment of the present invention, the memory access operation is a semiconductor memory device having implemented partially activated frame. 根据体地说,图4示出了图3的半导体存储器件的"页面模式,,操作。其中数据从存储器(100)的每个列块(101、 102、 103、 104)中具有相同行地址的存储单元中读出。在图4的实例中,假定脉沖串长度是四(4),并且假定借助四个激活命令ACT输入的行地址X1、 X2、 X3、 X4是相同的。 The body is to say, FIG. 4 shows a "page mode of the semiconductor memory device of FIG. 3 ,, operation wherein data having the same row address from the memory (100) for each column of blocks (101, 102, 103, 104) read from the storage unit. in the example of FIG. 4, it is assumed burst length is four (4), and it is assumed by four row address activation command ACT input X1, X2, X3, X4 are the same.

在图4的示范性"页面模式,,操作中,激活命令ACT和读命令/RD可以被无延迟地连续输入(与图2的方法相反),因为页面模式标记信号 In the exemplary FIG. 4 ",, page mode operation, active command ACT and a read command / RD can be continuously fed with no delay (as opposed to the method of FIG. 2), since the page mode flag signal

/PM—FLAG被激活,避免了在输入行地址(Xl、 X2、 X3、 X4)相同时执行行预充电操作。 / PM-FLAG is activated, while avoiding to perform row precharge operation input row address (Xl, X2, X3, X4) phase. 具体地说,在上文解释的图2的传统方法中,在激活命令ACT输入后的3个时钟自动执行行预充电操作。 Specifically, in the conventional method explained above in FIG. 2, three clock lines is performed automatically after the activation command ACT input precharge operation. 然而,在图4所示的示范性方法中,响应页面模式启动信号/PM—FLAG,将时钟周期C1、 C3和C5 中激活命令ACT输入后通常应当出现3个周期的行预充电操作(即,C4、 C6和C8中行预充电搡作)予以消除。 However, in the exemplary method shown in FIG. 4, page mode in response to the start signal / PM-FLAG, the clock cycle C1, C3 and C5, the active command ACT input should normally occur row 3 cycles precharge operation (i.e. , C4, C6 and C8 precharge shoving as BOC) be eliminated. 因此,在页面模式操作期间,具有相同行地址的字线被维持激活直至页面模式标记信号被禁止。 Thus, during a page mode operation, the word line having the same row address is maintained activated until the page mode flag signal is disabled.

下面结合图3和图4详细说明图4所示的示范性页面模式操作。 Below in conjunction with FIG exemplary page mode shown in FIG. 3 and FIG. 4 described in detail the operation. 在图4 中,在时钟周期Cl同步地输入激活命令ACT、行地址X1和列块选择地址CB1。 In FIG. 4, the input synchronization at clock cycle Cl active command ACT, row address X1 and the column address selection block CB1. 根据列块地址CB1选择第一列块(101 )(图3 ),以及响应输入行地址X1激活对应于输入行地址X1的子字线WL1 (整体字线的)。 Selecting a first column block CB1 column block address (101) (FIG. 3), and in response to activation of an input row address X1 corresponding to the input row address X1 sub word line WL1 (whole word line) in accordance with. 在时钟周期C2,输入读命令/RD和列地址Yl。 In the clock cycle C2, read command input / RD and column address Yl. 在响应时,对应于列地址Y1的列被选择,然后在3个时钟周期之后,从定位在已激活字线ML1和对应于地址Yl的已选择列的交集的存储单元开始读取数据。 In response, the column corresponding to the column address Y1 is selected, and then, after three clock cycles, data is read from the positioning start activated word line ML1 Yl address corresponding to the selected memory cell column intersection. 这里,由于脉冲串长度是四,因此响应时钟周期C5开始的读命令/RD,(从緩存器(180))连续输出四个数据比特DQ。 Here, since the burst length is four, so that the response clock cycle C5 read command start / RD, four data bits are continuously output the DQ (from the buffer (180)).

然后在时钟周期C3连续输入激活命令ACT、行地址X2和列块选择地址CB2。 Then the continuous input at clock cycle C3 activation command ACT, row address and column block select address X2 CB2. 第二列块响应地址CB2而激活。 The second column blocks CB2 response to the address is activated. 此外,第二列块的相应子字线WL2根据输入地址X2激活。 In addition, the respective sub-block word line WL2 second row activated according to input address X2. 特别是,参见图3,当前行地址X2经由地址緩存器(130)输入到行地址比较器(200)。 In particular, referring to Figure 3, the current row address input via the X2 address buffer (130) to the row address comparator (200). 行地址比较器(200)将当前输入行地址X2与在前行地址XI进行比较。 Row address comparator (200) the current input row address is compared with the preceding line X2 address XI. 由于行地址XI和X2相同,行地址比较器(200)生成页面模式标记信号/PM一FLAG,该标记信号具有阻止在前激活的子字线WL1预充电的"低,,逻辑电平。 如图4所示,页面模式标记信号造成,通常应当响应时钟周期C1中输入的ACT命令发生在时钟周期C4中的行预充电被取消。所以,子字线WL1的预充电(从而是相应的已激活整体字线)被推迟,并且在第二子字线WL2被激活的同时维持子字线WL1的激活状态。 Since the same row address XI and X2, the row address comparator (200) generating a page mode flag signal / PM a FLAG, the flag signal has a "low logic level prevents preceding ,, activated sub-word line WL1 precharging As As shown in FIG. 4, page mode flag signal resulting, in response to the line should generally be entered in the clock cycle C1 ACT command occurs in clock cycle C4 precharge is canceled. Therefore, the sub-word line WL1 precharging (thus have the corresponding activation of the entire word line) was delayed, and remain active sub word line WL1 in the second sub-word line WL2 is activated simultaneously.

然后,响应在时钟周期C4期间连续输入的读命令/RD和列地址Y2, 从位于已激活子字线WL2和对应于列地址Y2的已选择列线的交集上的存储单元开始读取数据。 Then, during a clock cycle in response to continuously input read command C4 / RD and column address Y2, located from the sub-word line WL2 is activated and Y2 corresponding to the column address of the selected memory cell on the column line intersection start reading. 由于脉冲串长度是四,所以响应在时钟周期C7开始的读命令/RD (从緩存器(180))连续输出四个数据比特DQ。 Since the burst length is four, so the clock cycle in response to a read command C7 start / RD four data bits are continuously output the DQ (from the buffer (180)).

此后,当在时钟周期C5输入第三激活命令ACT、当前行地址X3 (与在前行地址X2相同)以及列块选择地址CB3时,执行类似于上述操作的一个操作。 Thereafter, when the activation command ACT in the input of the third clock cycle C5, the current row address X3 (X2 are the same with the previous row address) and a column address selection block CB3, executing an operation similar to the above operation. 特别是,行地址比较器(200)确定当前地址X3和在前地址X2 相同,因此页面模式标记信号/PM一FLAG保持激活(逻辑"低,,电平)。因此, 通常应当响应时钟周期C3中第二输入ACT命令发生在时钟周期C6中的行预充电操作被取消。所以,子字线WL1和WL2 (从而是相应的已激活整体字线)的预充电被推迟,并且在激活第三子字线WL3的同时保持子字线WLi和WL2的激活状态。 In particular, the row address comparator (200) determines that the current and previous addresses to the same address X3 X2, so the page mode flag signal / PM a FLAG remains active (logic "low level ,,). Thus, it should generally response clock cycle C3 the second row input ACT command occurs at clock cycle C6 precharge operation is canceled. Therefore, the sub word lines WL1 and WL2 (so that the corresponding overall activated word line) was delayed precharge, activate the third and sub word line WL3 while maintaining the active state and the sub-word line WLi and WL2.

然后,响应在时钟周期C6期间连续输入的读命令/RD和列地址Y3, 从位于已激活子字线WL3和对应于列地址Y3的已选择列线的交集上的存储单元开始读取数据。 Then, during a clock cycle in response to continuously input read commands C6 / RD and column address Y3, located from the sub-word line WL3 has been activated and Y3 corresponding to the column address of the selected memory cell on the intersection of column lines start reading. 由于脉冲串长度是四,所以响应在时钟周期C9开始的读命令/RD (从缓存器(180))连续输出四个数据比特DQ。 Since the burst length is four, so the clock cycle in response to a read command starts C9 / RD four data bits are continuously output the DQ (from the buffer (180)).

同样,当在时钟周期C7输入第四激活命令ACT、当前行地址X4(与在前行地址X3相同)以及列块选择地址CB4时,行地址比较器(200)确定当前地址X4与在前地址X3相同,所以页面模式标记信号/PM—FLAG保持激活(逻辑"低,,电平)。所以,子字线WL1、 WL2和WL3 (从而是相应的已激活整体字线)的预充电被推迟,并且在激活子字线WL4的同时保持子字线WL1、 WL2和WL3的激活状态。 Similarly, when the input of the fourth clock cycle C7 active command ACT, the current row address X4 (the same as the previous row address X3) and a column address selection block CB4, the row address comparator (200) determines the previous address and current address X4 the same as X3, so the page mode flag signal / PM-fLAG remains active (logic "low level ,,). Therefore, the sub word lines WL1, WL2 and WL3 (so that the corresponding overall activated word line) is delayed precharge , and sub-word line WL4 is activated while maintaining the sub-word lines WL1, WL2 and WL3 of the active state.

然后,响应在时钟周期C8期间连续输入的读命令/RD和列地址Y4, 从位于已激活子字线WL4和对应于列地址Y4的已选择列线的交集上的存储单元开始读取数据。 Then, during a clock cycle in response to continuously input read commands C8 / RD and column address Y4, activated from the memory cells located in the sub-word line WL4 and Y4 corresponding to the column address of the selected column lines of intersection of the data reading starts. 由于脉沖串长度是四,所以响应在时钟周期Cll开始的读命令/RD (从緩存器(180))连续输出四个数据比特DQ。 Since the burst length is four, so the clock cycle in response to a read command Cll start / RD four data bits are continuously output the DQ (from the buffer (180)).

如图4所示,在时钟周期C9不输入激活命令。 4, the activation command is not input at clock cycle C9. 因此,行地址比较器(200 ) 确定当前行地址不同于在前行地址X4,因而禁止页面模式标记信号/PM一FLAG(例如,输出逻辑"高"电平)。 Thus, the row address comparator (200) determines that the current row address is different from the preceding row address X4, thus prohibiting the page mode flag signal / PM a FLAG (e.g., logic "high" level). 响应禁止页面模式标记信号,在时钟周期C10响应时钟周期C7的第四输入ACT命令将自动开始预充电操作。 Prohibition mode flag signal in response to the page, at clock cycle C10 clock cycle in response to a fourth input ACT command will automatically start the precharge operation C7. 在此情况下,预充电控制电路(194)(图3)将对所有的已激活字线WL1、 WL2、 WL3和WL4进行预充电路。 In this case, the precharge control circuit (194) (FIG. 3) all activated word lines WL1, WL2, WL3 and WL4 will be the precharge circuit.

所以,在数据从存储器读出的本发明的页面模式操作中,如果当前行地址和在前行地址被确定为相同,将启动页面模式标记信号/PM—FLAG以避免预充电操作,这将使在前激活的字线(响应在前行地址激活)保持已激活状态。 Therefore, in the page mode of the present invention, a data read out from the memory operation, if the current row address and the previous row address is determined to be the same, the page mode start flag signal / PM-FLAG to avoid the precharge operation, which will first activated word line (first row address in response to activation) remain activated. 因此,具有相同行地址的存储单元中的数据从相同列块或者不同列块中连续读出,从而在部分激活模式操作中增加存储器存取速度。 Accordingly, the data storage unit having the same row address is successively read out from the same column block or blocks of different columns, thereby increasing the speed of memory access operations in the active mode section. real

际上,如图4所示,数据比特DQ可以在连续的时钟周期C5-C12中连续输出。 On occasion, as shown in FIG. 4, data bits DQ continuous output in successive clock cycles of C5-C12.

这与参照图2解释的传统半导体存储器件的读取操作形成对照。 This is in contrast explained with reference to FIG. 2 a read operation of the conventional semiconductor memory device. 在传统操作中,即使当前和在前行地址相同,也必须在一个预定时间量tRC之后输入当前行地址,这样减低了以部分激活操作模式读取具有相同行地址的存储单元时的输入/输出速度。 In the conventional input operation, even with the same current and the previous row address, the row address must enter the current after a predetermined amount of time tRC, this reduces the read memory cell in the same row address portion when the active mode of operation / output speed. 实际上,如图2所示,即使连续输入相同行地址X,数据输出也不是连续的,而在图4中,当输入行地址相同时则连续输出数据。 In fact, as shown in FIG. 2, the same row address even if the continuous input X, the output data is not continuous, but in FIG. 4, when the input row address is continuously output the same data.

图5是说明本发明另一个实施例的存储器存取操作的示范性时序图, 该存储器存取操作被实施于具有部分激活构架的半导体存储器件。 FIG 5 is an exemplary timing diagram of another embodiment of the present invention the memory access operation, the memory access operation is implemented in the frame having a portion of a semiconductor memory device activation. 更具体地说,图5示出了数据被写入具有相同行地址的存储单元的"页面模式"。 More specifically, FIG. 5 shows the data are written into memory cells of the same row address "page mode." through

式操作中,除了在页面模式操作期间按上述方式消除行预充电之外,还将字线的激活和页面模式标记信号延迟一定的时间量,以解决与存储存取操作关联的写等待。 Type operation, except during page mode operation eliminates the outside line precharge, the word lines will be activated and page mode flag signal delayed by a certain amount of time, in order to solve the write operation associated with the store access wait the manner described above. 更具体地说,当收到写命令时,首先将对应于写命令的地址和数据存储到写緩存器中。 More specifically, when receiving a write command, the write command corresponding to the first address and the write data stored in the buffer. 此后,当收到用于相同存储体的后续写命令时,在对应于存入写緩存储中的地址的存储单元中写入写緩存器的数据。 Thereafter, when the writing command is received for the same memory bank, corresponding to the address stored in the write buffer storage units store the data to the write buffer. 因此,对应于借助写命令输入的行地址的字线不是迅速激活,而是在施加该后续命令之后激活。 Thus, by means of a word line corresponding to row address input of the write command is not activated quickly, but the application of the subsequent command after activation.

下面参照图3和图5更详细地解释图5所示的示范性页面模式操作。 Explained below with reference to FIGS. 3 and FIG. 5 in greater detail an exemplary operation of the page mode shown in FIG. 5. 在图5中,假定行地址X2、 X3和X4是相同的,但不同于行地址XI和X5, 以及借助长度为4的脉冲串执行脉沖串写操作。 In FIG. 5, the row address is assumed that X2, X3 and X4 are the same, but different from the row address XI and X5, and the length of a burst by burst 4 performs a write operation. 如同从存储读取数据的页面模式操作(如结合图4所述),与正常模式(非页面模式)期间施加激活命令ACT的时间间隔相比较,当执行写数据到存储器的页面模式操作时, 施加激活命令ACT的时间间隔被减少。 As the operation mode of reading data from a page (as in connection with FIG. 4), as compared to the active command ACT interval time is applied during the normal mode (non-page mode), when a data write operation to the page mode memory, active command ACT application time interval is reduced.

参见图5,激活命令ACT和行地址XI以及列块选择地址CB1借助时钟周期C1被同步地输入。 Referring to Figure 5, the active command ACT and the row address and the column block select address XI CB1 is input by means of clock cycle C1 in synchronism. 此后,在后续时钟周期C2输入写命令/WR和列地址Y1,并且在从列地址Yl起的三个时钟周期之后,连续输入四个数据比特Dl,以及在两个时钟周期期间将所述数据比特Dl存入位于DQ緩存器(180)的写緩存器(未示出)中。 Thereafter, in the subsequent clock cycle the write command C2 input / WR and column address Y1, and after the column address from the Yl of three clock cycles, four data bits Dl continuously inputted, and the data during two clock cycles bit Dl positioned into DQ buffer (180) of the write buffer (not shown).

在时钟周期C6中,收到另一个激活命令ACT,并输入行地址X2和列块选择地址CB2。 At clock cycle C6, the other received the active command ACT, and input row address and a column block select address X2 CB2. 行地址X2经由地址緩存器(130 )输入到行地址比较器(200),行地址比较器(200)将当前输入的行地址X2与在前行地址XI 进行比较。 X2 is inputted to the row address row address comparator (200) via an address buffer (130), a row address comparator (200) the current input row address of the preceding line address XI and X2 are compared. 由于行地址X1和X2不同,行地址比较器(200)将以"高,,逻辑电平保持页面模式标记信号/PM—FLAG。所以,页面模式标记信号保持被禁止,并且不触发页面模式操作。 Due to the different row addresses X1 and X2, the row address comparator (200) will be "high logic level holding ,, page mode flag signal / PM-FLAG. Therefore, the page mode flag signal remains disabled and does not trigger a page mode operation .

然后在后续时钟周期C7输入写命令/WR和列地址Y2。 Then in a subsequent clock cycle C7 write command input / WR and column address Y2. 所以,响应第二写命令/WR,并基于存入写緩存器中的行地址X1和列块选择地址CB1, 激活第一列块(101)的相应子字线WL1。 Therefore, in response to the second write command / WR, and the write row address buffer X1 and column address selection block CB1, activating the first column block (101) based on the corresponding sub-word line WL1 is stored. 对应于列地址Yl的列被选择, 以便在位于已激活子字线WL1和对应于列地址Y1的已选择列线的交集上的存储单元开始输入存储在写緩存器中的数据D1。 Yl column address corresponding to a column is selected to the activated memory cell corresponding to the sub-word line WL1 of the selected column address Y1 intersection of column lines and positioned at the beginning of input data D1 stored in the write buffer. 此外,由于页面模式操作还没有被激活,因此对在前激活的子字线WL1进行预充电。 Further, since the page mode operation has not been activated, so the first sub-word line WL1 is activated to precharge.

然后,在时钟周期C8中,收到另一个激活命令ACT,并输入行地址X3和列块选4奪地址CB3。 Then, at clock cycle C8, the other received the active command ACT, and input row address and a column block is selected from 4 X3 address wins CB3. 行地址比较器(200 )将当前输入的行地址X3与在前行地址X2进行比较。 Row address comparator (200) the current input row address is compared with the preceding line X3 address X2. 由于行地址X2和X3相同,行地址比较器(200 ) 生成具有逻辑"低,,电平的页面模式标记信号/PNLFLAG,从而激活页面模式操作。另一方面,借助一个TD2的延迟,输出页面模式标记信号/PM一FLAG, 以作为延迟的页面模式标记信号/D一PM,其原因在下文中解释。 The row address is the same as X2 and X3, the row address comparator (200) generates a logic "low level ,, page mode flag signal / PNLFLAG, thereby activating the page mode operation. On the other hand, the delay means, the output page of a TD2 mode flag signal / PM a fLAG, in which the reasons explained hereinafter as a page mode flag signal delay / D a PM.

在后续时钟周期C9,输入写命令/WR和列地址Y3。 In the subsequent clock cycle C9, write command input / WR and column address Y3. 所以,响应写命令/WR,并基于写緩存器中的行地址X2和列块选择地址CB2,激活第二列块(102)的相应子字线WL2。 Therefore, in response to the write command / WR, and X2 based on the write row address buffer and column blocks CB2 address selection, activates a second column block (102) of the respective sub-wordline WL2. 然而,为了充分保证在前激活的子字线WL1 的操作,将子字线WL2的激活延迟预定的第一延迟时间TD1,如图5所示。 However, in order to sufficiently guarantee the operation of the front activated sub word line WL1, the word line WL2 activator delays a predetermined first delay time TD1, as shown in FIG. 实际上,由于在页面模式操作中减少了施加激活命令ACT的时间间隔(与非页面模式操作比较),后续子字线WL2的激活被延迟,以确保在前激活的子字线WL1的操作和预充电。 Indeed, by reducing the time interval (compared to non-page mode operation) is applied to the active command ACT in the page mode operation, the subsequent activation of the sub word line WL2 is delayed to ensure that operations preceding the active sub-word line WL1 and precharged.

通常,子字线WL2应当在写命令/WR和列地址Y3输入(时钟周期C9 ) 后激活(如在时钟周期C7输入列地址Y2后的字线WL)。 Typically, the sub-word line WL2 should write command / WR and activation (e.g., C7 input clock cycles after the column address Y2 word line WL) after the column address Y3 input (clock period C9). 然而,由于在页面模式操作期间ACT命令以较短时间间隔接收,因此如果在此时间激活子字线WL2而不延迟,则将不能充分保证子字线WL1的操作时间。 However, since the interval to the reception in a short time during a page mode operation command ACT, so if activated sub word line WL2 at this time without delay, it will not sufficiently guarantee the operation time sub word line WL1. 因此,在图5的示范性实施例中,子字线WL2的激活最好在写命令/WR和列地址Y3输入后延迟约三个时钟周期。 Thus, in the exemplary embodiment of FIG. 5, the sub-word line WL2 is preferably activated in the write command / WR and column address Y3 delay of about three clock cycles after input. 在激活子字线WL2之后,将緩沖的数据D2从与子字线WL2和对应于Y2的已选择列线的交集相对应的存储位置开始写入存储器。 After the activation of the sub word line WL2, the buffered data D2 from the memory and starts writing the sub-word line WL2 and the selected column line corresponding to the intersection of Y2 corresponding to the storage location.

此外,由于子字线WL2的激活被延迟,因此还将已启动的页面模式标记信号/P]VLFLAG (推迟已激活子字线WL2的操作和推迟用于页面模式操作的后续激活的子字线(具有相同行地址))延迟预定时间TD2。 Further, due to the activation of the sub word line WL2 is delayed, the page mode will be started flag signal / P] VLFLAG (sub word line is activated delayed action and subsequent activation of deferred page mode operation for the sub-word line WL2 (having the same row address)) a predetermined time delay TD2. 更具体地说,在数据被写入存储器的页面模式操作中预充电控制电路(194)响应延迟的页面模式标记信号/D一PM控制子字线的预充电,该页面模式标记信号/D_PM通过将页面模式标记信号/PM一FLAG延迟预定数量的时钟周期,即图5所示的第二延迟时间TD2而生成。 More specifically, data is written to memory in the page mode operation of the precharge control circuit (194) page mode flag signal in response to the delayed / D precharge a PM control sub-word lines, the page mode flag signal / D_PM by the page mode flag signal / PM fLAG clock cycle delay a predetermined amount, i.e., second delay time TD2 shown in FIG. 5 is generated. 因此,子字线WL2的有充电被推迟并保持子字线WL2激活。 Thus, the sub-word line WL2 is delayed charging of the sub-word line WL2 and held activated.

接着,在时钟周期C10,输入激活命令ACT和行地址X4以及列块选择地址CB4,并且执行类似于上述操作的操作,因为行地址X4与在前行地址X3相同。 Next, at clock cycle C10, enter the activation command ACT and the row address and the column block select address X4 CB4, and performs an operation similar to the above operation, since the row address and the same row address X4 front X3.

在时钟周期C12不施加激活命令ACT。 Is not applied at clock cycle C12 active command ACT. 因此,行地址比较器(200)确定当前行地址不同于在前行地址X4,并且在响应时禁止页面模式标记信号/PM一FLAG(例如,生成具有逻辑"高"电平的页面模式标记信号)。 Thus, the row address comparator (200) determines that the current row address is different from the preceding row address X4, page mode and disable flag signal / PM in response to a FLAG (e.g., generates a logic "high" level page mode flag signal ). 因此, 响应具有逻辑"高,,电平的延迟页面模式标记信号/D—PM,有充电控制电路(194)在时钟周期C18开始有充电操作,以便同时对已激活子字线WL2、 WL3和WL4预充电。 Thus, the response delay page mode flag signal / D-PM having a logic "high ,, level, a charging control circuit (194) C18 starts charging operation clock cycle, simultaneously to the activated sub-word lines WL2, WL3, and WL4 precharge.

因此,图5的示范性方法能够使数据在页面模式操作中写入存储器中。 Thus, the exemplary method of FIG. 5 enables the data into the memory in a page mode operation. 如上所述,由于写操作是在输入后续写命令后执行的,因此页面模式操作造成后续子字线延迟第一延迟时间TD1,以保证在前激活的子字线的操作时间。 As described above, since the write operation is performed in the subsequent write command is input, thus resulting in subsequent sub-page mode operation of the word line delay first delay time TD1, to ensure that the operating time preceding the activation of the sub word line. 由于子字线的激活被延迟,因此在页面模式中,阻止已激活子字线的预充电操作的页面模式标记信号也被延迟。 Due to the activation of the sub word line is delayed, so the page mode, to prevent the activated page precharge operation mode flag of the sub-word line signal is also delayed. 需要理解的是,在页面模式操作中,当在前行地址与当前行地址相同时,通过保持对应于相同行地址的在前激活的字线的状态,就可以将数据连续写入不同列块或相同列块中具有相同行地址的存储单元中。 Is to be understood that, in the page mode operation, the first row address and the current row address is the same, the state remains the same row address corresponding to the activated word line to the front, the data can be continuously written in different column blocks when or the same column of the memory cell blocks having the same row address.

图6是说明本发明实施例的命令移位器(300 )的电路图,该电路最好实施于图3的器件。 FIG 6 is a circuit diagram shifter command (300) in an embodiment of the present invention, the circuit is preferably implemented in the device of FIG. 通常,在数据被写入存储器的页面模式操作中,命令移位器(300 )将写命令/WR延迟预定时间,以便将对应的字线延迟TD1 (如图5所示)。 Typically, data is written in the page memory mode operation, the shifter command (300) the write command / WR predetermined time delay so as to delay TD1 corresponding word line (shown in FIG. 5). 在示范性实施例中,写命令/WR仅仅在页面模式标记信号/PM—FLAG被启动时(逻辑低)才将被延迟。 In an exemplary embodiment, the write command / WR will be delayed until just when the page mode flag signal / PM-FLAG is activated (logic low).

参见图6,命令移位器(300)包括时钟移位器(310)、 NPR门(321、 322、 323 )和反相器(331、 332、 333 )。 Referring to Figure 6, the shifter command (300) includes a clock shifter (310), NPR door (321, 322, 323) and an inverter (331, 332, 333). 假定页面模式标记信号/PM—FLAG、 写命令/WR和读命令/RD是在逻辑"低"电平激活的信号。 Assumes a page mode flag signal / PM-FLAG, a write command / WR and read command / RD is a logic "low" level of the activating signal.

NOR门(321)接收作为输入的写命令/WR和页面模式标记信号/PM_FLAG,并对输入信号执行逻辑NOR操作。 NOR gate (321) receives as input a write command / WR signal and page mode flag / PM_FLAG, the input signal and performs a logical NOR operation. NOR门信号(322)接收作为输入的写命令/WR和反相的页面模式标记信号/PM—FLAG (由反相器(331)反相),并对输入信号执行NOR操作。 Signal of the NOR gate (322) receives as input a write command / WR mode flag and the inverted page signal / PM-FLAG (an inverter (331) inverting), the input signal and performs a NOR operation. 时钟移位器(310)将NOR 门(321 )的输出信号延迟第一延迟时间TD1 (图5 )。 The shift clock (310) to the NOR gate (321) output signal of the first delay time TD1 (FIG. 5). NOR门(323 )和反相器(333 )对时钟移位器(310)、 NOR门(322)和反相器(332 )输出的信号有效地执行逻辑"OR",这种"OR"操作的结果作为一个命令S_CMD输出。 NOR gate (323) and an inverter (333), the signal output from the NOR gate (322) and an inverter (332) effectively performing a logical "OR" of clock shifter (310), this "OR" operation as a result of the command output S_CMD.

对于图6的命令移位器(300),当启动页面模式标记信号/PM—FLAG 和写命令信号/WR (即,逻幹'低,,电平)以及禁止(逻幹'高,,电平)读命令信号/RD时,NOR门(322)和反相器(332)的输出将是逻辑低,而NOR 门(321)的输出将是逻幹'高"。然而,NOR门(321)的输出被延迟了预定时间TD1,这将逻辑"高"电平的S—CMD信号的生成延迟预定时间TD1. 因此,实际上,写命令/WR被时钟移位器(310)延迟第一延迟时间TDl。 6 to FIG shifter command (300), the page mode flag when the start signal / PM-FLAG and the write command signal / WR (i.e., logic dry ',, a low level) and the prohibition (dry logic' high electrical ,, when level) read command signal / RD, output of the NOR gate (322) and an inverter (332) will be a logic low, and NOR gate (321) output will be logic dry "high." However, the NOR gate (321 ) output is delayed by a predetermined time TD1, which generates a logic "high" level of the S-CMD signal a predetermined delay time TD1. Thus, in practice, a write command / WR is (310) delaying the first clock shifter delay time TDl.

当页面模式标记信号/PM—FLAG和读命令信号/RD都被禁止(逻辑高) 时,以及写命令信号/WR被启动(逻辑低)时,NOR门(321)和反相器(332 )的输出将是逻辑低,而NOR门(322)的输出将是逻辑高,并且将生成具有逻辑高电平的非延迟SJ^MD信号。 When the page mode flag signal / PM-FLAG and read command signals / RD are disabled (logic high), and the write command signal / WR is activated (logic low), the NOR gate (321) and an inverter (332) the output will be a logic low, and NOR gate (322) outputs a logic high, and the high logic level to generate a non-delayed signal SJ ^ MD. 因此,实际上,当以非页面模式操作时非延迟写命令/WR。 Therefore, in practice, when operating in the non-delayed non-page mode write command / WR.

另一方面,在读命令/RD被启动时的读操作中,具有逻辑"高,,电平的非延迟S一CMD信号将被输出,而不考虑页面模式标记信号/PM—FLAG的逻辑电平(即,不考虑存储器正在以页面模式操作还是以非页面模式操作)。 CMD a non-delayed signal S on the other hand, a read operation is started when the read command / RD having a logic "high level ,, to be output, regardless of the page mode flag signal / PM-FLAG logic level (i.e., without regard to the memory is operating in a non-page mode or a page mode operation).

应当理解的是,时钟移位器可以包括任何延迟信号的适当电路。 It will be appreciated that the clock shifter may comprise any suitable circuitry delayed signal. 例如, 时钟移位器可以包括多个串联连接的反相器。 For example, the shift clock may include a plurality of inverters connected in series. 作为选择,时钟移位器包括多个串联接连的触发器。 Alternatively, a plurality of clock shifter comprises a series of flip-flops connected in series. 本领域熟练技术人员可以容易地想到实现时钟移位电^4々其它方法。 Those skilled in the art can readily envision other methods to realize the clock shift circuit 4々 ^.

图7是说明本发明实施例的行地址比较器(200)电路图,该电路最好 7 is a row address comparator embodiment of the present invention (200) a circuit diagram, the circuit is preferably

实施于图3的器件。 3 embodiment of the device in FIG. 行地址比较器(200)包括三个开关(211、 212、 213), 两个锁存器(221和222),以及一个比较器(230)。 Row address comparator (200) comprises three switches (211, 212, 213), two latches (221 and 222), and a comparator (230). 第一、第二和第三开关(211、 212、 213)的每个包括传输门(230)和反相器,它们响应时钟/ 激活信号CLK+ACT CMD导通/截止。 First, second and third switches (211, 212, 213) each include a transmission gate (230) and an inverter, which in response to the clock / CLK + ACT CMD activation signal is turned on / off. 时钟/激活信号CLK+ACT CMD是响应时钟周期CLK信号和激活命令ACT信号生成的信号。 Clock / CLK + ACT CMD activation signal in response to the clock signal CLK cycle and activation signal ACT command signal generated. 更具体地说,第一和第三开关(211和213 )响应具有逻辑"高"电平的时钟/激活信号CLK+ACK CMD导通,而第二开关(212)响应具有逻辑"低"电平的时钟/激活信号CLK+ACT CMD导通,对此本领域熟练技术人员将容易理解。 More specifically, the first and third switches (211 and 213) responsive to a clock having a logic "high" level of the / CLK + ACK CMD activation signal is turned on and the second switch (212) having a response to a logic "low" level clock / CLK + ACT CMD activation signal is turned on, this skilled in the art will readily understand. 第一和第二锁存器(221和222)的每个包括一对反相器。 Each of the first and second latches (221 and 222) comprises a pair of inverters.

经由地址緩存器(130)输入的行地址XADDR作为行地址XADDR1 输出到比较器(230)的一端。 Row address XADDR inputted via an address buffer (130) to the end of the comparator (230) as the row address XADDR1. 同时,由于第一开关(211 )根据具有逻辑"高,, 电平的时钟/激活信号CLK+ACT CMD导通,因此行地址XADDR被输入到第一锁存器(221 )。输入到第一锁存器的行地址响应具有逻辑"低"电平的时钟/激活信号CLK+ACTCMD被输入到第二锁存器(222)。然后,响应具有逻辑"高"电平的时钟/激活信号CLK+ACTCMD,将输入到锁存器(222)的行地址输入到比较器(230 )的另一端。在这里,直接输入到比较器(230) 一端的行地址是"当前,,行地址XADDRl,经由锁存器输入到比较器(230) 另一端的行地址是"在前,,行地址XADDR2。如上所述,"当前"行地址XADDR1是目前输入的行地址,而"在前"行地址XADDR2是先前输入的行地址。 Meanwhile, since the first switch (211) in accordance with a clock having a logic "high level ,, / CLK + ACT CMD activation signal is turned on, the row address XADDR is inputted to the first latch (221) input to the first row address latch in response to a clock having a logic "low" level of the / CLK + ACTCMD activation signal is input to the second latch (222). then, in response to a clock having a logic "high" level / activation signal CLK + ACTCMD, to the other input terminal of the row address latch (222) is input to a comparator (230). here, the input directly to a comparator (230) at one end of the row address is "current row address ,, XADDRl, latch input to the comparator via (230) the other end of the row address is "first row address ,, XADDR2. As described above, the" current "row address XADDR1 current input row address, and a" previous "row address XADDR2 row address previously entered.

比较器(230)将当前行地址与在前行地址XADDR2进行比较,当行地址XADDR1和XADDR2相同时启动页面模式标记信号/PM—FLAG(输出逻辑"低"电平),当行地址XADDR1和XADDR2不同时禁止页面模式标记信号/PM—FLAG (输出逻辑"高"电平)。 A comparator (230) the current row address is compared with the previous row address XADDR2, when the row address XADDR1 and XADDR2 same starting page mode flag signal / PM-FLAG (logic "low" level), when the row address XADDR1 and XADDR2 not page mode flag while prohibiting signal / PM-fLAG (logic "high" level).

图8是本发明实施例的预充电控制电路的电路图,它最好实施于图3 的器件。 FIG 8 is a circuit diagram of a precharge device control circuit according to the present embodiment of the invention, which is preferably implemented in FIG. 3. 通常,预充电控制电路(194)接收作为输入的来自预充电控制信号生成单元(154)预充电启动信号(PRECH_EN)、从行地址比较器(200) 输出的页面模式标记信号(/PM一FLAG)、读命令/RD和写命令/WR信号。 Typically, the pre-charge control circuit (194) receives as input from the precharge control signal generating unit (154) precharge enable signal (PRECH_EN), page mode flag signal output from the row address comparator (200) (/ PM a FLAG ), a read command / RD and write command / WR signal. 在数据写入存储器的"页面模式"操作中,预充电控制电路(194)将页面模式标记信号(/PM—FLAG)延迟预定时间TD2 (即,生成延迟信号/D—PM) 以解决字线激活中的延迟(TD1)(如图5所示)。 Data is written in the memory "page mode" operation, a precharge control circuit (194) the page mode flag signal (/ PM-FLAG) a predetermined delay time TD2 (i.e., generates a delay signal / D-PM) to resolve the word line activation delay (TD1) (Figure 5). 在示范性实施例中,在数据从存储器读出的页面模式操作时不延迟页面模式标记信号(/PM一FLAG )。 In an exemplary embodiment, the page mode flag without delay signal (/ PM the FLAG a) the page mode data read out from the memory operation.

参见图8,预充电控制电路(194)包括:NOR门(411和412),反相器(421和422), NAND门(431),时钟移位器(310)和预充电控制单元(440)。 Referring to Figure 8, the precharge control circuit (194) comprising: NOR gates (411 and 412), an inverter (421 and 422), NAND gate (431), the shift clock (310) and a precharge control unit (440 ). NOR门(411)和反相器(421)有效地执行页面模式标记信号/PM—FLAG和写命令信号/WR的逻辑"OR"操作。 NOR gate (411) and an inverter (421) to perform page mode flag valid signal / PM-FLAG and the write command signal / WR logic "OR" operation. 时钟移位器(310 )将反相器(421 )的输出移位第二延迟时间TD2 (图5)。 The shift clock (310) to the inverter (421) of the second delay time TD2 outputs of shift (FIG. 5). 此外,NOR门(412)和反相器(422)有效地执行页面模式标记信号/PM一FLAG和读命令信号/RD 的逻辑OR操作。 Additionally, NOR gate (412) and an inverter (422) to perform page mode flag valid signal / PM read command signal and a FLAG / RD logic OR operation. 反相器(422)的输出不延迟地输入到NAND门(431)。 Output of the inverter (422) is not input to the NAND gate delay (431).

在数据被写入存储器的页面模式操作中,页面模式标记/PM—FLAG和写命令信号/WR都被启动(逻辑低),读命令/RD是逻辑"高"。 Data is written to memory in a page mode operation, the page mode flag / PM-FLAG and the write command signal / WR are activated (logic low), a read command / RD is a logic "high." 因此,反相器(422)的输出被时钟移位器(310)延迟了第二延迟时间TD2。 Thus, the output of the inverter (422) is a clock shifter (310) delayed by a second delay time TD2. 因此, 页面模式标记信号/PM—FLAG (逻辑低启动)实际上被延迟TD2 (延迟的页面模式信号/D从时钟移位器(310)输出)。 Thus, the page mode flag signal / PM-FLAG (logic low to start) is actually delayed TD2 (delayed page mode signal / D clock output from the shifter (310)).

在数据从存储器读出的页面模式操作中,页面模式标记信号/PM一FLAG 和读命令信号/RD都被启动(逻辑低),而写命令信号被禁止(逻辑高)。 In the data read out from the page mode operation of the memory, the page mode flag signal / PM read command signal and a FLAG / RD are activated (logic low), and the write command signal is disabled (logic high). 所以,反相器(421)的输出将是逻辑"高"电平,反相器(422)的输出将是逻幹'低,,电平。 Therefore, the output of the inverter (421) the output will be a logic "high" level, the inverter (422) will be a logic dry ',, a low level. 因此,实际上在数据从存储器读出的页面模式操作中不延迟页面模式标记信号/PM一FLAG。 Thus, the page mode flag is not actually delayed signal / PM FLAG page mode in a data read operation from the memory.

NAND门(431 )执行预充电启动信号PRECH—EN和时钟移位器(310 ) 和反相器(422)的输出信号的逻辑NAND操作,并输出预充电控制信号/PRECH—CS。 NAND gate (431) performing a logical NAND operation of the output precharge signal PRECH-EN enable signal and the clock shifter (310) and an inverter (422), and outputs the precharge control signal / PRECH-CS. 预充电启动信号PRECH—EN是从激活命令ACT输入开始经历一个预定时间量后自动启动的信号(从预充电控制信号生成单元(154) 输出逻辑"高,,电平)。例如,在参照图2讨论的传统方法中,是在自施加激活命令ACT时的时钟周期起的三个(3)周期后自动启动行预充电。然而, 在页面模式标记/PM—FLAG被启动(逻辑低电平)时的本发明写数据到存储器的页面模式操作中,则是在根据延迟命令S—CMD延迟第一延迟时间TD1后,输出预充电启动信号PRECH—EN,如图6所示。在传统半导体存储器件中,预充电在预充电启动信号PRECH+EN被启用时自动发生。 Precharge enable signal PRECH-EN is input from the activation command ACT after the start signal is subjected to a predetermined amount of time to start automatically (from the precharge control signal generating unit (154) outputs a logic "high level,,). For example, with reference to FIG. 2 discussed conventional method, is applied from the clock cycle when the active command ACT from three (3) to start precharging period automatically. However, in the page mode flag / PM-fLAG is activated (low logic level when the present invention) writing data to the memory page mode operation, the delay in the first delay time TD1 the delayed command S-CMD, the output of the precharge enable signal PRECH-EN, shown in Figure 6. in the conventional semiconductor memory devices, the precharge starts automatically occurs when the precharge signal PRECH + EN is enabled.

从NAND门(431)输出的预充电控制信号/PRECH一CS被输出给预充电控制单元(440 )。 From the pre-charging the NAND gate (431) output from the control signal / PRECH CS is output to a precharge control means (440). 预充电控制单元(440 )仅仅在预充电控制信号/PRECH_CS被启动(具有逻辑"低"电平)时才将执行预充电操作。 The precharge control means (440) only in the precharge control signal / PRECH_CS is activated (having a logic "low" level) when the precharge operation is performed. 因此, 当时钟移位器(310)或者反相器(422)的输出为逻辑"低"时,预充电控制信号/PRECH—CS将被禁止(逻辑"高"电平)。 Thus, when the output of clock shifter (310) or the inverter (422) is a logic "low" precharge control signal / PRECH-CS will be disabled (logic "high" level).

参见图9, 一个示范性时序图分别描述了在本发明的页面模式操作期间,图7和图8的行地址比较电路(200)和预充电控制电路(194)的操作模式。 Referring to Figure 9, an exemplary timing diagram depict during page mode operation of the present invention, the row address FIGS. 7 and 8 the operation mode of the comparison circuit (200) and a precharge control circuit (194) is. 在图9的实例中,假定激活命令ACT在每个奇数时中周期Cl、 C3、 C5、 C7和C9被激活。 In the example of FIG. 9, it is assumed active command ACT is activated in cycle Cl, C3, C5, C7 and C9 each odd number. 此外,还假定借助头三个激活命令ACT输入行地址XADDR "00000",并且借助至少两个激活或命令ACT llr入行地址XADDR "FFFF,,。 Further assume that the first means of three active command ACT input row address XADDR "00000", and by means of at least two active command ACT LLR or the row address XADDR "FFFF ,,.

响应式中CLK和激活命令ACT,以一个预定时间量启动(逻辑高)时钟/激活信号CLK+ACT CMD,如图9所示。 And wherein in response to CLK active command ACT, a predetermined amount of time to start (logic high) clock / activation signal CLK + ACT CMD, as shown in FIG. 所以,在该示范性时序图中, 每两个时钟周期启动(逻辑低电平)时钟/激活信号CLK+ACTCMD。 Therefore, in this exemplary timing diagram, the start every two clock cycles (logical low level) clock / activation signal CLK + ACTCMD. 当激活命令ACT被激活时(逻辑低电平),行地址信号XADDR被输入。 When the active command ACT is activated (low logic level), the row address signal is input XADDR. 直接输入到比较器(230) —端的第一地址XADDR1与外部(例如,来自存储器控制器)施加的行地址相同。 It is directly input to the comparator (230) - a first outer end and the XADDR1 address (e.g., from the memory controller) applied to the same row address. 实际上,在接收行地址XADDR的时间与实际输入XADDR1到比较器(230)端口时的时间之间可以有略微延迟。 In fact, at the time of receiving the row address XADDR XADDR1 actual input to a comparator (230) may have a slight delay between the time when the port.

在时钟周期Cl,第一输入行地址XADDR1 "0000,,与第一激活命令ACT 被输入到比较器(230)的一端。当响应第一启动命令ACT在H1代表的时段启动(逻辑高)时钟/激活信号CLK+ACT CMD时,第一和第三开关(211 和213)导通。所以,存储在第二锁存器(222)中的地址XXXX被输入到比较器(230 )的另一端,作为在前地址XADDR2。在这里,第二锁存器(222 ) 中存储的地址是一个预定的初始地址XXXX。与此同时,当前行地址XADDR1"0000"被输入到第一锁存器(221 )。 In clock cycle Cl, a first input row address XADDR1 "0000 ,, the first active command ACT is inputted to one terminal of the comparator (230). When the response to the first start command to start in the period represented by the ACT H1 (logic high) clock / CLK + when the activation signal ACT CMD, first and third switches (211 and 213) are turned on. Therefore, XXXX address stored in the second latch (222) is input to a comparator (230) and the other end as previous address XADDR2. here, the second address latch (222) is stored in a predetermined initial address XXXX. at the same time, the current row address XADDR1 "0000" is input to the first latch ( 221).

当时钟/激活信号CLK+ACT CMD在Ll代表的时段期间被禁止(逻辑低电平)时,第一和第三开关(211和213)被截止以及第二开关(212) 被导通。 When the clock / CLK + ACT CMD activation signal is disabled (logic low level) during the period represented by Ll, the first and third switches (211 and 213) are turned off and a second switch (212) is turned on. 因此,存入在第一锁存器(221)中的第一输入行地址0000被输入到第二锁存器(222)。 Accordingly, the first input row address stored in the first latch (221) 0000 is input to the second latch (222).

然后,在时钟周期C3输入第二激活命令ACT和第二输入行地址XADDR "0000"。 Then, at cycle C3 of the clock input of the second active command ACT and row address second input XADDR "0000". 当响应第二激活命令ACT启动(逻辑高)时钟/激活信号CLK+ACTCMD时,第一和第三开关(211和213 )被导通。 When the response to the second active command ACT is activated (logic high) clock / activation signal CLK + ACTCMD, first and third switches (211 and 213) are turned on. 这样,第二锁存器(222)中存储的第一输入行地址0000被输入到比较器(230),以作为在前地址XADDR2。 Thus, the first input of the second row address latch (222) is stored in 0000 is input to a comparator (230), as the preceding address XADDR2.

在这里,由于当前地址XADDR1 (借助第二激活命令ACT输入)和在前地址XADDR2 (借助第一激活命令ACT输入)同样为"0000",因此比较器(230)输出低电平的页面模式标记/PM一FLAG。 Here, since the current address XADDR1 (by means of a second active command ACT input) and the preceding address XADDR2 (by means of a first active command ACT input) the same as the "0000", the comparator (230) outputs a low-level page mode flag / PM a FLAG.

当时钟/激活信号CLK+ACT CMD在L2代表的时段被禁止(逻辑低电平)时,第二开关(212)被导通,所以第一锁存器(221)中存储的第二输入行地址0000被输入到第二锁存器(222 )。 When the clock / CLK + ACT CMD activation signal is disabled (logic low level) in the period represented by L2, a second switch (212) is turned on, the first latch (221) storing a second input line address 0000 is input to the second latch (222). 结果,第一和第二锁存器(221 和222 )存储借助第二激活命令AXT输入的在前行地址,并且在输入的三激活命令ACT时将在前地址XADDR2供应给比较器(230 )。 As a result, the first and second latches (221 and 222) a second storage means of the front row address AXT active command input, and supplies at three active command ACT input to the comparator XADDR2 previous address (230) .

然后,比较器(230 )将在前地址(借助第二激活命令ACT输入)与当前地址XADDR1(借助第三激活命令ACT输入的)进行比较。 Then, the comparator (230) the previous address (by means of a second active command ACT input) and the current address XADDR1 (by means of the third active command ACT input) is compared. 由于"0000" 的在前输入行地址与"0000"的第三(当前)输入行地址相同,因此页面模式标记/PM一FLAG保持启动(保持逻辑"低电平")。 Since the "0000" address input line of the first third (current) input the same row address and "0000", so the page mode flag / PM FLAG holding a boot (remains a logic "low").

然而,由于"FFFF,的第四输入行地址(借助时钟周期C7中激活命令输入)不同于"OOOO,,的第三输入行地址(借助时钟)(在时钟周期C5中借助激活命令输入),因此页面模式标记/PM—FLAG被禁止(逻辑高电平)。 However, due to "FFFF, a fourth input row address (clock cycle by means of the activation command input C7) is different from" OOOO ,, third input row address (clock means) (by means of the activation command input clock cycle C5), Thus the page mode flag / PM-fLAG is disabled (logic high). 并且由于第五输入行地址"FFFF,(借助时钟周期C9中激活命令输入)和"FFFF,的在前输入行地址(借助时钟周期C7中激活命令输入)相同,因此页面模式标记/PM—FLAG被再次启动(逻辑低电平)。 And as a fifth input row address "FFFF, (C9 clock cycle activated by command input) and" FFFF, the front row address input (clock cycle C7 activated by the command input), and thus the page mode flag / PM-FLAG It is activated (low logic level) again.

此外,如图9所示,预充电启动信号PRECH—EN在从每个激活命令ACT 输入开始的三个时钟周期之后被启动预定时间量。 Further, as shown in FIG. 9, the precharge enable signal PRECH-EN is started a predetermined amount of time after the start command ACT three clock cycles from the input of each activation. 这样,在图9的实例中, 预充电启动信号PRECH—EN响应第一至第三激活命令ACT被启动三次。 Thus, in the example of FIG. 9, the precharge enable signal PRECH-EN response to the first to third active command ACT is activated three times. 然而,当第一至第三预充电启动信号PRECH_EN被启动时(逻辑"高,,电平) 时,页面模式标记信号/PM—FLAG被启动(逻辑"低"电平),因此预充电控制信号/PRCH一CS被禁止(逻辑"高"电平)。由于预充电控制信号/PRCH一CS 被禁止,因此预充电控制电路(194)阻止预充电操作。 However, when the first to third pre-charge start signal PRECH_EN is activated (logic ",, high level), page mode flag signal / PM-FLAG is enabled (logic" low "level), so the pre-charge control signal / PRCH a CS is disabled (logic "high" level). Since the precharge control signal / PRCH a CS is disabled, so the pre-charge control circuit (194) to prevent the precharge operation.

当第三与充电启动信号PRECH—EN被启动(逻辑"高,,电平)时,页面模式标记/PM一FLAG被禁止(逻辑"高"电平),因此预充电控制信号/PRCH—CS被启动(逻辑"低"电平)。所以,预充电控制电路(194)启动预充电操作。总之,在在前行地址和当前行地址相同的本发明的存储器存取操作中, 预充电操作被阻止,从而增加了数据被写入/读出具有相同行地址的存储单元时的存储器存取速度。有利的是,这里所述的示范性电路和方法提高了具有部分激活结构的半导体存储器件的页面模式操作的效率。上述的电路和方法能够对相同行地址的连续读出或写入操作增加存储器存取速度。 When the third and the charge enable signal PRECH-EN is enabled (logic ",, high level), the page mode flag / PM a FLAG is disabled (logic" high "level), so the precharge control signal / PRCH-CS is enabled (logic "low" level). Therefore, the precharge control circuit (194) starts the precharge operation. in short, the memory access operation of the current row address and the previous invention of the same row address precharge operation It is prevented, thereby increasing memory access speed when data is written / read memory cells having the same row address. advantageously, the exemplary circuits and methods described herein improve the semiconductor memory device having a structure partially activated efficiency page mode operation above circuits and methods capable of a continuous read or write the same row address operation increases the memory access speed.

图IO是说明可以实施本发明的存储器系统的示意性方框图。 FIG IO is a schematic block diagram of a memory system according to the present invention may be implemented. 存储器系 Memory system

统(1000)包括:CPU (1001),存储器控制器(1002)和多个存储器模块(1003 )。 System (1000) comprising: CPU (1001), the memory controller (1002) and a plurality of memory modules (1003). CPU可以是处理器单元(MPU)或者网络处理单元(NPU)等。 CPU may be a processor unit (MPU) or the network processing unit (the NPU) and the like. 每个存储器模块(1003 )包括多个半导体存储器件如FCRAMS。 Each memory module (1003) comprises a plurality of semiconductor memory devices such as FCRAMS. CPU( 1001 ) 通过第一总线系统(Bl)(例如,控制总线,数据总线,地址总线)连接到存储器控制器,存储器控制器(1002)经由第二总线系统(B2)(控制总线, 数据总线,地址总线)连接存储器模块(1003 )。 CPU (1001) via a first bus system (Bl) (e.g., a control bus, a data bus, address bus) connected to the memory controller, the memory controller (1002) via a second bus system (B2) (a control bus, a data bus , address bus) connected to the memory module (1003). 在图IO的示范性构架中, CPU(1001)控制存储器控制器(1002),存储器控制器(1002)控制存储器(1003, 1004)(尽管通常认为,CPU可以用来直接控制存储器,不需要使用分离的存储器控制器)。 In the exemplary framework of FIG IO, CPU (1001) controls the memory controller (1002), the memory controller (1002) controls the memory (1003, 1004) (although usually considered, the CPU can be used to directly control the memory, without using separate memory controller).

在图IO的示范性实施例中,每个存储器模块(1003 )可以代表例如一个存储体,以及给定的存储器模块(1003 )的每个存储器件(1004)可以采用本发明的页面操作模式操作。 In the exemplary embodiment of FIG IO, each memory module (1003) may represent, for example, a bank, and a given memory module (1003) of each memory device (1004) page operation mode of operation of the present invention may be employed . 在此情况下,每个存储器件(1004)在逻辑上被分成多个列块,以提供部分激活构架,然后按上述方式控制以提供页面操作。 In this case, each memory device (1004) is divided into a plurality of columns on the logical blocks, to provide a partially activated frame, then the above-described operation is controlled to provide a page. 执行页面模式存储器存取的控制电路也可以位于存储器件(1004)内。 The control circuit performs page mode memory access may also be located within the memory device (1004).

在一个优选实施例中,存储器模块的存储器件可以有x8比特结构,而另一个存储器模块的存储器件可以有x16比特结构。 In a preferred embodiment, the memory device may have memory modules x8 bit structure, the memory device of another memory module may have a x16-bit structure. 也就是,不同存储器模块可以采用不同比特结构操作。 That is, different memory modules may operate with different bit configuration.

本发明另一个实施例的存储器系统可以包括: 一个或多个分离的半导体存储器件(替代具有如图10所示的多个存储器件的存储模块), 一个中央处理单元(并且没有存储器控制器)。 Another embodiment of a memory system embodiment of the present invention may comprise: one or more separate semiconductor memory device (memory module having a plurality of alternate shown in FIG memory device 10), a central processing unit (and without a memory controller) . 在该实施例中,存储器件直接与中央处理单元通信。 In this embodiment, the memory device in communication with a central processing unit directly.

在另一个实施例中,本发明的存储器系统可以包括直接与存储器控制器通信的一个或多个分离的半导体存储器件(替代具有如图IO所示的多个存储器件的存储器模块)。 In another embodiment, the memory system of the present invention may include a controller in communication directly with a plurality of separate memory or a semiconductor memory device (memory module having a plurality of alternate memory device shown in FIG IO). 在该实施例中, 一个存储器件可以有x8比特结构,另一个存储器件可以有x16比特结构。 In this embodiment, the memory device may have a x8 bit structure, there may be another memory device x16 bit structure.

尽管已经结合附图说明了示范性实施例,但是应当理解本发明不限于这里所述的严格的系统和方法实施例,并且在不背离本发明精神和范围的条件下,本领域熟练技术人员可以实现各种其它的变化和修改。 While there has been described in conjunction with the accompanying drawings of exemplary embodiments, it is to be understood that the present invention is not limited to the rigorous systems and methods according to embodiments herein, and without departing from the spirit and scope of the present invention, those skilled in the art can that various other changes and modifications. 所有此类变化和修改被包含在所附权利要求所定义的本发明的范围之内。 All such variations and modifications are included within the scope of the invention as defined by the appended claims of.

Claims (35)

  1. 1、一种存取存储器件中数据的方法,包括以下步骤:激活对应于第一地址的第一字线,以执行数据存取操作;接收第一地址后的第二地址;如果第二地址与第一地址相同,则生成页面模式标记信号,以保持对应于第一地址的第一字线的已激活状态,同时激活对应于第二地址的第二字线,如果第二地址与第一地址不同,则第一字线被预充电;和响应页面模式标记信号的禁止,去激活第一和第二字线。 1. A method for accessing data in a memory device, comprising the steps of: activating the first word line corresponding to the first address, to perform data access operation; receiving a first address a second address; if the second address Like the first address, the page mode flag signal is generated to maintain the word line corresponding to the first address of a first active state, while activating the second word line corresponding to the second address, a second address if the first different addresses, the first word line is precharged; page mode, and prohibit flag in response to the signal, to activate the first and second word lines.
  2. 2、 根据权利要求1所述的方法,其中生成页面模式标记信号的步骤包括以下步骤:使用一个比较器将第二地址与第一地址相比较,以确定第一地址与第二地址是否相同;如果第一地址和第二地址相同,则从比较器输出页面模式标记信号。 2. The method according to claim 1, wherein the step of generating a page mode flag signal includes the steps of: using a second address comparator compared with the first address, to determine a first address and the second address are the same; If the first address and the second address are the same, the output from the comparator page mode flag signal.
  3. 3、 根据权利要求1所述的方法,其中保持第一字线的已激活状态的步骤包括:在激活页面模式标记信号的同时,避免具有相同地址的第一字线的预充电操作。 Step 3. The method according to claim 1, wherein remain activated first word line comprising: simultaneously activating the page mode flag signals, to avoid the precharge operation having the same first word line address.
  4. 4、 根据权利要求1所述的方法,其中数据存取操作是写操作,该方法还包括以下步骤:生成写信号;和将写命令信号延迟预定的第一延迟时间。 4. The method of claim 1, wherein the data access operation is a write operation, the method further comprising the steps of: generating a write signal; and a write command signal delayed by the predetermined first delay time.
  5. 5、 根据权利要求4所述的方法,还包括将页面模式标记信号延迟预定的第二时间,以生成延迟的页面模式标记信号的步骤。 5. The method as claimed in claim 4, further comprising a page mode flag predetermined second time delay signal to delay the step of generating a page mode flag signal.
  6. 6、 根据权利要求5所述的方法,其中延迟的页面模式标记信号避免至少一次预充电操作。 6. The method of claim 5, wherein the page mode flag signal delay to avoid at least one pre-charge operation.
  7. 7、 根据权利要求1所述的方法,其中第一地址包括行地址。 7. The method of claim 1, wherein the first address comprises a row address.
  8. 8、 根据权利要求7所述的方法,其中第一地址还包括列块选择地址。 8. The method of claim 7, wherein the address further comprises a first column block select address.
  9. 9、 根据权利要求8所述的方法,其中列块选择地址包括列地址或者行地址。 9. The method of claim 8, wherein the column block select address comprises a row address or a column address.
  10. 10、 一种半导体存储器件,包括: 包含多个存储块的存储单元阵列;命令译码器,用于对命令信号译码,并输出已译码命令信号以执行数据存取操作;行地址比较器,用于将对应于已激活第一字线的第一地址与第一地址之后接收的第二地址进行比较,如果第一地址与第二地址相同,则生成页面模式标记信号,如果第二地址与第一地址不同,则第一字线被预充电; 预充电控制电路,用于控制预充电操作,其中预充电控制电路响应页面模式标记信号,防止已激活第一字线的预充电操作,同时激活对应于第二地址的第二字线以执行数据存取操作;以及命令移位器电路,可操作地连接到命令译码器和行地址比较器的输出端,其中响应从行地址比较器输出的页面模式标记信号,所述命令移位器将命令译码器输出的写命令信号延迟预定的第一延迟时间。 10. A semiconductor memory device, comprising: a memory cell array comprising a plurality of memory blocks; comparing a row address; command decoder for decoding command signals, and outputs the decoded command signal to perform a data access operation is, for a second address corresponding to the received first address after activation of the first address of the first word line are compared, if the first address and the second address are the same, the page mode flag signal is generated, if the second address different from the first address, the first word line is precharged; precharge control circuit for controlling the pre-charging operation, wherein the control circuit is responsive to the precharge page mode flag signal is activated to prevent the first word line precharge operation while activating the second word line corresponding to the second address to perform a data access operation; and a command shifter circuit, operatively connected to the output of the command decoder and a row address comparator, wherein in response to a row address from the page mode flag output signal of the comparator, the shift command is a command write command decoder output signal delayed by a predetermined first delay time.
  11. 11、 根据权利要求IO所述的器件,行地址比较器包括:将第二地址与第一地址相比较,以确定第一地址与第二地址是否相同的装置;如果第一地址和第二地址相同,则从比较器输出页面^t式标记信号的装置。 11. The device according to claim IO, the row address comparator comprising: a first address and the second address is compared to determine a first address and the second address is the same means; if the first and second address same, the output from the comparator means ^ t page formula marker signal.
  12. 12、 根据权利要求IO所述的器件,其中命令移位器电路包括延迟写命令信号的时钟移位器,所述时钟移位器包括多个串联连接的反相器。 12, the device according to claim IO wherein the shifter circuit comprises a delay command to the write command signal shifter clock, the clock shifter comprises a plurality of serially connected inverters.
  13. 13、 根据权利要求IO所述的器件,其中命令移位器电路包括延迟写命令信号的时钟移位器,所述时钟移位器包括多个串联连接的触发器。 13, the device according to claim IO wherein the shifter circuit comprises a delay command to the write command signal shifter clock, the clock shifter comprises a plurality of flip-flops connected in series.
  14. 14、 根据权利要求IO所述的器件,其中响应写命令信号,所述预充电控制电路将页面模式标记信号延迟预定的第二延迟时间,以生成延迟的页面才莫式标记信号。 14, the IO device as claimed in claim, wherein in response to the write command signal, the precharge control circuit page mode flag signal delay of a second predetermined delay time to generate a delayed signal mark pages only Mohs.
  15. 15、 根据权利要求14所述的器件,其中延迟的页面模式标记信号已激活第一字线的预充电操作。 15. The device of claim 14, wherein the page mode flag delay signal is a precharge operation of the first activated word line.
  16. 16、 根据权利要求IO所述的器件,其中存储单元阵列包括部分激活构 16. The device according to claim IO wherein the memory cell array includes partially activated configuration
  17. 17、 根据权利要求16所述的器件,其中数据存取操作包括页面模式操作,在页面模式操作中,对相同存储块或不同存储块中具有相同行地址的一个或多个存储单元存取数据。 17. The device of claim 16, wherein the data access operation comprises a page mode operation, having the same row address or a plurality of data storage units access the same memory block or different blocks in a page mode memory operation .
  18. 18、 根据权利要求17所述的器件,其中使用脉冲串模式存取数据。 18. The device of claim 17, wherein the burst-mode data access.
  19. 19、 一种存储器系统,包括:一个存储器控制器,用于生成多个命令和地址信号;和接收命令和地址信号的第一存储模块,其中第一存储模块包括第一存储器件,所述第一存储器件包括:一个在逻辑上分成多个存储块的存储单元阵列;命令译码器,用于对命令信号译码,并输出已译码命令信号以执行数据存取操作;行地址比较器,用于将对应于已激活第一字线的第一地址与第一地址之后接收的第二地址进行比较,如果第一地址与第二地址相同,则生成页面模式标记信号,如杲第二地址与第一地址不同,则第一字线被预充电;预充电控制电路,用于控制预充电操作,其中预充电控制电路响应页面模式标记信号,防止已激活第一字线的预充电操作,同时激活对应于第二地址的第二字线以执行数据存取操作;以及命令移位器电路,可操作地连接到命令译 19. A memory system, comprising: a memory controller for generating a plurality of command and address signals; and receiving command and address signals of the first storage module, wherein the first storage module comprises a first memory device, the second a memory device comprising: a storage unit is logically divided into a plurality of memory array blocks; command decoder for decoding command signals, and outputs the decoded command signal to perform the data access operation; row address comparator , corresponding to a second address received after activation of the first address and the first address of the first word line are compared, if the first address and the second address are the same, the page mode flag signal is generated, as a second Gao address different from the first address, the first word line is precharged; precharge control circuit for controlling the pre-charging operation, wherein the control circuit is responsive to the precharge page mode flag signal is activated to prevent the first word line precharge operation while activating the second word line corresponding to the second address to perform a data access operation; and a command shifter circuit, operatively connected to the command translation 器和行地址比较器的输出端,其中响应从行地址比较器输出的页面模式标记信号,所述命令移位器将命令译码器输出的写命令信号延迟预定的第一延迟时间。 And the output of the row address comparator, wherein the page mode flag in response to a signal output from the row address comparator, a shift command is a command write command decoder output signal delayed by a predetermined first delay time.
  20. 20、 根据权利要求19所述的存储器系统,其中存储器系统包括部分激活构架,其中第一存储器件的每个存储块由块地址单独地寻址。 20. The memory system of claim 19, wherein the memory system comprises a partial activation framework, each memory block of the first memory device wherein the individually addressed by a block address.
  21. 21、 根据权利要求19所述的存储器系统,还包括含有第二存储器件的第二存储模块,其中第一存储器件具有第一比特结构,第二存储器件具有第二比特结构,其中第一比特结构和第二比特结构不相同。 21. The memory system according to claim 19, further comprising a second memory module comprising a second memory device, wherein a first bit of the first memory device has a structure, a second storage device having a second configuration bit, wherein a first bit structure and the second structure is not the same bit.
  22. 22、 一种存储器系统,包括:存储器控制器,用于生成多个命令和地址信号;和接收命令和地址信号的第一存储器件,其中第一存储器件包括: 在逻辑上分成多个存储块的存储单元阵列; 命令译码器,用于对命令信号译码,并输出已译码命令信号以执行数据存取操作;行地址比较器,用于将对应于已激活第一字线的第一地址与第一地址之后接收的第二地址进行比较,如果第一地址与第二地址相同,则生成页面模式标记信号,如果第二地址与第一地址不同,则第一字线被预充电;预充电控制电路,用于控制预充电操作,其中预充电控制电路响应页面模式标记信号,防止已激活第一字线的预充电操作,同时激活对应于第二地址的第二字线以执行数据存取操作;以及命令移位器电路,可操作地连接到命令译码器和行地址比较器的输出端,其中响应从行 22. A memory system, comprising: a memory controller for generating a plurality of command and address signals; and a first memory device receives command and address signals, wherein the first memory device comprising: a memory divided into a plurality of logical blocks a memory cell array; second row address comparator for comparing the corresponding first word line is activated; command decoder for decoding command signals, and outputs the decoded command signal to perform a data access operation receiving a second address after the address is compared with the first address, if the first address and the second address are the same, the page mode flag signal is generated if the second address is different from the first address, the first word line is precharged ; precharge control circuit for controlling the pre-charging operation, wherein the precharge control circuit mode flag signal in response to the page, the first word line is activated to prevent the precharge operation while activating the second word line corresponding to the address to perform a second data access operation; and a command shifter circuit, operatively connected to the output of the command decoder and a row address comparator, wherein the response from the line 址比较器输出的页面模式标记信号,所述命令移位器将命令译码器输出的写命令信号延迟预定的第一延迟时间。 Page mode flag address comparator output signal, said command shifter command write command decoder output signal delayed by a predetermined first delay time.
  23. 23、 根据权利要求22所述的存储器系统,还包括第二存储器件,其中第一存储器件具有第一比特结构,第二存储器件具有第二比特结构。 23. The memory system according to claim 22, further comprising a second memory device, wherein a first bit of the first memory device has a structure, a second member having a second memory bit structure.
  24. 24、 一种存储器系统,包括:中央处理单元,用于生成多个命令和地址信号;和接收命令和地址信号的第一存储模块,其中第一存储模块包括第一存储器件,所述第一存储器件包括:在逻辑上分成多个存储块的存储单元阵列;命令译码器,用于对命令信号译码,并输出已译码命令信号以执行数据存取操作;行地址比较器,用于将对应于已激活第一字线的第一地址与第一地址之后接收的第二地址进行比较,如果第一地址与第二地址相同,则生成页面模式标记信号,如果第二地址与第一地址不同,则第一字线被预充电;预充电控制电路,用于控制预充电操作,其中预充电控制电路响应页面模式标记信号,防止已激活第一字线的预充电操作,同时激活对应于第二地址的第二字线以执行数据存取操作;以及命令移位器电路,可操作地连接到命令译码器和行 24. A memory system, comprising: a central processing unit, for generating a plurality of command and address signals; and receiving command and address signals of the first storage module, wherein the first storage module comprises a first memory device, the first memory device comprising: logically divided into a plurality of memory cell array of memory blocks; command decoder for decoding command signals, and outputs the decoded command signal to perform the data access operation; row address comparator, with in the address corresponding to the second received after activation of the first address and the first address of the first word line are compared, if the first address and the second address are the same, the page mode flag signal is generated, if the first and second address a different address, the first word line is precharged; precharge control circuit for controlling the pre-charging operation, wherein the precharge control circuit mode flag signal in response to the page, the first word line is activated to prevent the precharge operation while activating a second word line corresponding to a second address to perform a data access operation; and a command shifter circuit, operatively connected to the command decoder and row 址比较器的输出端,其中响应从行地址比较器输出的页面模式标记信号,所述命令移位器将命令译码器输出的写命令信号延迟预定的第一延迟时间。 Address comparator output terminal, wherein the page mode flag in response to a signal output from the row address comparator, a shift command is a command write command decoder output signal delayed by a predetermined first delay time.
  25. 25、 根据权利要求24所述的存储器系统,还包括含有第二存储器件的第二存储模块。 25. The memory system of claim 24, further comprising a second memory module comprising a second memory device.
  26. 26、 根据权利要求25所述的存储器系统,其中第一存储器件具有第一比特结构,第二存储器件具有第二比特结构,其中第一比特结构和第二比特结构不相同。 26. The memory system according to claim 25, wherein a first bit of the first memory device has a structure, a second storage device having a second configuration bit, wherein the first structure and the second bit configuration bits are not the same.
  27. 27、 根据权利要求24所述的存储器系统,其中中央处理单元是网络处理单元(NPU)。 27. The memory system of claim 24, wherein the central processing unit is a network processing unit (NPU).
  28. 28、 一种存储器系统,包括:中央处理单元,用于生成多个命令和地址信号;和接收命令和地址信号的第一存储器件,其中第一存储器具有一第一比特结构;第一存储器件包括:在逻辑上分成多个存储块的存储单元阵列;命令译码器,用于对命令信号译码,并输出已译码命令信号以执行数据存取操作;行地址比较器,用于将对应于已激活第一字线的第一地址与第一地址之后接收的第二地址进行比较,如果第一地址与第二地址相同,则生成页面模式标记信号,如果第二地址与第一地址不同,则第一字线被预充电;预充电控制电路,用于控制预充电操作,其中预充电控制电路响应页面模式标记信号,防止已激活第一字线的预充电操作,同时激活对应于第二地址的第二字线以执行数据存取操作;以及命令移位器电路,可操作地连接到命令译码器和行地址 28. A memory system, comprising: a central processing unit, for generating a plurality of command and address signals; and a first memory device receives command and address signals, wherein the first memory having a first bit structure; a first memory device comprising: logically divided into a plurality of memory cell array of memory blocks; command decoder for decoding command signals, and outputs the decoded command signal to perform the data access operation; row address comparator for after the second address received corresponds to the first address and the first address of the first word line is activated, and if the first address and the second address are the same, the page mode flag signal is generated, if a first address to the second address different from, the first word line is precharged; precharge control circuit for controlling the pre-charging operation, wherein the precharge control circuit mode flag signal in response to the page, the first word line is activated to prevent the precharge operation while activating the corresponding a second address of the second word line to perform a data access operation; and a command shifter circuit, operatively connected to a command decoder and a row address 较器的输出端,其中响应从行地址比较器输出的页面模式标记信号,所述命令移位器将命令"^码器输出的写命令信号延迟预定的第一延迟时间。 The output of the comparator, wherein in response to the page mode flag signal output from the row address comparator, a shift command is a command "^ write command signal delayed by the predetermined code outputted from the first delay time.
  29. 29、 根据权利要求28所述的存储器系统,还包括具有第二比特结构的第二存储器件,其中第一比特结构和第二比特结构不相同。 29. The memory system of claim 28, further comprising a second storage device having a second configuration bit, wherein the first structure and the second bit configuration bits are not the same.
  30. 30、 根据权利要求28所述的存储器系统,其中中央处理单元是网络处理单元(NPU)。 30. The memory system of claim 28, wherein the central processing unit is a network processing unit (NPU).
  31. 31、 一种存取存储器件中数据的方法,所述存储器件包括被分成多个存储块的存储器阵列,该方法包括以下步骤:(a )输入第一行地址和第一存储块选择地址;(b) 选择对应于第一存储块选择地址的存储器阵列中第一存储块,激活对应于第一行地址的已选择第一存储块的第一字线以执行数据存取操作;(c) 输入第二行地址和第二存储块选择地址;(d) 将第二行地址与第一行地址进行比较,如果第二行地址和第一行地址相同,生成避免第一字线预充电的控制信号,以及选择对应于第二存储块选择地址的存储器阵列中的第二存储块,并激活对应于第二行地址的已选择的第二存储块的第二字线;(e) 在每个随后输入的行地址与最新输入的行地址相同时,保持控制信号处于启动状态,以此避免去激活从第一已激活字线开始的、具有相同地址的先前激活的字线,(f) 31. A method of accessing data in a memory device, the memory device comprises a memory array is divided into a plurality of memory blocks, the method comprising the steps of: (a) a first input row address and a first memory block selection address; (b) selecting a first memory block corresponding to the selected memory array address in the first memory block, the activation of the row address corresponding to the first selected first word line of the first memory blocks to perform a data access operation; (c) input of a second row address and a second memory block selection address; (d) a second row address is compared with a first row address, if the second row address and a first row address are the same, generating a first word line precharge avoid the control signal, and selecting the second memory block corresponding to a second selected memory block of the memory array addresses and activates corresponding to a second selected word line of the second memory block of the second row address; (e) each a row address and row address of the latest input a subsequent input phase while maintaining the control signal is active, thereby avoiding the deactivation of the first active word line from the beginning, previously activated word line has the same address, (f) 随后输入的行地址与最新输入的行地址不相同时,禁止控制信号,以去激活具有相同行地址的在前激活的字线。 Subsequently inputted row address with the row address is not the same as the latest input, a control prohibition signal to deactivate the row having the same first address activated word line.
  32. 32、 根据权利要求31所述的方法,其中第一和第二已选择存储块是相同的。 32. The method of claim 31, wherein the first and second selected memory block are the same.
  33. 33、 根据权利要求31所述的方法,其中输入第一行地址和第一存储块选择地址的步骤包括在第一时钟周期同步地输入第一激活命令与第一行地址和第一存储块选择地址,该方法还包括以下步骤:在第一时钟周期之后的第二时钟内同步地输入第一数据存取命令和第一列线地址;和在第二时钟周期之后的第三时钟周期内同步地输入第二激活命令与第二行地址和第二存储块选择地址。 33. The method of claim 31, wherein the input of the first row address and the selected address input block comprises the step of storing a first command to select a first activation of the first row and the first memory block address in synchronization with a first clock cycle address, the method further comprising the steps of: inputting the first clock cycle after the second clock synchronization first data access commands and a first column address lines; and a third clock period following the second clock cycle synchronization the second input of the second command to activate a row address and a second memory block selection address.
  34. 34、 根据权利要求33所述的方法,其中第一数据存取命令是写命令, 其中该方法还包括以下步骤:将写命令延迟第一预定时段,以延迟对应于第一行地址的第一字线的激活,并启动在前激活的其地址不同于第一行地址的字线的预充电。 34. The method of claim 33, wherein the first data access command is a write command, wherein the method further comprises the steps of: delaying a first predetermined period of time a write command to a first delay corresponding to a first row address activation of the word line and the precharge start address is different from its previous activation of the first row address of the word line.
  35. 35、 根据权利要求34所述的方法,还包括将控制信号的输出延迟预定时间以解决第一字线的被延迟激活的步骤。 35. The method of claim 34, further comprising the output control signal by a predetermined time in order to solve the step of the first word line is activated delayed.
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